2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/ide.h>
17 #include <linux/init.h>
21 #define DRV_NAME "ns87415"
24 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
26 * which use the integrated NS87514 cell for CD-ROM support.
27 * i.e we have to support for CD-ROM installs.
28 * See drivers/parisc/superio.c for more gory details.
30 #include <asm/superio.h>
32 #define SUPERIO_IDE_MAX_RETRIES 25
34 /* Because of a defect in Super I/O, all reads of the PCI DMA status
35 * registers, IDE status register and the IDE select register need to be
38 static u8 superio_ide_inb (unsigned long port)
41 int retries = SUPERIO_IDE_MAX_RETRIES;
43 /* printk(" [ reading port 0x%x with retry ] ", port); */
49 } while (tmp == 0 && retries-- > 0);
54 static u8 superio_read_status(ide_hwif_t *hwif)
56 return superio_ide_inb(hwif->io_ports.status_addr);
59 static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
64 static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
66 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
67 struct ide_taskfile *tf = &cmd->tf;
69 /* be sure we're looking at the low order bits */
70 outb(ATA_DEVCTL_OBS, io_ports->ctl_addr);
72 if (cmd->tf_flags & IDE_TFLAG_IN_ERROR)
73 tf->error = inb(io_ports->feature_addr);
74 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
75 tf->nsect = inb(io_ports->nsect_addr);
76 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
77 tf->lbal = inb(io_ports->lbal_addr);
78 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
79 tf->lbam = inb(io_ports->lbam_addr);
80 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
81 tf->lbah = inb(io_ports->lbah_addr);
82 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
83 tf->device = superio_ide_inb(io_ports->device_addr);
85 if (cmd->tf_flags & IDE_TFLAG_LBA48) {
86 outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr);
88 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR)
89 tf->hob_error = inb(io_ports->feature_addr);
90 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
91 tf->hob_nsect = inb(io_ports->nsect_addr);
92 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
93 tf->hob_lbal = inb(io_ports->lbal_addr);
94 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
95 tf->hob_lbam = inb(io_ports->lbam_addr);
96 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
97 tf->hob_lbah = inb(io_ports->lbah_addr);
101 static const struct ide_tp_ops superio_tp_ops = {
102 .exec_command = ide_exec_command,
103 .read_status = superio_read_status,
104 .read_altstatus = ide_read_altstatus,
105 .write_devctl = ide_write_devctl,
107 .tf_load = ide_tf_load,
108 .tf_read = superio_tf_read,
110 .input_data = ide_input_data,
111 .output_data = ide_output_data,
114 static void __devinit superio_init_iops(struct hwif_s *hwif)
116 struct pci_dev *pdev = to_pci_dev(hwif->dev);
118 u8 port = hwif->channel, tmp;
120 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
122 /* Clear error/interrupt, enable dma */
123 tmp = superio_ide_inb(dma_stat);
124 outb(tmp | 0x66, dma_stat);
127 #define superio_dma_sff_read_status ide_dma_sff_read_status
130 static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
133 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
134 * the IRQ associated with the port,
135 * and selects either PIO or DMA handshaking for the next I/O operation.
137 static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
139 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
144 local_irq_save(flags);
147 /* Adjust IRQ enable bit */
148 bit = 1 << (8 + hwif->channel);
150 if (drive->dev_flags & IDE_DFLAG_PRESENT)
155 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
156 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
157 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
158 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
164 * Don't change DMA engine settings while Write Buffers
167 (void) pci_read_config_byte(dev, 0x43, &stat);
168 while (stat & 0x03) {
170 (void) pci_read_config_byte(dev, 0x43, &stat);
174 (void) pci_write_config_dword(dev, 0x40, new);
177 * And let things settle...
182 local_irq_restore(flags);
185 static void ns87415_selectproc (ide_drive_t *drive)
187 ns87415_prepare_drive(drive,
188 !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
191 static void ns87415_dma_start(ide_drive_t *drive)
193 ns87415_prepare_drive(drive, 1);
194 ide_dma_start(drive);
197 static int ns87415_dma_end(ide_drive_t *drive)
199 ide_hwif_t *hwif = drive->hwif;
200 u8 dma_stat = 0, dma_cmd = 0;
202 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
203 /* get DMA command mode */
204 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
206 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
207 /* from ERRATA: clear the INTR & ERROR bits */
208 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
209 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
211 ns87415_prepare_drive(drive, 0);
213 /* verify good DMA status */
214 return (dma_stat & 7) != 4;
217 static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
219 struct pci_dev *dev = to_pci_dev(hwif->dev);
220 unsigned int ctrl, using_inta;
228 * We cannot probe for IRQ: both ports share common IRQ on INTA.
229 * Also, leave IRQ masked during drive probing, to prevent infinite
230 * interrupts from a potentially floating INTA..
232 * IRQs get unmasked in selectproc when drive is first used.
234 (void) pci_read_config_dword(dev, 0x40, &ctrl);
235 (void) pci_read_config_byte(dev, 0x09, &progif);
236 /* is irq in "native" mode? */
237 using_inta = progif & (1 << (hwif->channel << 1));
239 using_inta = ctrl & (1 << (4 + hwif->channel));
241 hwif->select_data = hwif->mate->select_data;
243 hwif->select_data = (unsigned long)
244 &ns87415_control[ns87415_count++];
245 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
247 ctrl &= ~(1 << 6); /* unmask INTA */
248 *((unsigned int *)hwif->select_data) = ctrl;
249 (void) pci_write_config_dword(dev, 0x40, ctrl);
252 * Set prefetch size to 512 bytes for both ports,
253 * but don't turn on/off prefetching here.
255 pci_write_config_byte(dev, 0x55, 0xee);
259 * XXX: Reset the device, if we don't it will not respond to
260 * SELECT_DRIVE() properly during first ide_probe_port().
263 outb(12, hwif->io_ports.ctl_addr);
265 outb(8, hwif->io_ports.ctl_addr);
268 stat = hwif->tp_ops->read_status(hwif);
271 } while ((stat & ATA_BUSY) && --timeout);
276 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
281 outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
284 static const struct ide_port_ops ns87415_port_ops = {
285 .selectproc = ns87415_selectproc,
288 static const struct ide_dma_ops ns87415_dma_ops = {
289 .dma_host_set = ide_dma_host_set,
290 .dma_setup = ide_dma_setup,
291 .dma_start = ns87415_dma_start,
292 .dma_end = ns87415_dma_end,
293 .dma_test_irq = ide_dma_test_irq,
294 .dma_lost_irq = ide_dma_lost_irq,
295 .dma_timer_expiry = ide_dma_sff_timer_expiry,
296 .dma_sff_read_status = superio_dma_sff_read_status,
299 static const struct ide_port_info ns87415_chipset __devinitdata = {
301 .init_hwif = init_hwif_ns87415,
302 .port_ops = &ns87415_port_ops,
303 .dma_ops = &ns87415_dma_ops,
304 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
305 IDE_HFLAG_NO_ATAPI_DMA,
308 static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
310 struct ide_port_info d = ns87415_chipset;
312 #ifdef CONFIG_SUPERIO
313 if (PCI_SLOT(dev->devfn) == 0xE) {
314 /* Built-in - assume it's under superio. */
315 d.init_iops = superio_init_iops;
316 d.tp_ops = &superio_tp_ops;
319 return ide_pci_init_one(dev, &d, NULL);
322 static const struct pci_device_id ns87415_pci_tbl[] = {
323 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
326 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
328 static struct pci_driver ns87415_pci_driver = {
329 .name = "NS87415_IDE",
330 .id_table = ns87415_pci_tbl,
331 .probe = ns87415_init_one,
332 .remove = ide_pci_remove,
333 .suspend = ide_pci_suspend,
334 .resume = ide_pci_resume,
337 static int __init ns87415_ide_init(void)
339 return ide_pci_register_driver(&ns87415_pci_driver);
342 static void __exit ns87415_ide_exit(void)
344 pci_unregister_driver(&ns87415_pci_driver);
347 module_init(ns87415_ide_init);
348 module_exit(ns87415_ide_exit);
350 MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
351 MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
352 MODULE_LICENSE("GPL");