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   1 /*
   2  * linux/drivers/ide/mips/au1xxx-ide.c  version 01.30.00        Aug. 02 2005
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   6  *
   7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   8  *
   9  * This program is free software; you can redistribute it and/or modify it under
  10  * the terms of the GNU General Public License as published by the Free Software
  11  * Foundation; either version 2 of the License, or (at your option) any later
  12  * version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  23  * POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the GNU General Public License along with
  26  * this program; if not, write to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  30  *       Interface and Linux Device Driver" Application Note.
  31  */
  32 #undef REALLY_SLOW_IO           /* most systems can safely undef this */
  33
  34 #include <linux/types.h>
  35 #include <linux/module.h>
  36 #include <linux/kernel.h>
  37 #include <linux/delay.h>
  38 #include <linux/platform_device.h>
  39
  40 #include <linux/init.h>
  41 #include <linux/ide.h>
  42 #include <linux/sysdev.h>
  43
  44 #include <linux/dma-mapping.h>
  45
  46 #include "ide-timing.h"
  47
  48 #include <asm/io.h>
  49 #include <asm/mach-au1x00/au1xxx.h>
  50 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  51
  52 #include <asm/mach-au1x00/au1xxx_ide.h>
  53
  54 #define DRV_NAME        "au1200-ide"
  55 #define DRV_VERSION     "1.0"
  56 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  57
  58 /* enable the burstmode in the dbdma */
  59 #define IDE_AU1XXX_BURSTMODE    1
  60
  61 static _auide_hwif auide_hwif;
  62 static int dbdma_init_done;
  63
  64 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  65
  66 void auide_insw(unsigned long port, void *addr, u32 count)
  67 {
  68         _auide_hwif *ahwif = &auide_hwif;
  69         chan_tab_t *ctp;
  70         au1x_ddma_desc_t *dp;
  71
  72         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  73                            DDMA_FLAGS_NOIE)) {
  74                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  75                 return;
  76         }
  77         ctp = *((chan_tab_t **)ahwif->rx_chan);
  78         dp = ctp->cur_ptr;
  79         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  80                 ;
  81         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  82 }
  83
  84 void auide_outsw(unsigned long port, void *addr, u32 count)
  85 {
  86         _auide_hwif *ahwif = &auide_hwif;
  87         chan_tab_t *ctp;
  88         au1x_ddma_desc_t *dp;
  89
  90         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  91                              count << 1, DDMA_FLAGS_NOIE)) {
  92                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  93                 return;
  94         }
  95         ctp = *((chan_tab_t **)ahwif->tx_chan);
  96         dp = ctp->cur_ptr;
  97         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  98                 ;
  99         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
 100 }
 101
 102 #endif
 103
 104 static void auide_tune_drive(ide_drive_t *drive, byte pio)
 105 {
 106         int mem_sttime;
 107         int mem_stcfg;
 108         u8 speed;
 109
 110         /* get the best pio mode for the drive */
 111         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 112
 113         printk(KERN_INFO "%s: setting Au1XXX IDE to PIO mode%d\n",
 114                drive->name, pio);
 115
 116         mem_sttime = 0;
 117         mem_stcfg  = au_readl(MEM_STCFG2);
 118
 119         /* set pio mode! */
 120         switch(pio) {
 121         case 0:
 122                 mem_sttime = SBC_IDE_TIMING(PIO0);
 123
 124                 /* set configuration for RCS2# */
 125                 mem_stcfg |= TS_MASK;
 126                 mem_stcfg &= ~TCSOE_MASK;
 127                 mem_stcfg &= ~TOECS_MASK;
 128                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 129                 break;
 130
 131         case 1:
 132                 mem_sttime = SBC_IDE_TIMING(PIO1);
 133
 134                 /* set configuration for RCS2# */
 135                 mem_stcfg |= TS_MASK;
 136                 mem_stcfg &= ~TCSOE_MASK;
 137                 mem_stcfg &= ~TOECS_MASK;
 138                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 139                 break;
 140
 141         case 2:
 142                 mem_sttime = SBC_IDE_TIMING(PIO2);
 143
 144                 /* set configuration for RCS2# */
 145                 mem_stcfg &= ~TS_MASK;
 146                 mem_stcfg &= ~TCSOE_MASK;
 147                 mem_stcfg &= ~TOECS_MASK;
 148                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 149                 break;
 150
 151         case 3:
 152                 mem_sttime = SBC_IDE_TIMING(PIO3);
 153
 154                 /* set configuration for RCS2# */
 155                 mem_stcfg &= ~TS_MASK;
 156                 mem_stcfg &= ~TCSOE_MASK;
 157                 mem_stcfg &= ~TOECS_MASK;
 158                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 159
 160                 break;
 161
 162         case 4:
 163                 mem_sttime = SBC_IDE_TIMING(PIO4);
 164
 165                 /* set configuration for RCS2# */
 166                 mem_stcfg &= ~TS_MASK;
 167                 mem_stcfg &= ~TCSOE_MASK;
 168                 mem_stcfg &= ~TOECS_MASK;
 169                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 170                 break;
 171         }
 172
 173         au_writel(mem_sttime,MEM_STTIME2);
 174         au_writel(mem_stcfg,MEM_STCFG2);
 175
 176         speed = pio + XFER_PIO_0;
 177         ide_config_drive_speed(drive, speed);
 178 }
 179
 180 static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
 181 {
 182         int mem_sttime;
 183         int mem_stcfg;
 184
 185         mem_sttime = 0;
 186         mem_stcfg  = au_readl(MEM_STCFG2);
 187
 188         if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
 189                 auide_tune_drive(drive, speed - XFER_PIO_0);
 190                 return 0;
 191         }
 192
 193         switch(speed) {
 194 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 195         case XFER_MW_DMA_2:
 196                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 197
 198                 /* set configuration for RCS2# */
 199                 mem_stcfg &= ~TS_MASK;
 200                 mem_stcfg &= ~TCSOE_MASK;
 201                 mem_stcfg &= ~TOECS_MASK;
 202                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 203
 204                 break;
 205         case XFER_MW_DMA_1:
 206                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 207
 208                 /* set configuration for RCS2# */
 209                 mem_stcfg &= ~TS_MASK;
 210                 mem_stcfg &= ~TCSOE_MASK;
 211                 mem_stcfg &= ~TOECS_MASK;
 212                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 213
 214                 break;
 215         case XFER_MW_DMA_0:
 216                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 217
 218                 /* set configuration for RCS2# */
 219                 mem_stcfg |= TS_MASK;
 220                 mem_stcfg &= ~TCSOE_MASK;
 221                 mem_stcfg &= ~TOECS_MASK;
 222                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 223
 224                 break;
 225 #endif
 226         default:
 227                 return 1;
 228         }
 229
 230         if (ide_config_drive_speed(drive, speed))
 231                 return 1;
 232
 233         au_writel(mem_sttime,MEM_STTIME2);
 234         au_writel(mem_stcfg,MEM_STCFG2);
 235
 236         return 0;
 237 }
 238
 239 /*
 240  * Multi-Word DMA + DbDMA functions
 241  */
 242
 243 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 244
 245 static int auide_build_sglist(ide_drive_t *drive,  struct request *rq)
 246 {
 247         ide_hwif_t *hwif = drive->hwif;
 248         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 249         struct scatterlist *sg = hwif->sg_table;
 250
 251         ide_map_sg(drive, rq);
 252
 253         if (rq_data_dir(rq) == READ)
 254                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 255         else
 256                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 257
 258         return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
 259                           hwif->sg_dma_direction);
 260 }
 261
 262 static int auide_build_dmatable(ide_drive_t *drive)
 263 {
 264         int i, iswrite, count = 0;
 265         ide_hwif_t *hwif = HWIF(drive);
 266
 267         struct request *rq = HWGROUP(drive)->rq;
 268
 269         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 270         struct scatterlist *sg;
 271
 272         iswrite = (rq_data_dir(rq) == WRITE);
 273         /* Save for interrupt context */
 274         ahwif->drive = drive;
 275
 276         /* Build sglist */
 277         hwif->sg_nents = i = auide_build_sglist(drive, rq);
 278
 279         if (!i)
 280                 return 0;
 281
 282         /* fill the descriptors */
 283         sg = hwif->sg_table;
 284         while (i && sg_dma_len(sg)) {
 285                 u32 cur_addr;
 286                 u32 cur_len;
 287
 288                 cur_addr = sg_dma_address(sg);
 289                 cur_len = sg_dma_len(sg);
 290
 291                 while (cur_len) {
 292                         u32 flags = DDMA_FLAGS_NOIE;
 293                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 294
 295                         if (++count >= PRD_ENTRIES) {
 296                                 printk(KERN_WARNING "%s: DMA table too small\n",
 297                                        drive->name);
 298                                 goto use_pio_instead;
 299                         }
 300
 301                         /* Lets enable intr for the last descriptor only */
 302                         if (1==i)
 303                                 flags = DDMA_FLAGS_IE;
 304                         else
 305                                 flags = DDMA_FLAGS_NOIE;
 306
 307                         if (iswrite) {
 308                                 if(!put_source_flags(ahwif->tx_chan,
 309                                                      (void*)(page_address(sg->page)
 310                                                              + sg->offset),
 311                                                      tc, flags)) {
 312                                         printk(KERN_ERR "%s failed %d\n",
 313                                                __FUNCTION__, __LINE__);
 314                                 }
 315                         } else
 316                         {
 317                                 if(!put_dest_flags(ahwif->rx_chan,
 318                                                    (void*)(page_address(sg->page)
 319                                                            + sg->offset),
 320                                                    tc, flags)) {
 321                                         printk(KERN_ERR "%s failed %d\n",
 322                                                __FUNCTION__, __LINE__);
 323                                 }
 324                         }
 325
 326                         cur_addr += tc;
 327                         cur_len -= tc;
 328                 }
 329                 sg++;
 330                 i--;
 331         }
 332
 333         if (count)
 334                 return 1;
 335
 336  use_pio_instead:
 337         dma_unmap_sg(ahwif->dev,
 338                      hwif->sg_table,
 339                      hwif->sg_nents,
 340                      hwif->sg_dma_direction);
 341
 342         return 0; /* revert to PIO for this request */
 343 }
 344
 345 static int auide_dma_end(ide_drive_t *drive)
 346 {
 347         ide_hwif_t *hwif = HWIF(drive);
 348         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 349
 350         if (hwif->sg_nents) {
 351                 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
 352                              hwif->sg_dma_direction);
 353                 hwif->sg_nents = 0;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static void auide_dma_start(ide_drive_t *drive )
 360 {
 361 }
 362
 363
 364 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 365 {
 366         /* issue cmd to drive */
 367         ide_execute_command(drive, command, &ide_dma_intr,
 368                             (2*WAIT_CMD), NULL);
 369 }
 370
 371 static int auide_dma_setup(ide_drive_t *drive)
 372 {
 373         struct request *rq = HWGROUP(drive)->rq;
 374
 375         if (!auide_build_dmatable(drive)) {
 376                 ide_map_sg(drive, rq);
 377                 return 1;
 378         }
 379
 380         drive->waiting_for_dma = 1;
 381         return 0;
 382 }
 383
 384 static int auide_dma_check(ide_drive_t *drive)
 385 {
 386         u8 speed;
 387
 388 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 389
 390         if( dbdma_init_done == 0 ){
 391                 auide_hwif.white_list = ide_in_drive_list(drive->id,
 392                                                           dma_white_list);
 393                 auide_hwif.black_list = ide_in_drive_list(drive->id,
 394                                                           dma_black_list);
 395                 auide_hwif.drive = drive;
 396                 auide_ddma_init(&auide_hwif);
 397                 dbdma_init_done = 1;
 398         }
 399 #endif
 400
 401         /* Is the drive in our DMA black list? */
 402
 403         if ( auide_hwif.black_list ) {
 404                 drive->using_dma = 0;
 405
 406                 /* Borrowed the warning message from ide-dma.c */
 407
 408                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
 409                        drive->name, drive->id->model);
 410         }
 411         else
 412                 drive->using_dma = 1;
 413
 414         speed = ide_find_best_mode(drive, XFER_PIO | XFER_MWDMA);
 415
 416         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
 417                 return HWIF(drive)->ide_dma_on(drive);
 418
 419         return HWIF(drive)->ide_dma_off_quietly(drive);
 420 }
 421
 422 static int auide_dma_test_irq(ide_drive_t *drive)
 423 {
 424         if (drive->waiting_for_dma == 0)
 425                 printk(KERN_WARNING "%s: ide_dma_test_irq \
 426                                      called while not waiting\n", drive->name);
 427
 428         /* If dbdma didn't execute the STOP command yet, the
 429          * active bit is still set
 430          */
 431         drive->waiting_for_dma++;
 432         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 433                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 434                                      complete\n", drive->name);
 435                 return 1;
 436         }
 437         udelay(10);
 438         return 0;
 439 }
 440
 441 static int auide_dma_host_on(ide_drive_t *drive)
 442 {
 443         return 0;
 444 }
 445
 446 static int auide_dma_on(ide_drive_t *drive)
 447 {
 448         drive->using_dma = 1;
 449         return auide_dma_host_on(drive);
 450 }
 451
 452
 453 static int auide_dma_host_off(ide_drive_t *drive)
 454 {
 455         return 0;
 456 }
 457
 458 static int auide_dma_off_quietly(ide_drive_t *drive)
 459 {
 460         drive->using_dma = 0;
 461         return auide_dma_host_off(drive);
 462 }
 463
 464 static int auide_dma_lostirq(ide_drive_t *drive)
 465 {
 466         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 467         return 0;
 468 }
 469
 470 static void auide_ddma_tx_callback(int irq, void *param)
 471 {
 472         _auide_hwif *ahwif = (_auide_hwif*)param;
 473         ahwif->drive->waiting_for_dma = 0;
 474 }
 475
 476 static void auide_ddma_rx_callback(int irq, void *param)
 477 {
 478         _auide_hwif *ahwif = (_auide_hwif*)param;
 479         ahwif->drive->waiting_for_dma = 0;
 480 }
 481
 482 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 483
 484 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 485 {
 486         dev->dev_id          = dev_id;
 487         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
 488         dev->dev_intlevel    = 0;
 489         dev->dev_intpolarity = 0;
 490         dev->dev_tsize       = tsize;
 491         dev->dev_devwidth    = devwidth;
 492         dev->dev_flags       = flags;
 493 }
 494
 495 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 496
 497 static int auide_dma_timeout(ide_drive_t *drive)
 498 {
 499 //      printk("%s\n", __FUNCTION__);
 500
 501         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 502
 503         if (HWIF(drive)->ide_dma_test_irq(drive))
 504                 return 0;
 505
 506         return HWIF(drive)->ide_dma_end(drive);
 507 }
 508
 509
 510 static int auide_ddma_init(_auide_hwif *auide) {
 511
 512         dbdev_tab_t source_dev_tab, target_dev_tab;
 513         u32 dev_id, tsize, devwidth, flags;
 514         ide_hwif_t *hwif = auide->hwif;
 515
 516         dev_id   = AU1XXX_ATA_DDMA_REQ;
 517
 518         if (auide->white_list || auide->black_list) {
 519                 tsize    = 8;
 520                 devwidth = 32;
 521         }
 522         else {
 523                 tsize    = 1;
 524                 devwidth = 16;
 525
 526                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
 527                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
 528         }
 529
 530 #ifdef IDE_AU1XXX_BURSTMODE
 531         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 532 #else
 533         flags = DEV_FLAGS_SYNC;
 534 #endif
 535
 536         /* setup dev_tab for tx channel */
 537         auide_init_dbdma_dev( &source_dev_tab,
 538                               dev_id,
 539                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 540         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 541
 542         auide_init_dbdma_dev( &source_dev_tab,
 543                               dev_id,
 544                               tsize, devwidth, DEV_FLAGS_IN | flags);
 545         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 546
 547         /* We also need to add a target device for the DMA */
 548         auide_init_dbdma_dev( &target_dev_tab,
 549                               (u32)DSCR_CMD0_ALWAYS,
 550                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 551         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 552
 553         /* Get a channel for TX */
 554         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 555                                                  auide->tx_dev_id,
 556                                                  auide_ddma_tx_callback,
 557                                                  (void*)auide);
 558
 559         /* Get a channel for RX */
 560         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 561                                                  auide->target_dev_id,
 562                                                  auide_ddma_rx_callback,
 563                                                  (void*)auide);
 564
 565         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 566                                                              NUM_DESCRIPTORS);
 567         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 568                                                              NUM_DESCRIPTORS);
 569
 570         hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
 571                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
 572                                                 &hwif->dmatable_dma, GFP_KERNEL);
 573
 574         au1xxx_dbdma_start( auide->tx_chan );
 575         au1xxx_dbdma_start( auide->rx_chan );
 576
 577         return 0;
 578 }
 579 #else
 580
 581 static int auide_ddma_init( _auide_hwif *auide )
 582 {
 583         dbdev_tab_t source_dev_tab;
 584         int flags;
 585
 586 #ifdef IDE_AU1XXX_BURSTMODE
 587         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 588 #else
 589         flags = DEV_FLAGS_SYNC;
 590 #endif
 591
 592         /* setup dev_tab for tx channel */
 593         auide_init_dbdma_dev( &source_dev_tab,
 594                               (u32)DSCR_CMD0_ALWAYS,
 595                               8, 32, DEV_FLAGS_OUT | flags);
 596         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 597
 598         auide_init_dbdma_dev( &source_dev_tab,
 599                               (u32)DSCR_CMD0_ALWAYS,
 600                               8, 32, DEV_FLAGS_IN | flags);
 601         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 602
 603         /* Get a channel for TX */
 604         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 605                                                  auide->tx_dev_id,
 606                                                  NULL,
 607                                                  (void*)auide);
 608
 609         /* Get a channel for RX */
 610         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 611                                                  DSCR_CMD0_ALWAYS,
 612                                                  NULL,
 613                                                  (void*)auide);
 614
 615         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 616                                                              NUM_DESCRIPTORS);
 617         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 618                                                              NUM_DESCRIPTORS);
 619
 620         au1xxx_dbdma_start( auide->tx_chan );
 621         au1xxx_dbdma_start( auide->rx_chan );
 622
 623         return 0;
 624 }
 625 #endif
 626
 627 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 628 {
 629         int i;
 630         unsigned long *ata_regs = hw->io_ports;
 631
 632         /* FIXME? */
 633         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
 634                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
 635         }
 636
 637         /* set the Alternative Status register */
 638         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
 639 }
 640
 641 static int au_ide_probe(struct device *dev)
 642 {
 643         struct platform_device *pdev = to_platform_device(dev);
 644         _auide_hwif *ahwif = &auide_hwif;
 645         ide_hwif_t *hwif;
 646         struct resource *res;
 647         int ret = 0;
 648
 649 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 650         char *mode = "MWDMA2";
 651 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 652         char *mode = "PIO+DDMA(offload)";
 653 #endif
 654
 655         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 656         auide_hwif.dev                  = 0;
 657
 658         ahwif->dev = dev;
 659         ahwif->irq = platform_get_irq(pdev, 0);
 660
 661         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 662
 663         if (res == NULL) {
 664                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
 665                 ret = -ENODEV;
 666                 goto out;
 667         }
 668         if (ahwif->irq < 0) {
 669                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
 670                 ret = -ENODEV;
 671                 goto out;
 672         }
 673
 674         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
 675                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 676                 ret =  -EBUSY;
 677                 goto out;
 678         }
 679
 680         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
 681         if (ahwif->regbase == 0) {
 682                 ret = -ENOMEM;
 683                 goto out;
 684         }
 685
 686         /* FIXME:  This might possibly break PCMCIA IDE devices */
 687
 688         hwif                            = &ide_hwifs[pdev->id];
 689         hw_regs_t *hw                   = &hwif->hw;
 690         hwif->irq = hw->irq             = ahwif->irq;
 691         hwif->chipset                   = ide_au1xxx;
 692
 693         auide_setup_ports(hw, ahwif);
 694         memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
 695
 696         hwif->ultra_mask                = 0x0;  /* Disable Ultra DMA */
 697 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 698         hwif->mwdma_mask                = 0x07; /* Multimode-2 DMA  */
 699         hwif->swdma_mask                = 0x00;
 700 #else
 701         hwif->mwdma_mask                = 0x0;
 702         hwif->swdma_mask                = 0x0;
 703 #endif
 704
 705         hwif->noprobe = 0;
 706         hwif->drives[0].unmask          = 1;
 707         hwif->drives[1].unmask          = 1;
 708
 709         /* hold should be on in all cases */
 710         hwif->hold                      = 1;
 711
 712         hwif->mmio  = 1;
 713
 714         /* If the user has selected DDMA assisted copies,
 715            then set up a few local I/O function entry points
 716         */
 717
 718 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 719         hwif->INSW                      = auide_insw;
 720         hwif->OUTSW                     = auide_outsw;
 721 #endif
 722
 723         hwif->tuneproc                  = &auide_tune_drive;
 724         hwif->speedproc                 = &auide_tune_chipset;
 725
 726 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 727         hwif->ide_dma_off_quietly       = &auide_dma_off_quietly;
 728         hwif->ide_dma_timeout           = &auide_dma_timeout;
 729
 730         hwif->ide_dma_check             = &auide_dma_check;
 731         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
 732         hwif->dma_start                 = &auide_dma_start;
 733         hwif->ide_dma_end               = &auide_dma_end;
 734         hwif->dma_setup                 = &auide_dma_setup;
 735         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
 736         hwif->ide_dma_host_off          = &auide_dma_host_off;
 737         hwif->ide_dma_host_on           = &auide_dma_host_on;
 738         hwif->ide_dma_lostirq           = &auide_dma_lostirq;
 739         hwif->ide_dma_on                = &auide_dma_on;
 740
 741         hwif->autodma                   = 1;
 742         hwif->drives[0].autodma         = hwif->autodma;
 743         hwif->drives[1].autodma         = hwif->autodma;
 744         hwif->atapi_dma                 = 1;
 745
 746 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 747         hwif->autodma                   = 0;
 748         hwif->channel                   = 0;
 749         hwif->hold                      = 1;
 750         hwif->select_data               = 0;    /* no chipset-specific code */
 751         hwif->config_data               = 0;    /* no chipset-specific code */
 752
 753         hwif->drives[0].autodma         = 0;
 754         hwif->drives[0].autotune        = 1;    /* 1=autotune, 2=noautotune, 0=default */
 755 #endif
 756         hwif->drives[0].no_io_32bit     = 1;
 757
 758         auide_hwif.hwif                 = hwif;
 759         hwif->hwif_data                 = &auide_hwif;
 760
 761 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 762         auide_ddma_init(&auide_hwif);
 763         dbdma_init_done = 1;
 764 #endif
 765
 766         probe_hwif_init(hwif);
 767         dev_set_drvdata(dev, hwif);
 768
 769         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 770
 771  out:
 772         return ret;
 773 }
 774
 775 static int au_ide_remove(struct device *dev)
 776 {
 777         struct platform_device *pdev = to_platform_device(dev);
 778         struct resource *res;
 779         ide_hwif_t *hwif = dev_get_drvdata(dev);
 780         _auide_hwif *ahwif = &auide_hwif;
 781
 782         ide_unregister(hwif - ide_hwifs);
 783
 784         iounmap((void *)ahwif->regbase);
 785
 786         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 787         release_mem_region(res->start, res->end - res->start);
 788
 789         return 0;
 790 }
 791
 792 static struct device_driver au1200_ide_driver = {
 793         .name           = "au1200-ide",
 794         .bus            = &platform_bus_type,
 795         .probe          = au_ide_probe,
 796         .remove         = au_ide_remove,
 797 };
 798
 799 static int __init au_ide_init(void)
 800 {
 801         return driver_register(&au1200_ide_driver);
 802 }
 803
 804 static void __exit au_ide_exit(void)
 805 {
 806         driver_unregister(&au1200_ide_driver);
 807 }
 808
 809 MODULE_LICENSE("GPL");
 810 MODULE_DESCRIPTION("AU1200 IDE driver");
 811
 812 module_init(au_ide_init);
 813 module_exit(au_ide_exit);