2 * Copyright (c) 1996-2004 Russell King.
4 * Please note that this platform does not support 32-bit IDE IO.
7 #include <linux/string.h>
8 #include <linux/module.h>
9 #include <linux/ioport.h>
10 #include <linux/slab.h>
11 #include <linux/blkdev.h>
12 #include <linux/errno.h>
13 #include <linux/ide.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/scatterlist.h>
21 #include <asm/ecard.h>
23 #define DRV_NAME "icside"
25 #define ICS_IDENT_OFFSET 0x2280
27 #define ICS_ARCIN_V5_INTRSTAT 0x0000
28 #define ICS_ARCIN_V5_INTROFFSET 0x0004
29 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
30 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
31 #define ICS_ARCIN_V5_IDESTEPPING 6
33 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
34 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
35 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
36 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
37 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
38 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
39 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
40 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
41 #define ICS_ARCIN_V6_IDESTEPPING 6
44 unsigned int dataoffset;
45 unsigned int ctrloffset;
46 unsigned int stepping;
49 static struct cardinfo icside_cardinfo_v5 = {
50 .dataoffset = ICS_ARCIN_V5_IDEOFFSET,
51 .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
52 .stepping = ICS_ARCIN_V5_IDESTEPPING,
55 static struct cardinfo icside_cardinfo_v6_1 = {
56 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
57 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
58 .stepping = ICS_ARCIN_V6_IDESTEPPING,
61 static struct cardinfo icside_cardinfo_v6_2 = {
62 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
63 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
64 .stepping = ICS_ARCIN_V6_IDESTEPPING,
70 void __iomem *irq_port;
71 void __iomem *ioc_base;
74 struct ide_host *host;
77 #define ICS_TYPE_A3IN 0
78 #define ICS_TYPE_A3USER 1
80 #define ICS_TYPE_V5 15
81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
83 /* ---------------- Version 5 PCB Support Functions --------------------- */
84 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
85 * Purpose : enable interrupts from card
87 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
89 struct icside_state *state = ec->irq_data;
91 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
94 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
95 * Purpose : disable interrupts from card
97 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
99 struct icside_state *state = ec->irq_data;
101 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
104 static const expansioncard_ops_t icside_ops_arcin_v5 = {
105 .irqenable = icside_irqenable_arcin_v5,
106 .irqdisable = icside_irqdisable_arcin_v5,
110 /* ---------------- Version 6 PCB Support Functions --------------------- */
111 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
112 * Purpose : enable interrupts from card
114 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
116 struct icside_state *state = ec->irq_data;
117 void __iomem *base = state->irq_port;
121 switch (state->channel) {
123 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
124 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
127 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
128 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
133 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
134 * Purpose : disable interrupts from card
136 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
138 struct icside_state *state = ec->irq_data;
142 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
143 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
146 /* Prototype: icside_irqprobe(struct expansion_card *ec)
147 * Purpose : detect an active interrupt from card
149 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
151 struct icside_state *state = ec->irq_data;
153 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
154 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
157 static const expansioncard_ops_t icside_ops_arcin_v6 = {
158 .irqenable = icside_irqenable_arcin_v6,
159 .irqdisable = icside_irqdisable_arcin_v6,
160 .irqpending = icside_irqpending_arcin_v6,
164 * Handle routing of interrupts. This is called before
165 * we write the command to the drive.
167 static void icside_maskproc(ide_drive_t *drive, int mask)
169 ide_hwif_t *hwif = drive->hwif;
170 struct expansion_card *ec = ECARD_DEV(hwif->dev);
171 struct icside_state *state = ecard_get_drvdata(ec);
174 local_irq_save(flags);
176 state->channel = hwif->channel;
178 if (state->enabled && !mask) {
179 switch (hwif->channel) {
181 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
182 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
185 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
186 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
190 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
191 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
194 local_irq_restore(flags);
197 static const struct ide_port_ops icside_v6_no_dma_port_ops = {
198 .maskproc = icside_maskproc,
201 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
205 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
206 * There is only one DMA controller per card, which means that only
207 * one drive can be accessed at one time. NOTE! We do not enforce that
208 * here, but we rely on the main IDE driver spotting that both
209 * interfaces use the same IRQ, which should guarantee this.
213 * Configure the IOMD to give the appropriate timings for the transfer
214 * mode being requested. We take the advice of the ATA standards, and
215 * calculate the cycle time based on the transfer mode, and the EIDE
216 * MW DMA specs that the drive provides in the IDENTIFY command.
218 * We have the following IOMD DMA modes to choose from:
220 * Type Active Recovery Cycle
221 * A 250 (250) 312 (550) 562 (800)
223 * C 125 (125) 125 (375) 250 (500)
226 * (figures in brackets are actual measured timings)
228 * However, we also need to take care of the read/write active and
232 * Mode Active -- Recovery -- Cycle IOMD type
233 * MW0 215 50 215 480 A
237 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
239 int cycle_time, use_dma_info = 0;
264 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
265 * take care to note the values in the ID...
267 if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
268 cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
270 drive->drive_data = cycle_time;
272 printk("%s: %s selected (peak %dMB/s)\n", drive->name,
273 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
276 static const struct ide_port_ops icside_v6_port_ops = {
277 .set_dma_mode = icside_set_dma_mode,
278 .maskproc = icside_maskproc,
281 static void icside_dma_host_set(ide_drive_t *drive, int on)
285 static int icside_dma_end(ide_drive_t *drive)
287 ide_hwif_t *hwif = drive->hwif;
288 struct expansion_card *ec = ECARD_DEV(hwif->dev);
290 drive->waiting_for_dma = 0;
292 disable_dma(ec->dma);
294 /* Teardown mappings after DMA has completed. */
295 ide_destroy_dmatable(drive);
297 return get_dma_residue(ec->dma) != 0;
300 static void icside_dma_start(ide_drive_t *drive)
302 ide_hwif_t *hwif = drive->hwif;
303 struct expansion_card *ec = ECARD_DEV(hwif->dev);
305 /* We can not enable DMA on both channels simultaneously. */
306 BUG_ON(dma_channel_active(ec->dma));
310 static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
312 ide_hwif_t *hwif = drive->hwif;
313 struct expansion_card *ec = ECARD_DEV(hwif->dev);
314 struct icside_state *state = ecard_get_drvdata(ec);
315 unsigned int dma_mode;
317 if (cmd->tf_flags & IDE_TFLAG_WRITE)
318 dma_mode = DMA_MODE_WRITE;
320 dma_mode = DMA_MODE_READ;
323 * We can not enable DMA on both channels.
325 BUG_ON(dma_channel_active(ec->dma));
328 * Ensure that we have the right interrupt routed.
330 icside_maskproc(drive, 0);
333 * Route the DMA signals to the correct interface.
335 writeb(state->sel | hwif->channel, state->ioc_base);
338 * Select the correct timing for this drive.
340 set_dma_speed(ec->dma, drive->drive_data);
343 * Tell the DMA engine about the SG table and
346 set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
347 set_dma_mode(ec->dma, dma_mode);
349 drive->waiting_for_dma = 1;
354 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
356 /* issue cmd to drive */
357 ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
360 static int icside_dma_test_irq(ide_drive_t *drive)
362 ide_hwif_t *hwif = drive->hwif;
363 struct expansion_card *ec = ECARD_DEV(hwif->dev);
364 struct icside_state *state = ecard_get_drvdata(ec);
366 return readb(state->irq_port +
368 ICS_ARCIN_V6_INTRSTAT_2 :
369 ICS_ARCIN_V6_INTRSTAT_1)) & 1;
372 static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
374 hwif->dmatable_cpu = NULL;
375 hwif->dmatable_dma = 0;
380 static const struct ide_dma_ops icside_v6_dma_ops = {
381 .dma_host_set = icside_dma_host_set,
382 .dma_setup = icside_dma_setup,
383 .dma_exec_cmd = icside_dma_exec_cmd,
384 .dma_start = icside_dma_start,
385 .dma_end = icside_dma_end,
386 .dma_test_irq = icside_dma_test_irq,
387 .dma_timeout = ide_dma_timeout,
388 .dma_lost_irq = ide_dma_lost_irq,
391 #define icside_v6_dma_ops NULL
394 static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
399 static void icside_setup_ports(hw_regs_t *hw, void __iomem *base,
400 struct cardinfo *info, struct expansion_card *ec)
402 unsigned long port = (unsigned long)base + info->dataoffset;
404 hw->io_ports.data_addr = port;
405 hw->io_ports.error_addr = port + (1 << info->stepping);
406 hw->io_ports.nsect_addr = port + (2 << info->stepping);
407 hw->io_ports.lbal_addr = port + (3 << info->stepping);
408 hw->io_ports.lbam_addr = port + (4 << info->stepping);
409 hw->io_ports.lbah_addr = port + (5 << info->stepping);
410 hw->io_ports.device_addr = port + (6 << info->stepping);
411 hw->io_ports.status_addr = port + (7 << info->stepping);
412 hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
416 hw->chipset = ide_acorn;
419 static const struct ide_port_info icside_v5_port_info = {
420 .host_flags = IDE_HFLAG_NO_DMA,
424 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
427 struct ide_host *host;
428 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
431 base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
435 state->irq_port = base;
437 ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
440 ecard_setirq(ec, &icside_ops_arcin_v5, state);
443 * Be on the safe side - disable interrupts
445 icside_irqdisable_arcin_v5(ec, 0);
447 icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
449 host = ide_host_alloc(&icside_v5_port_info, hws);
455 ecard_set_drvdata(ec, state);
457 ret = ide_host_register(host, &icside_v5_port_info, hws);
464 ecard_set_drvdata(ec, NULL);
468 static const struct ide_port_info icside_v6_port_info __initdata = {
469 .init_dma = icside_dma_off_init,
470 .port_ops = &icside_v6_no_dma_port_ops,
471 .dma_ops = &icside_v6_dma_ops,
472 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
473 .mwdma_mask = ATA_MWDMA2,
474 .swdma_mask = ATA_SWDMA2,
478 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
480 void __iomem *ioc_base, *easi_base;
481 struct ide_host *host;
482 unsigned int sel = 0;
484 hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
485 struct ide_port_info d = icside_v6_port_info;
487 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
493 easi_base = ioc_base;
495 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
496 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
503 * Enable access to the EASI region.
508 writeb(sel, ioc_base);
510 ecard_setirq(ec, &icside_ops_arcin_v6, state);
512 state->irq_port = easi_base;
513 state->ioc_base = ioc_base;
517 * Be on the safe side - disable interrupts
519 icside_irqdisable_arcin_v6(ec, 0);
521 icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
522 icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
524 host = ide_host_alloc(&d, hws);
530 ecard_set_drvdata(ec, state);
532 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
533 d.init_dma = icside_dma_init;
534 d.port_ops = &icside_v6_port_ops;
538 ret = ide_host_register(host, &d, hws);
547 ecard_set_drvdata(ec, NULL);
553 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
555 struct icside_state *state;
559 ret = ecard_request_resources(ec);
563 state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
569 state->type = ICS_TYPE_NOTYPE;
571 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
575 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
576 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
577 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
578 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
579 ecardm_iounmap(ec, idmem);
584 switch (state->type) {
586 dev_warn(&ec->dev, "A3IN unsupported\n");
590 case ICS_TYPE_A3USER:
591 dev_warn(&ec->dev, "A3USER unsupported\n");
596 ret = icside_register_v5(state, ec);
600 ret = icside_register_v6(state, ec);
604 dev_warn(&ec->dev, "unknown interface type\n");
614 ecard_release_resources(ec);
619 static void __devexit icside_remove(struct expansion_card *ec)
621 struct icside_state *state = ecard_get_drvdata(ec);
623 switch (state->type) {
625 /* FIXME: tell IDE to stop using the interface */
627 /* Disable interrupts */
628 icside_irqdisable_arcin_v5(ec, 0);
632 /* FIXME: tell IDE to stop using the interface */
633 if (ec->dma != NO_DMA)
636 /* Disable interrupts */
637 icside_irqdisable_arcin_v6(ec, 0);
639 /* Reset the ROM pointer/EASI selection */
640 writeb(0, state->ioc_base);
644 ecard_set_drvdata(ec, NULL);
647 ecard_release_resources(ec);
650 static void icside_shutdown(struct expansion_card *ec)
652 struct icside_state *state = ecard_get_drvdata(ec);
656 * Disable interrupts from this card. We need to do
657 * this before disabling EASI since we may be accessing
658 * this register via that region.
660 local_irq_save(flags);
661 ec->ops->irqdisable(ec, 0);
662 local_irq_restore(flags);
665 * Reset the ROM pointer so that we can read the ROM
666 * after a soft reboot. This also disables access to
667 * the IDE taskfile via the EASI region.
670 writeb(0, state->ioc_base);
673 static const struct ecard_id icside_ids[] = {
674 { MANU_ICS, PROD_ICS_IDE },
675 { MANU_ICS2, PROD_ICS2_IDE },
679 static struct ecard_driver icside_driver = {
680 .probe = icside_probe,
681 .remove = __devexit_p(icside_remove),
682 .shutdown = icside_shutdown,
683 .id_table = icside_ids,
689 static int __init icside_init(void)
691 return ecard_register_driver(&icside_driver);
694 static void __exit icside_exit(void)
696 ecard_remove_driver(&icside_driver);
699 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
700 MODULE_LICENSE("GPL");
701 MODULE_DESCRIPTION("ICS IDE driver");
703 module_init(icside_init);
704 module_exit(icside_exit);