2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
20 * Note that final HPT370 support was done by force extraction of GPL.
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/blkdev.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
132 #include <asm/uaccess.h>
135 #define DRV_NAME "hpt366"
137 /* various tuning parameters */
138 #undef HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
141 static const char *bad_ata100_5[] = {
160 static const char *bad_ata66_4[] = {
176 "MAXTOR STM3320620A",
180 static const char *bad_ata66_3[] = {
185 static const char *bad_ata33[] = {
186 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
187 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
188 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
190 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
191 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
192 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
196 static u8 xfer_speeds[] = {
216 /* Key for bus clock timings
219 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
221 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
223 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
225 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
227 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
228 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
229 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
231 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
232 * task file register access.
235 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
240 static u32 forty_base_hpt36x[] = {
241 /* XFER_UDMA_6 */ 0x900fd943,
242 /* XFER_UDMA_5 */ 0x900fd943,
243 /* XFER_UDMA_4 */ 0x900fd943,
244 /* XFER_UDMA_3 */ 0x900ad943,
245 /* XFER_UDMA_2 */ 0x900bd943,
246 /* XFER_UDMA_1 */ 0x9008d943,
247 /* XFER_UDMA_0 */ 0x9008d943,
249 /* XFER_MW_DMA_2 */ 0xa008d943,
250 /* XFER_MW_DMA_1 */ 0xa010d955,
251 /* XFER_MW_DMA_0 */ 0xa010d9fc,
253 /* XFER_PIO_4 */ 0xc008d963,
254 /* XFER_PIO_3 */ 0xc010d974,
255 /* XFER_PIO_2 */ 0xc010d997,
256 /* XFER_PIO_1 */ 0xc010d9c7,
257 /* XFER_PIO_0 */ 0xc018d9d9
260 static u32 thirty_three_base_hpt36x[] = {
261 /* XFER_UDMA_6 */ 0x90c9a731,
262 /* XFER_UDMA_5 */ 0x90c9a731,
263 /* XFER_UDMA_4 */ 0x90c9a731,
264 /* XFER_UDMA_3 */ 0x90cfa731,
265 /* XFER_UDMA_2 */ 0x90caa731,
266 /* XFER_UDMA_1 */ 0x90cba731,
267 /* XFER_UDMA_0 */ 0x90c8a731,
269 /* XFER_MW_DMA_2 */ 0xa0c8a731,
270 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
271 /* XFER_MW_DMA_0 */ 0xa0c8a797,
273 /* XFER_PIO_4 */ 0xc0c8a731,
274 /* XFER_PIO_3 */ 0xc0c8a742,
275 /* XFER_PIO_2 */ 0xc0d0a753,
276 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
277 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
280 static u32 twenty_five_base_hpt36x[] = {
281 /* XFER_UDMA_6 */ 0x90c98521,
282 /* XFER_UDMA_5 */ 0x90c98521,
283 /* XFER_UDMA_4 */ 0x90c98521,
284 /* XFER_UDMA_3 */ 0x90cf8521,
285 /* XFER_UDMA_2 */ 0x90cf8521,
286 /* XFER_UDMA_1 */ 0x90cb8521,
287 /* XFER_UDMA_0 */ 0x90cb8521,
289 /* XFER_MW_DMA_2 */ 0xa0ca8521,
290 /* XFER_MW_DMA_1 */ 0xa0ca8532,
291 /* XFER_MW_DMA_0 */ 0xa0ca8575,
293 /* XFER_PIO_4 */ 0xc0ca8521,
294 /* XFER_PIO_3 */ 0xc0ca8532,
295 /* XFER_PIO_2 */ 0xc0ca8542,
296 /* XFER_PIO_1 */ 0xc0d08572,
297 /* XFER_PIO_0 */ 0xc0d08585
301 /* These are the timing tables from the HighPoint open source drivers... */
302 static u32 thirty_three_base_hpt37x[] = {
303 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
304 /* XFER_UDMA_5 */ 0x12446231,
305 /* XFER_UDMA_4 */ 0x12446231,
306 /* XFER_UDMA_3 */ 0x126c6231,
307 /* XFER_UDMA_2 */ 0x12486231,
308 /* XFER_UDMA_1 */ 0x124c6233,
309 /* XFER_UDMA_0 */ 0x12506297,
311 /* XFER_MW_DMA_2 */ 0x22406c31,
312 /* XFER_MW_DMA_1 */ 0x22406c33,
313 /* XFER_MW_DMA_0 */ 0x22406c97,
315 /* XFER_PIO_4 */ 0x06414e31,
316 /* XFER_PIO_3 */ 0x06414e42,
317 /* XFER_PIO_2 */ 0x06414e53,
318 /* XFER_PIO_1 */ 0x06814e93,
319 /* XFER_PIO_0 */ 0x06814ea7
322 static u32 fifty_base_hpt37x[] = {
323 /* XFER_UDMA_6 */ 0x12848242,
324 /* XFER_UDMA_5 */ 0x12848242,
325 /* XFER_UDMA_4 */ 0x12ac8242,
326 /* XFER_UDMA_3 */ 0x128c8242,
327 /* XFER_UDMA_2 */ 0x120c8242,
328 /* XFER_UDMA_1 */ 0x12148254,
329 /* XFER_UDMA_0 */ 0x121882ea,
331 /* XFER_MW_DMA_2 */ 0x22808242,
332 /* XFER_MW_DMA_1 */ 0x22808254,
333 /* XFER_MW_DMA_0 */ 0x228082ea,
335 /* XFER_PIO_4 */ 0x0a81f442,
336 /* XFER_PIO_3 */ 0x0a81f443,
337 /* XFER_PIO_2 */ 0x0a81f454,
338 /* XFER_PIO_1 */ 0x0ac1f465,
339 /* XFER_PIO_0 */ 0x0ac1f48a
342 static u32 sixty_six_base_hpt37x[] = {
343 /* XFER_UDMA_6 */ 0x1c869c62,
344 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
345 /* XFER_UDMA_4 */ 0x1c8a9c62,
346 /* XFER_UDMA_3 */ 0x1c8e9c62,
347 /* XFER_UDMA_2 */ 0x1c929c62,
348 /* XFER_UDMA_1 */ 0x1c9a9c62,
349 /* XFER_UDMA_0 */ 0x1c829c62,
351 /* XFER_MW_DMA_2 */ 0x2c829c62,
352 /* XFER_MW_DMA_1 */ 0x2c829c66,
353 /* XFER_MW_DMA_0 */ 0x2c829d2e,
355 /* XFER_PIO_4 */ 0x0c829c62,
356 /* XFER_PIO_3 */ 0x0c829c84,
357 /* XFER_PIO_2 */ 0x0c829ca6,
358 /* XFER_PIO_1 */ 0x0d029d26,
359 /* XFER_PIO_0 */ 0x0d029d5e
363 * The following are the new timing tables with PIO mode data/taskfile transfer
364 * overclocking fixed...
367 /* This table is taken from the HPT370 data manual rev. 1.02 */
368 static u32 thirty_three_base_hpt37x[] = {
369 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
370 /* XFER_UDMA_5 */ 0x16455031,
371 /* XFER_UDMA_4 */ 0x16455031,
372 /* XFER_UDMA_3 */ 0x166d5031,
373 /* XFER_UDMA_2 */ 0x16495031,
374 /* XFER_UDMA_1 */ 0x164d5033,
375 /* XFER_UDMA_0 */ 0x16515097,
377 /* XFER_MW_DMA_2 */ 0x26515031,
378 /* XFER_MW_DMA_1 */ 0x26515033,
379 /* XFER_MW_DMA_0 */ 0x26515097,
381 /* XFER_PIO_4 */ 0x06515021,
382 /* XFER_PIO_3 */ 0x06515022,
383 /* XFER_PIO_2 */ 0x06515033,
384 /* XFER_PIO_1 */ 0x06915065,
385 /* XFER_PIO_0 */ 0x06d1508a
388 static u32 fifty_base_hpt37x[] = {
389 /* XFER_UDMA_6 */ 0x1a861842,
390 /* XFER_UDMA_5 */ 0x1a861842,
391 /* XFER_UDMA_4 */ 0x1aae1842,
392 /* XFER_UDMA_3 */ 0x1a8e1842,
393 /* XFER_UDMA_2 */ 0x1a0e1842,
394 /* XFER_UDMA_1 */ 0x1a161854,
395 /* XFER_UDMA_0 */ 0x1a1a18ea,
397 /* XFER_MW_DMA_2 */ 0x2a821842,
398 /* XFER_MW_DMA_1 */ 0x2a821854,
399 /* XFER_MW_DMA_0 */ 0x2a8218ea,
401 /* XFER_PIO_4 */ 0x0a821842,
402 /* XFER_PIO_3 */ 0x0a821843,
403 /* XFER_PIO_2 */ 0x0a821855,
404 /* XFER_PIO_1 */ 0x0ac218a8,
405 /* XFER_PIO_0 */ 0x0b02190c
408 static u32 sixty_six_base_hpt37x[] = {
409 /* XFER_UDMA_6 */ 0x1c86fe62,
410 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
411 /* XFER_UDMA_4 */ 0x1c8afe62,
412 /* XFER_UDMA_3 */ 0x1c8efe62,
413 /* XFER_UDMA_2 */ 0x1c92fe62,
414 /* XFER_UDMA_1 */ 0x1c9afe62,
415 /* XFER_UDMA_0 */ 0x1c82fe62,
417 /* XFER_MW_DMA_2 */ 0x2c82fe62,
418 /* XFER_MW_DMA_1 */ 0x2c82fe66,
419 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
421 /* XFER_PIO_4 */ 0x0c82fe62,
422 /* XFER_PIO_3 */ 0x0c82fe84,
423 /* XFER_PIO_2 */ 0x0c82fea6,
424 /* XFER_PIO_1 */ 0x0d02ff26,
425 /* XFER_PIO_0 */ 0x0d42ff7f
429 #define HPT371_ALLOW_ATA133_6 1
430 #define HPT302_ALLOW_ATA133_6 1
431 #define HPT372_ALLOW_ATA133_6 1
432 #define HPT370_ALLOW_ATA100_5 0
433 #define HPT366_ALLOW_ATA66_4 1
434 #define HPT366_ALLOW_ATA66_3 1
436 /* Supported ATA clock frequencies */
450 u32 *clock_table[NUM_ATA_CLOCKS];
454 * Hold all the HighPoint chip information in one place.
458 char *chip_name; /* Chip name */
459 u8 chip_type; /* Chip type */
460 u8 udma_mask; /* Allowed UltraDMA modes mask. */
461 u8 dpll_clk; /* DPLL clock in MHz */
462 u8 pci_clk; /* PCI clock in MHz */
463 struct hpt_timings *timings; /* Chipset timing data */
464 u8 clock; /* ATA clock selected */
467 /* Supported HighPoint chips */
482 static struct hpt_timings hpt36x_timings = {
483 .pio_mask = 0xc1f8ffff,
484 .dma_mask = 0x303800ff,
485 .ultra_mask = 0x30070000,
487 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
488 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
489 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
490 [ATA_CLOCK_50MHZ] = NULL,
491 [ATA_CLOCK_66MHZ] = NULL
495 static struct hpt_timings hpt37x_timings = {
496 .pio_mask = 0xcfc3ffff,
497 .dma_mask = 0x31c001ff,
498 .ultra_mask = 0x303c0000,
500 [ATA_CLOCK_25MHZ] = NULL,
501 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
502 [ATA_CLOCK_40MHZ] = NULL,
503 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
504 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
508 static const struct hpt_info hpt36x __devinitdata = {
509 .chip_name = "HPT36x",
511 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
512 .dpll_clk = 0, /* no DPLL */
513 .timings = &hpt36x_timings
516 static const struct hpt_info hpt370 __devinitdata = {
517 .chip_name = "HPT370",
519 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
521 .timings = &hpt37x_timings
524 static const struct hpt_info hpt370a __devinitdata = {
525 .chip_name = "HPT370A",
526 .chip_type = HPT370A,
527 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
529 .timings = &hpt37x_timings
532 static const struct hpt_info hpt374 __devinitdata = {
533 .chip_name = "HPT374",
535 .udma_mask = ATA_UDMA5,
537 .timings = &hpt37x_timings
540 static const struct hpt_info hpt372 __devinitdata = {
541 .chip_name = "HPT372",
543 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
545 .timings = &hpt37x_timings
548 static const struct hpt_info hpt372a __devinitdata = {
549 .chip_name = "HPT372A",
550 .chip_type = HPT372A,
551 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
553 .timings = &hpt37x_timings
556 static const struct hpt_info hpt302 __devinitdata = {
557 .chip_name = "HPT302",
559 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
561 .timings = &hpt37x_timings
564 static const struct hpt_info hpt371 __devinitdata = {
565 .chip_name = "HPT371",
567 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
569 .timings = &hpt37x_timings
572 static const struct hpt_info hpt372n __devinitdata = {
573 .chip_name = "HPT372N",
574 .chip_type = HPT372N,
575 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
577 .timings = &hpt37x_timings
580 static const struct hpt_info hpt302n __devinitdata = {
581 .chip_name = "HPT302N",
582 .chip_type = HPT302N,
583 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
585 .timings = &hpt37x_timings
588 static const struct hpt_info hpt371n __devinitdata = {
589 .chip_name = "HPT371N",
590 .chip_type = HPT371N,
591 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
593 .timings = &hpt37x_timings
596 static int check_in_drive_list(ide_drive_t *drive, const char **list)
598 char *m = (char *)&drive->id[ATA_ID_PROD];
601 if (!strcmp(*list++, m))
606 static struct hpt_info *hpt3xx_get_info(struct device *dev)
608 struct ide_host *host = dev_get_drvdata(dev);
609 struct hpt_info *info = (struct hpt_info *)host->host_priv;
611 return dev == host->dev[1] ? info + 1 : info;
615 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
616 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
619 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
621 ide_hwif_t *hwif = drive->hwif;
622 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
623 u8 mask = hwif->ultra_mask;
625 switch (info->chip_type) {
627 if (!HPT366_ALLOW_ATA66_4 ||
628 check_in_drive_list(drive, bad_ata66_4))
631 if (!HPT366_ALLOW_ATA66_3 ||
632 check_in_drive_list(drive, bad_ata66_3))
636 if (!HPT370_ALLOW_ATA100_5 ||
637 check_in_drive_list(drive, bad_ata100_5))
641 if (!HPT370_ALLOW_ATA100_5 ||
642 check_in_drive_list(drive, bad_ata100_5))
648 if (ata_id_is_sata(drive->id))
655 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
658 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
660 ide_hwif_t *hwif = drive->hwif;
661 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
663 switch (info->chip_type) {
668 if (ata_id_is_sata(drive->id))
676 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
681 * Lookup the transfer mode table to get the index into
684 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
686 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
687 if (xfer_speeds[i] == speed)
690 return info->timings->clock_table[info->clock][i];
693 static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
695 ide_hwif_t *hwif = drive->hwif;
696 struct pci_dev *dev = to_pci_dev(hwif->dev);
697 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
698 struct hpt_timings *t = info->timings;
699 u8 itr_addr = 0x40 + (drive->dn * 4);
701 u32 new_itr = get_speed_setting(speed, info);
702 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
703 (speed < XFER_UDMA_0 ? t->dma_mask :
706 pci_read_config_dword(dev, itr_addr, &old_itr);
707 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
709 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
710 * to avoid problems handling I/O errors later
712 new_itr &= ~0xc0000000;
714 pci_write_config_dword(dev, itr_addr, new_itr);
717 static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
719 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
722 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
724 ide_hwif_t *hwif = drive->hwif;
725 struct pci_dev *dev = to_pci_dev(hwif->dev);
726 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
728 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
731 if (info->chip_type >= HPT370) {
734 pci_read_config_byte(dev, 0x5a, &scr1);
735 if (((scr1 & 0x10) >> 4) != mask) {
740 pci_write_config_byte(dev, 0x5a, scr1);
743 disable_irq(hwif->irq);
745 enable_irq(hwif->irq);
749 * This is specific to the HPT366 UDMA chipset
750 * by HighPoint|Triones Technologies, Inc.
752 static void hpt366_dma_lost_irq(ide_drive_t *drive)
754 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
755 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
757 pci_read_config_byte(dev, 0x50, &mcr1);
758 pci_read_config_byte(dev, 0x52, &mcr3);
759 pci_read_config_byte(dev, 0x5a, &scr1);
760 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
761 drive->name, __func__, mcr1, mcr3, scr1);
763 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
764 ide_dma_lost_irq(drive);
767 static void hpt370_clear_engine(ide_drive_t *drive)
769 ide_hwif_t *hwif = drive->hwif;
770 struct pci_dev *dev = to_pci_dev(hwif->dev);
772 pci_write_config_byte(dev, hwif->select_data, 0x37);
776 static void hpt370_irq_timeout(ide_drive_t *drive)
778 ide_hwif_t *hwif = drive->hwif;
779 struct pci_dev *dev = to_pci_dev(hwif->dev);
783 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
784 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
786 /* get DMA command mode */
787 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
789 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
790 hpt370_clear_engine(drive);
793 static void hpt370_dma_start(ide_drive_t *drive)
795 #ifdef HPT_RESET_STATE_ENGINE
796 hpt370_clear_engine(drive);
798 ide_dma_start(drive);
801 static int hpt370_dma_end(ide_drive_t *drive)
803 ide_hwif_t *hwif = drive->hwif;
804 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
806 if (dma_stat & ATA_DMA_ACTIVE) {
809 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
810 if (dma_stat & ATA_DMA_ACTIVE)
811 hpt370_irq_timeout(drive);
813 return ide_dma_end(drive);
816 /* returns 1 if DMA IRQ issued, 0 otherwise */
817 static int hpt374_dma_test_irq(ide_drive_t *drive)
819 ide_hwif_t *hwif = drive->hwif;
820 struct pci_dev *dev = to_pci_dev(hwif->dev);
824 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
826 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
830 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
831 /* return 1 if INTR asserted */
832 if (dma_stat & ATA_DMA_INTR)
838 static int hpt374_dma_end(ide_drive_t *drive)
840 ide_hwif_t *hwif = drive->hwif;
841 struct pci_dev *dev = to_pci_dev(hwif->dev);
842 u8 mcr = 0, mcr_addr = hwif->select_data;
843 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
845 pci_read_config_byte(dev, 0x6a, &bwsr);
846 pci_read_config_byte(dev, mcr_addr, &mcr);
848 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
849 return ide_dma_end(drive);
853 * hpt3xxn_set_clock - perform clock switching dance
854 * @hwif: hwif to switch
855 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
857 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
860 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
862 unsigned long base = hwif->extra_base;
863 u8 scr2 = inb(base + 0x6b);
865 if ((scr2 & 0x7f) == mode)
868 /* Tristate the bus */
869 outb(0x80, base + 0x63);
870 outb(0x80, base + 0x67);
872 /* Switch clock and reset channels */
873 outb(mode, base + 0x6b);
874 outb(0xc0, base + 0x69);
877 * Reset the state machines.
878 * NOTE: avoid accidentally enabling the disabled channels.
880 outb(inb(base + 0x60) | 0x32, base + 0x60);
881 outb(inb(base + 0x64) | 0x32, base + 0x64);
884 outb(0x00, base + 0x69);
886 /* Reconnect channels to bus */
887 outb(0x00, base + 0x63);
888 outb(0x00, base + 0x67);
892 * hpt3xxn_rw_disk - prepare for I/O
893 * @drive: drive for command
894 * @rq: block request structure
896 * This is called when a disk I/O is issued to HPT3xxN.
897 * We need it because of the clock switching.
900 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
902 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
906 * hpt37x_calibrate_dpll - calibrate the DPLL
909 * Perform a calibration cycle on the DPLL.
910 * Returns 1 if this succeeds
912 static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
914 u32 dpll = (f_high << 16) | f_low | 0x100;
918 pci_write_config_dword(dev, 0x5c, dpll);
920 /* Wait for oscillator ready */
921 for(i = 0; i < 0x5000; ++i) {
923 pci_read_config_byte(dev, 0x5b, &scr2);
927 /* See if it stays ready (we'll just bail out if it's not yet) */
928 for(i = 0; i < 0x1000; ++i) {
929 pci_read_config_byte(dev, 0x5b, &scr2);
930 /* DPLL destabilized? */
934 /* Turn off tuning, we have the DPLL set */
935 pci_read_config_dword (dev, 0x5c, &dpll);
936 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
940 static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
942 struct ide_host *host = pci_get_drvdata(dev);
943 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
944 u8 chip_type = info->chip_type;
945 u8 new_mcr, old_mcr = 0;
948 * Disable the "fast interrupt" prediction. Don't hold off
949 * on interrupts. (== 0x01 despite what the docs say)
951 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
953 if (chip_type >= HPT374)
954 new_mcr = old_mcr & ~0x07;
955 else if (chip_type >= HPT370) {
958 #ifdef HPT_DELAY_INTERRUPT
963 } else /* HPT366 and HPT368 */
964 new_mcr = old_mcr & ~0x80;
966 if (new_mcr != old_mcr)
967 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
970 static int init_chipset_hpt366(struct pci_dev *dev)
972 unsigned long io_base = pci_resource_start(dev, 4);
973 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
974 const char *name = DRV_NAME;
975 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
977 enum ata_clock clock;
979 chip_type = info->chip_type;
981 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
982 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
983 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
984 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
987 * First, try to estimate the PCI clock frequency...
989 if (chip_type >= HPT370) {
994 /* Interrupt force enable. */
995 pci_read_config_byte(dev, 0x5a, &scr1);
997 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1000 * HighPoint does this for HPT372A.
1001 * NOTE: This register is only writeable via I/O space.
1003 if (chip_type == HPT372A)
1004 outb(0x0e, io_base + 0x9c);
1007 * Default to PCI clock. Make sure MA15/16 are set to output
1008 * to prevent drives having problems with 40-pin cables.
1010 pci_write_config_byte(dev, 0x5b, 0x23);
1013 * We'll have to read f_CNT value in order to determine
1014 * the PCI clock frequency according to the following ratio:
1016 * f_CNT = Fpci * 192 / Fdpll
1018 * First try reading the register in which the HighPoint BIOS
1019 * saves f_CNT value before reprogramming the DPLL from its
1020 * default setting (which differs for the various chips).
1022 * NOTE: This register is only accessible via I/O space;
1023 * HPT374 BIOS only saves it for the function 0, so we have to
1024 * always read it from there -- no need to check the result of
1025 * pci_get_slot() for the function 0 as the whole device has
1026 * been already "pinned" (via function 1) in init_setup_hpt374()
1028 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1029 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1031 unsigned long io_base = pci_resource_start(dev1, 4);
1033 temp = inl(io_base + 0x90);
1036 temp = inl(io_base + 0x90);
1039 * In case the signature check fails, we'll have to
1040 * resort to reading the f_CNT register itself in hopes
1041 * that nobody has touched the DPLL yet...
1043 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1046 printk(KERN_WARNING "%s %s: no clock data saved by "
1047 "BIOS\n", name, pci_name(dev));
1049 /* Calculate the average value of f_CNT. */
1050 for (temp = i = 0; i < 128; i++) {
1051 pci_read_config_word(dev, 0x78, &f_cnt);
1052 temp += f_cnt & 0x1ff;
1057 f_cnt = temp & 0x1ff;
1059 dpll_clk = info->dpll_clk;
1060 pci_clk = (f_cnt * dpll_clk) / 192;
1062 /* Clamp PCI clock to bands. */
1065 else if(pci_clk < 45)
1067 else if(pci_clk < 55)
1072 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1073 "assuming %d MHz PCI\n", name, pci_name(dev),
1074 dpll_clk, f_cnt, pci_clk);
1078 pci_read_config_dword(dev, 0x40, &itr1);
1080 /* Detect PCI clock by looking at cmd_high_time. */
1081 switch((itr1 >> 8) & 0x07) {
1095 /* Let's assume we'll use PCI clock for the ATA clock... */
1098 clock = ATA_CLOCK_25MHZ;
1102 clock = ATA_CLOCK_33MHZ;
1105 clock = ATA_CLOCK_40MHZ;
1108 clock = ATA_CLOCK_50MHZ;
1111 clock = ATA_CLOCK_66MHZ;
1116 * Only try the DPLL if we don't have a table for the PCI clock that
1117 * we are running at for HPT370/A, always use it for anything newer...
1119 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1120 * We also don't like using the DPLL because this causes glitches
1121 * on PRST-/SRST- when the state engine gets reset...
1123 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1124 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1128 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1129 * supported/enabled, use 50 MHz DPLL clock otherwise...
1131 if (info->udma_mask == ATA_UDMA6) {
1133 clock = ATA_CLOCK_66MHZ;
1134 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1136 clock = ATA_CLOCK_50MHZ;
1139 if (info->timings->clock_table[clock] == NULL) {
1140 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1141 name, pci_name(dev));
1145 /* Select the DPLL clock. */
1146 pci_write_config_byte(dev, 0x5b, 0x21);
1149 * Adjust the DPLL based upon PCI clock, enable it,
1150 * and wait for stabilization...
1152 f_low = (pci_clk * 48) / dpll_clk;
1154 for (adjust = 0; adjust < 8; adjust++) {
1155 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1159 * See if it'll settle at a fractionally different clock
1162 f_low -= adjust >> 1;
1164 f_low += adjust >> 1;
1167 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1168 name, pci_name(dev));
1172 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1173 name, pci_name(dev), dpll_clk);
1175 /* Mark the fact that we're not using the DPLL. */
1178 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1179 name, pci_name(dev), pci_clk);
1182 /* Store the clock frequencies. */
1183 info->dpll_clk = dpll_clk;
1184 info->pci_clk = pci_clk;
1185 info->clock = clock;
1187 if (chip_type >= HPT370) {
1191 * Reset the state engines.
1192 * NOTE: Avoid accidentally enabling the disabled channels.
1194 pci_read_config_byte (dev, 0x50, &mcr1);
1195 pci_read_config_byte (dev, 0x54, &mcr4);
1196 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1197 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1202 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1203 * the MISC. register to stretch the UltraDMA Tss timing.
1204 * NOTE: This register is only writeable via I/O space.
1206 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1207 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1209 hpt3xx_disable_fast_irq(dev, 0x50);
1210 hpt3xx_disable_fast_irq(dev, 0x54);
1215 static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1217 struct pci_dev *dev = to_pci_dev(hwif->dev);
1218 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1219 u8 chip_type = info->chip_type;
1220 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1223 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1224 * address lines to access an external EEPROM. To read valid
1225 * cable detect state the pins must be enabled as inputs.
1227 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1229 * HPT374 PCI function 1
1230 * - set bit 15 of reg 0x52 to enable TCBLID as input
1231 * - set bit 15 of reg 0x56 to enable FCBLID as input
1233 u8 mcr_addr = hwif->select_data + 2;
1236 pci_read_config_word(dev, mcr_addr, &mcr);
1237 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1238 /* now read cable id register */
1239 pci_read_config_byte(dev, 0x5a, &scr1);
1240 pci_write_config_word(dev, mcr_addr, mcr);
1241 } else if (chip_type >= HPT370) {
1243 * HPT370/372 and 374 pcifn 0
1244 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1248 pci_read_config_byte(dev, 0x5b, &scr2);
1249 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1250 /* now read cable id register */
1251 pci_read_config_byte(dev, 0x5a, &scr1);
1252 pci_write_config_byte(dev, 0x5b, scr2);
1254 pci_read_config_byte(dev, 0x5a, &scr1);
1256 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1259 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1261 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1262 u8 chip_type = info->chip_type;
1264 /* Cache the channel's MISC. control registers' offset */
1265 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1268 * HPT3xxN chips have some complications:
1270 * - on 33 MHz PCI we must clock switch
1271 * - on 66 MHz PCI we must NOT use the PCI clock
1273 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1275 * Clock is shared between the channels,
1276 * so we'll have to serialize them... :-(
1278 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
1279 hwif->rw_disk = &hpt3xxn_rw_disk;
1283 static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1284 const struct ide_port_info *d)
1286 struct pci_dev *dev = to_pci_dev(hwif->dev);
1287 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1288 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1293 hwif->dma_base = base;
1295 if (ide_pci_check_simplex(hwif, d) < 0)
1298 if (ide_pci_set_master(dev, d->name) < 0)
1301 dma_old = inb(base + 2);
1303 local_irq_save(flags);
1306 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1307 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1309 if (masterdma & 0x30) dma_new |= 0x20;
1310 if ( slavedma & 0x30) dma_new |= 0x40;
1311 if (dma_new != dma_old)
1312 outb(dma_new, base + 2);
1314 local_irq_restore(flags);
1316 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1317 hwif->name, base, base + 7);
1319 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1321 if (ide_allocate_dma_engine(hwif))
1327 static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1329 if (dev2->irq != dev->irq) {
1330 /* FIXME: we need a core pci_set_interrupt() */
1331 dev2->irq = dev->irq;
1332 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1333 "fixed\n", pci_name(dev2));
1337 static void __devinit hpt371_init(struct pci_dev *dev)
1342 * HPT371 chips physically have only one channel, the secondary one,
1343 * but the primary channel registers do exist! Go figure...
1344 * So, we manually disable the non-existing channel here
1345 * (if the BIOS hasn't done this already).
1347 pci_read_config_byte(dev, 0x50, &mcr1);
1349 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1352 static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1354 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1357 * Now we'll have to force both channels enabled if
1358 * at least one of them has been enabled by BIOS...
1360 pci_read_config_byte(dev, 0x50, &mcr1);
1362 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1364 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1365 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1367 if (pin1 != pin2 && dev->irq == dev2->irq) {
1368 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1369 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1376 #define IDE_HFLAGS_HPT3XX \
1377 (IDE_HFLAG_NO_ATAPI_DMA | \
1378 IDE_HFLAG_OFF_BOARD)
1380 static const struct ide_port_ops hpt3xx_port_ops = {
1381 .set_pio_mode = hpt3xx_set_pio_mode,
1382 .set_dma_mode = hpt3xx_set_mode,
1383 .maskproc = hpt3xx_maskproc,
1384 .mdma_filter = hpt3xx_mdma_filter,
1385 .udma_filter = hpt3xx_udma_filter,
1386 .cable_detect = hpt3xx_cable_detect,
1389 static const struct ide_dma_ops hpt37x_dma_ops = {
1390 .dma_host_set = ide_dma_host_set,
1391 .dma_setup = ide_dma_setup,
1392 .dma_start = ide_dma_start,
1393 .dma_end = hpt374_dma_end,
1394 .dma_test_irq = hpt374_dma_test_irq,
1395 .dma_lost_irq = ide_dma_lost_irq,
1396 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1397 .dma_sff_read_status = ide_dma_sff_read_status,
1400 static const struct ide_dma_ops hpt370_dma_ops = {
1401 .dma_host_set = ide_dma_host_set,
1402 .dma_setup = ide_dma_setup,
1403 .dma_start = hpt370_dma_start,
1404 .dma_end = hpt370_dma_end,
1405 .dma_test_irq = ide_dma_test_irq,
1406 .dma_lost_irq = ide_dma_lost_irq,
1407 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1408 .dma_clear = hpt370_irq_timeout,
1409 .dma_sff_read_status = ide_dma_sff_read_status,
1412 static const struct ide_dma_ops hpt36x_dma_ops = {
1413 .dma_host_set = ide_dma_host_set,
1414 .dma_setup = ide_dma_setup,
1415 .dma_start = ide_dma_start,
1416 .dma_end = ide_dma_end,
1417 .dma_test_irq = ide_dma_test_irq,
1418 .dma_lost_irq = hpt366_dma_lost_irq,
1419 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1420 .dma_sff_read_status = ide_dma_sff_read_status,
1423 static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1426 .init_chipset = init_chipset_hpt366,
1427 .init_hwif = init_hwif_hpt366,
1428 .init_dma = init_dma_hpt366,
1430 * HPT36x chips have one channel per function and have
1431 * both channel enable bits located differently and visible
1432 * to both functions -- really stupid design decision... :-(
1433 * Bit 4 is for the primary channel, bit 5 for the secondary.
1435 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1436 .port_ops = &hpt3xx_port_ops,
1437 .dma_ops = &hpt36x_dma_ops,
1438 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1439 .pio_mask = ATA_PIO4,
1440 .mwdma_mask = ATA_MWDMA2,
1444 .init_chipset = init_chipset_hpt366,
1445 .init_hwif = init_hwif_hpt366,
1446 .init_dma = init_dma_hpt366,
1447 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1448 .port_ops = &hpt3xx_port_ops,
1449 .dma_ops = &hpt37x_dma_ops,
1450 .host_flags = IDE_HFLAGS_HPT3XX,
1451 .pio_mask = ATA_PIO4,
1452 .mwdma_mask = ATA_MWDMA2,
1457 * hpt366_init_one - called when an HPT366 is found
1458 * @dev: the hpt366 device
1459 * @id: the matching pci id
1461 * Called when the PCI registration layer (or the IDE initialization)
1462 * finds a device matching our IDE device tables.
1464 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1466 const struct hpt_info *info = NULL;
1467 struct hpt_info *dyn_info;
1468 struct pci_dev *dev2 = NULL;
1469 struct ide_port_info d;
1470 u8 idx = id->driver_data;
1471 u8 rev = dev->revision;
1474 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1482 switch (min_t(u8, rev, 6)) {
1483 case 3: info = &hpt370; break;
1484 case 4: info = &hpt370a; break;
1485 case 5: info = &hpt372; break;
1486 case 6: info = &hpt372n; break;
1492 info = (rev > 1) ? &hpt372n : &hpt372a;
1495 info = (rev > 1) ? &hpt302n : &hpt302;
1499 info = (rev > 1) ? &hpt371n : &hpt371;
1509 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1511 d = hpt366_chipsets[min_t(u8, idx, 1)];
1513 d.udma_mask = info->udma_mask;
1515 /* fixup ->dma_ops for HPT370/HPT370A */
1516 if (info == &hpt370 || info == &hpt370a)
1517 d.dma_ops = &hpt370_dma_ops;
1519 if (info == &hpt36x || info == &hpt374)
1520 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1522 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1523 if (dyn_info == NULL) {
1524 printk(KERN_ERR "%s %s: out of memory!\n",
1525 d.name, pci_name(dev));
1531 * Copy everything from a static "template" structure
1532 * to just allocated per-chip hpt_info structure.
1534 memcpy(dyn_info, info, sizeof(*dyn_info));
1537 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1539 if (info == &hpt374)
1540 hpt374_init(dev, dev2);
1542 if (hpt36x_init(dev, dev2))
1543 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1546 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1554 ret = ide_pci_init_one(dev, &d, dyn_info);
1561 static void __devexit hpt366_remove(struct pci_dev *dev)
1563 struct ide_host *host = pci_get_drvdata(dev);
1564 struct ide_info *info = host->host_priv;
1565 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1567 ide_pci_remove(dev);
1572 static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
1573 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1574 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1575 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1576 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1577 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1578 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1581 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1583 static struct pci_driver hpt366_pci_driver = {
1584 .name = "HPT366_IDE",
1585 .id_table = hpt366_pci_tbl,
1586 .probe = hpt366_init_one,
1587 .remove = __devexit_p(hpt366_remove),
1588 .suspend = ide_pci_suspend,
1589 .resume = ide_pci_resume,
1592 static int __init hpt366_ide_init(void)
1594 return ide_pci_register_driver(&hpt366_pci_driver);
1597 static void __exit hpt366_ide_exit(void)
1599 pci_unregister_driver(&hpt366_pci_driver);
1602 module_init(hpt366_ide_init);
1603 module_exit(hpt366_ide_exit);
1605 MODULE_AUTHOR("Andre Hedrick");
1606 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1607 MODULE_LICENSE("GPL");