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   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37 #include <linux/scatterlist.h>
  38
  39 #include <asm/mach-au1x00/au1xxx.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1xxx_ide.h>
  42
  43 #define DRV_NAME        "au1200-ide"
  44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  45
  46 /* enable the burstmode in the dbdma */
  47 #define IDE_AU1XXX_BURSTMODE    1
  48
  49 static _auide_hwif auide_hwif;
  50
  51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  52
  53 void auide_insw(unsigned long port, void *addr, u32 count)
  54 {
  55         _auide_hwif *ahwif = &auide_hwif;
  56         chan_tab_t *ctp;
  57         au1x_ddma_desc_t *dp;
  58
  59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  60                            DDMA_FLAGS_NOIE)) {
  61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  62                 return;
  63         }
  64         ctp = *((chan_tab_t **)ahwif->rx_chan);
  65         dp = ctp->cur_ptr;
  66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  67                 ;
  68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  69 }
  70
  71 void auide_outsw(unsigned long port, void *addr, u32 count)
  72 {
  73         _auide_hwif *ahwif = &auide_hwif;
  74         chan_tab_t *ctp;
  75         au1x_ddma_desc_t *dp;
  76
  77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  78                              count << 1, DDMA_FLAGS_NOIE)) {
  79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  80                 return;
  81         }
  82         ctp = *((chan_tab_t **)ahwif->tx_chan);
  83         dp = ctp->cur_ptr;
  84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  85                 ;
  86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  87 }
  88
  89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
  90                               void *buf, unsigned int len)
  91 {
  92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  93 }
  94
  95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
  96                                void *buf, unsigned int len)
  97 {
  98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  99 }
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212 static int auide_build_dmatable(ide_drive_t *drive)
 213 {
 214         ide_hwif_t *hwif = drive->hwif;
 215         struct request *rq = hwif->rq;
 216         _auide_hwif *ahwif = &auide_hwif;
 217         struct scatterlist *sg;
 218         int i = hwif->sg_nents, iswrite, count = 0;
 219
 220         iswrite = (rq_data_dir(rq) == WRITE);
 221         /* Save for interrupt context */
 222         ahwif->drive = drive;
 223
 224         /* fill the descriptors */
 225         sg = hwif->sg_table;
 226         while (i && sg_dma_len(sg)) {
 227                 u32 cur_addr;
 228                 u32 cur_len;
 229
 230                 cur_addr = sg_dma_address(sg);
 231                 cur_len = sg_dma_len(sg);
 232
 233                 while (cur_len) {
 234                         u32 flags = DDMA_FLAGS_NOIE;
 235                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 236
 237                         if (++count >= PRD_ENTRIES) {
 238                                 printk(KERN_WARNING "%s: DMA table too small\n",
 239                                        drive->name);
 240                                 goto use_pio_instead;
 241                         }
 242
 243                         /* Lets enable intr for the last descriptor only */
 244                         if (1==i)
 245                                 flags = DDMA_FLAGS_IE;
 246                         else
 247                                 flags = DDMA_FLAGS_NOIE;
 248
 249                         if (iswrite) {
 250                                 if(!put_source_flags(ahwif->tx_chan,
 251                                                      (void*) sg_virt(sg),
 252                                                      tc, flags)) {
 253                                         printk(KERN_ERR "%s failed %d\n",
 254                                                __func__, __LINE__);
 255                                 }
 256                         } else
 257                         {
 258                                 if(!put_dest_flags(ahwif->rx_chan,
 259                                                    (void*) sg_virt(sg),
 260                                                    tc, flags)) {
 261                                         printk(KERN_ERR "%s failed %d\n",
 262                                                __func__, __LINE__);
 263                                 }
 264                         }
 265
 266                         cur_addr += tc;
 267                         cur_len -= tc;
 268                 }
 269                 sg = sg_next(sg);
 270                 i--;
 271         }
 272
 273         if (count)
 274                 return 1;
 275
 276  use_pio_instead:
 277         ide_destroy_dmatable(drive);
 278
 279         return 0; /* revert to PIO for this request */
 280 }
 281
 282 static int auide_dma_end(ide_drive_t *drive)
 283 {
 284         ide_destroy_dmatable(drive);
 285
 286         return 0;
 287 }
 288
 289 static void auide_dma_start(ide_drive_t *drive )
 290 {
 291 }
 292
 293
 294 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 295 {
 296         /* issue cmd to drive */
 297         ide_execute_command(drive, command, &ide_dma_intr,
 298                             (2*WAIT_CMD), NULL);
 299 }
 300
 301 static int auide_dma_setup(ide_drive_t *drive)
 302 {
 303         struct request *rq = drive->hwif->rq;
 304
 305         if (!auide_build_dmatable(drive)) {
 306                 ide_map_sg(drive, rq);
 307                 return 1;
 308         }
 309
 310         drive->waiting_for_dma = 1;
 311         return 0;
 312 }
 313
 314 static int auide_dma_test_irq(ide_drive_t *drive)
 315 {
 316         /* If dbdma didn't execute the STOP command yet, the
 317          * active bit is still set
 318          */
 319         drive->waiting_for_dma++;
 320         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 321                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 322                                      complete\n", drive->name);
 323                 return 1;
 324         }
 325         udelay(10);
 326         return 0;
 327 }
 328
 329 static void auide_dma_host_set(ide_drive_t *drive, int on)
 330 {
 331 }
 332
 333 static void auide_ddma_tx_callback(int irq, void *param)
 334 {
 335         _auide_hwif *ahwif = (_auide_hwif*)param;
 336         ahwif->drive->waiting_for_dma = 0;
 337 }
 338
 339 static void auide_ddma_rx_callback(int irq, void *param)
 340 {
 341         _auide_hwif *ahwif = (_auide_hwif*)param;
 342         ahwif->drive->waiting_for_dma = 0;
 343 }
 344
 345 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 346
 347 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 348 {
 349         dev->dev_id          = dev_id;
 350         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
 351         dev->dev_intlevel    = 0;
 352         dev->dev_intpolarity = 0;
 353         dev->dev_tsize       = tsize;
 354         dev->dev_devwidth    = devwidth;
 355         dev->dev_flags       = flags;
 356 }
 357
 358 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 359 static const struct ide_dma_ops au1xxx_dma_ops = {
 360         .dma_host_set           = auide_dma_host_set,
 361         .dma_setup              = auide_dma_setup,
 362         .dma_exec_cmd           = auide_dma_exec_cmd,
 363         .dma_start              = auide_dma_start,
 364         .dma_end                = auide_dma_end,
 365         .dma_test_irq           = auide_dma_test_irq,
 366         .dma_lost_irq           = ide_dma_lost_irq,
 367         .dma_timeout            = ide_dma_timeout,
 368 };
 369
 370 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 371 {
 372         _auide_hwif *auide = &auide_hwif;
 373         dbdev_tab_t source_dev_tab, target_dev_tab;
 374         u32 dev_id, tsize, devwidth, flags;
 375
 376         dev_id   = IDE_DDMA_REQ;
 377
 378         tsize    =  8; /*  1 */
 379         devwidth = 32; /* 16 */
 380
 381 #ifdef IDE_AU1XXX_BURSTMODE
 382         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 383 #else
 384         flags = DEV_FLAGS_SYNC;
 385 #endif
 386
 387         /* setup dev_tab for tx channel */
 388         auide_init_dbdma_dev( &source_dev_tab,
 389                               dev_id,
 390                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 391         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 392
 393         auide_init_dbdma_dev( &source_dev_tab,
 394                               dev_id,
 395                               tsize, devwidth, DEV_FLAGS_IN | flags);
 396         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 397
 398         /* We also need to add a target device for the DMA */
 399         auide_init_dbdma_dev( &target_dev_tab,
 400                               (u32)DSCR_CMD0_ALWAYS,
 401                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 402         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 403
 404         /* Get a channel for TX */
 405         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 406                                                  auide->tx_dev_id,
 407                                                  auide_ddma_tx_callback,
 408                                                  (void*)auide);
 409
 410         /* Get a channel for RX */
 411         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 412                                                  auide->target_dev_id,
 413                                                  auide_ddma_rx_callback,
 414                                                  (void*)auide);
 415
 416         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 417                                                              NUM_DESCRIPTORS);
 418         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 419                                                              NUM_DESCRIPTORS);
 420
 421         /* FIXME: check return value */
 422         (void)ide_allocate_dma_engine(hwif);
 423
 424         au1xxx_dbdma_start( auide->tx_chan );
 425         au1xxx_dbdma_start( auide->rx_chan );
 426
 427         return 0;
 428 }
 429 #else
 430 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 431 {
 432         _auide_hwif *auide = &auide_hwif;
 433         dbdev_tab_t source_dev_tab;
 434         int flags;
 435
 436 #ifdef IDE_AU1XXX_BURSTMODE
 437         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 438 #else
 439         flags = DEV_FLAGS_SYNC;
 440 #endif
 441
 442         /* setup dev_tab for tx channel */
 443         auide_init_dbdma_dev( &source_dev_tab,
 444                               (u32)DSCR_CMD0_ALWAYS,
 445                               8, 32, DEV_FLAGS_OUT | flags);
 446         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 447
 448         auide_init_dbdma_dev( &source_dev_tab,
 449                               (u32)DSCR_CMD0_ALWAYS,
 450                               8, 32, DEV_FLAGS_IN | flags);
 451         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 452
 453         /* Get a channel for TX */
 454         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 455                                                  auide->tx_dev_id,
 456                                                  NULL,
 457                                                  (void*)auide);
 458
 459         /* Get a channel for RX */
 460         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 461                                                  DSCR_CMD0_ALWAYS,
 462                                                  NULL,
 463                                                  (void*)auide);
 464
 465         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 466                                                              NUM_DESCRIPTORS);
 467         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 468                                                              NUM_DESCRIPTORS);
 469
 470         au1xxx_dbdma_start( auide->tx_chan );
 471         au1xxx_dbdma_start( auide->rx_chan );
 472
 473         return 0;
 474 }
 475 #endif
 476
 477 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 478 {
 479         int i;
 480         unsigned long *ata_regs = hw->io_ports_array;
 481
 482         /* FIXME? */
 483         for (i = 0; i < 8; i++)
 484                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
 485
 486         /* set the Alternative Status register */
 487         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
 488 }
 489
 490 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 491 static const struct ide_tp_ops au1xxx_tp_ops = {
 492         .exec_command           = ide_exec_command,
 493         .read_status            = ide_read_status,
 494         .read_altstatus         = ide_read_altstatus,
 495
 496         .set_irq                = ide_set_irq,
 497
 498         .tf_load                = ide_tf_load,
 499         .tf_read                = ide_tf_read,
 500
 501         .input_data             = au1xxx_input_data,
 502         .output_data            = au1xxx_output_data,
 503 };
 504 #endif
 505
 506 static const struct ide_port_ops au1xxx_port_ops = {
 507         .set_pio_mode           = au1xxx_set_pio_mode,
 508         .set_dma_mode           = auide_set_dma_mode,
 509 };
 510
 511 static const struct ide_port_info au1xxx_port_info = {
 512         .init_dma               = auide_ddma_init,
 513 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 514         .tp_ops                 = &au1xxx_tp_ops,
 515 #endif
 516         .port_ops               = &au1xxx_port_ops,
 517 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 518         .dma_ops                = &au1xxx_dma_ops,
 519 #endif
 520         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 521                                   IDE_HFLAG_NO_IO_32BIT |
 522                                   IDE_HFLAG_UNMASK_IRQS,
 523         .pio_mask               = ATA_PIO4,
 524 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 525         .mwdma_mask             = ATA_MWDMA2,
 526 #endif
 527 };
 528
 529 static int au_ide_probe(struct platform_device *dev)
 530 {
 531         _auide_hwif *ahwif = &auide_hwif;
 532         struct resource *res;
 533         struct ide_host *host;
 534         int ret = 0;
 535         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 536
 537 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 538         char *mode = "MWDMA2";
 539 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 540         char *mode = "PIO+DDMA(offload)";
 541 #endif
 542
 543         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 544         ahwif->irq = platform_get_irq(dev, 0);
 545
 546         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 547
 548         if (res == NULL) {
 549                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
 550                 ret = -ENODEV;
 551                 goto out;
 552         }
 553         if (ahwif->irq < 0) {
 554                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
 555                 ret = -ENODEV;
 556                 goto out;
 557         }
 558
 559         if (!request_mem_region(res->start, res->end - res->start + 1,
 560                                 dev->name)) {
 561                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 562                 ret =  -EBUSY;
 563                 goto out;
 564         }
 565
 566         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
 567         if (ahwif->regbase == 0) {
 568                 ret = -ENOMEM;
 569                 goto out;
 570         }
 571
 572         memset(&hw, 0, sizeof(hw));
 573         auide_setup_ports(&hw, ahwif);
 574         hw.irq = ahwif->irq;
 575         hw.dev = &dev->dev;
 576         hw.chipset = ide_au1xxx;
 577
 578         ret = ide_host_add(&au1xxx_port_info, hws, &host);
 579         if (ret)
 580                 goto out;
 581
 582         auide_hwif.hwif = host->ports[0];
 583
 584         platform_set_drvdata(dev, host);
 585
 586         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 587
 588  out:
 589         return ret;
 590 }
 591
 592 static int au_ide_remove(struct platform_device *dev)
 593 {
 594         struct resource *res;
 595         struct ide_host *host = platform_get_drvdata(dev);
 596         _auide_hwif *ahwif = &auide_hwif;
 597
 598         ide_host_remove(host);
 599
 600         iounmap((void *)ahwif->regbase);
 601
 602         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 603         release_mem_region(res->start, res->end - res->start + 1);
 604
 605         return 0;
 606 }
 607
 608 static struct platform_driver au1200_ide_driver = {
 609         .driver = {
 610                 .name           = "au1200-ide",
 611                 .owner          = THIS_MODULE,
 612         },
 613         .probe          = au_ide_probe,
 614         .remove         = au_ide_remove,
 615 };
 616
 617 static int __init au_ide_init(void)
 618 {
 619         return platform_driver_register(&au1200_ide_driver);
 620 }
 621
 622 static void __exit au_ide_exit(void)
 623 {
 624         platform_driver_unregister(&au1200_ide_driver);
 625 }
 626
 627 MODULE_LICENSE("GPL");
 628 MODULE_DESCRIPTION("AU1200 IDE driver");
 629
 630 module_init(au_ide_init);
 631 module_exit(au_ide_exit);