ide: remove ->ide_dma_check (take 2)
[safe/jmp/linux-2.6] / drivers / ide / arm / icside.c
1 /*
2  * linux/drivers/ide/arm/icside.c
3  *
4  * Copyright (c) 1996-2004 Russell King.
5  *
6  * Please note that this platform does not support 32-bit IDE IO.
7  */
8
9 #include <linux/string.h>
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/slab.h>
13 #include <linux/blkdev.h>
14 #include <linux/errno.h>
15 #include <linux/hdreg.h>
16 #include <linux/ide.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/scatterlist.h>
21 #include <linux/io.h>
22
23 #include <asm/dma.h>
24 #include <asm/ecard.h>
25
26 #define ICS_IDENT_OFFSET                0x2280
27
28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING        6
33
34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING        6
43
44 struct cardinfo {
45         unsigned int dataoffset;
46         unsigned int ctrloffset;
47         unsigned int stepping;
48 };
49
50 static struct cardinfo icside_cardinfo_v5 = {
51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
54 };
55
56 static struct cardinfo icside_cardinfo_v6_1 = {
57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
60 };
61
62 static struct cardinfo icside_cardinfo_v6_2 = {
63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
66 };
67
68 struct icside_state {
69         unsigned int channel;
70         unsigned int enabled;
71         void __iomem *irq_port;
72         void __iomem *ioc_base;
73         unsigned int type;
74         /* parent device... until the IDE core gets one of its own */
75         struct device *dev;
76         ide_hwif_t *hwif[2];
77 };
78
79 #define ICS_TYPE_A3IN   0
80 #define ICS_TYPE_A3USER 1
81 #define ICS_TYPE_V6     3
82 #define ICS_TYPE_V5     15
83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
84
85 /* ---------------- Version 5 PCB Support Functions --------------------- */
86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
87  * Purpose  : enable interrupts from card
88  */
89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
90 {
91         struct icside_state *state = ec->irq_data;
92
93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
94 }
95
96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
97  * Purpose  : disable interrupts from card
98  */
99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
100 {
101         struct icside_state *state = ec->irq_data;
102
103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
104 }
105
106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
107         .irqenable      = icside_irqenable_arcin_v5,
108         .irqdisable     = icside_irqdisable_arcin_v5,
109 };
110
111
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114  * Purpose  : enable interrupts from card
115  */
116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
117 {
118         struct icside_state *state = ec->irq_data;
119         void __iomem *base = state->irq_port;
120
121         state->enabled = 1;
122
123         switch (state->channel) {
124         case 0:
125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
127                 break;
128         case 1:
129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
131                 break;
132         }
133 }
134
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136  * Purpose  : disable interrupts from card
137  */
138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
139 {
140         struct icside_state *state = ec->irq_data;
141
142         state->enabled = 0;
143
144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
146 }
147
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149  * Purpose  : detect an active interrupt from card
150  */
151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
152 {
153         struct icside_state *state = ec->irq_data;
154
155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
157 }
158
159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
160         .irqenable      = icside_irqenable_arcin_v6,
161         .irqdisable     = icside_irqdisable_arcin_v6,
162         .irqpending     = icside_irqpending_arcin_v6,
163 };
164
165 /*
166  * Handle routing of interrupts.  This is called before
167  * we write the command to the drive.
168  */
169 static void icside_maskproc(ide_drive_t *drive, int mask)
170 {
171         ide_hwif_t *hwif = HWIF(drive);
172         struct icside_state *state = hwif->hwif_data;
173         unsigned long flags;
174
175         local_irq_save(flags);
176
177         state->channel = hwif->channel;
178
179         if (state->enabled && !mask) {
180                 switch (hwif->channel) {
181                 case 0:
182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
184                         break;
185                 case 1:
186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
188                         break;
189                 }
190         } else {
191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
193         }
194
195         local_irq_restore(flags);
196 }
197
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
199 /*
200  * SG-DMA support.
201  *
202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
203  * There is only one DMA controller per card, which means that only
204  * one drive can be accessed at one time.  NOTE! We do not enforce that
205  * here, but we rely on the main IDE driver spotting that both
206  * interfaces use the same IRQ, which should guarantee this.
207  */
208
209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
210 {
211         ide_hwif_t *hwif = drive->hwif;
212         struct icside_state *state = hwif->hwif_data;
213         struct scatterlist *sg = hwif->sg_table;
214
215         ide_map_sg(drive, rq);
216
217         if (rq_data_dir(rq) == READ)
218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
219         else
220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
221
222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
223                                     hwif->sg_dma_direction);
224 }
225
226 /*
227  * Configure the IOMD to give the appropriate timings for the transfer
228  * mode being requested.  We take the advice of the ATA standards, and
229  * calculate the cycle time based on the transfer mode, and the EIDE
230  * MW DMA specs that the drive provides in the IDENTIFY command.
231  *
232  * We have the following IOMD DMA modes to choose from:
233  *
234  *      Type    Active          Recovery        Cycle
235  *      A       250 (250)       312 (550)       562 (800)
236  *      B       187             250             437
237  *      C       125 (125)       125 (375)       250 (500)
238  *      D       62              125             187
239  *
240  * (figures in brackets are actual measured timings)
241  *
242  * However, we also need to take care of the read/write active and
243  * recovery timings:
244  *
245  *                      Read    Write
246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
247  *      MW0     215     50      215     480     A
248  *      MW1     80      50      50      150     C
249  *      MW2     70      25      25      120     C
250  */
251 static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
252 {
253         int cycle_time, use_dma_info = 0;
254
255         switch (xfer_mode) {
256         case XFER_MW_DMA_2:
257                 cycle_time = 250;
258                 use_dma_info = 1;
259                 break;
260
261         case XFER_MW_DMA_1:
262                 cycle_time = 250;
263                 use_dma_info = 1;
264                 break;
265
266         case XFER_MW_DMA_0:
267                 cycle_time = 480;
268                 break;
269
270         case XFER_SW_DMA_2:
271         case XFER_SW_DMA_1:
272         case XFER_SW_DMA_0:
273                 cycle_time = 480;
274                 break;
275         default:
276                 return;
277         }
278
279         /*
280          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
281          * take care to note the values in the ID...
282          */
283         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
284                 cycle_time = drive->id->eide_dma_time;
285
286         drive->drive_data = cycle_time;
287
288         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
289                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
290 }
291
292 static void icside_dma_host_off(ide_drive_t *drive)
293 {
294 }
295
296 static void icside_dma_off_quietly(ide_drive_t *drive)
297 {
298         drive->using_dma = 0;
299 }
300
301 static void icside_dma_host_on(ide_drive_t *drive)
302 {
303 }
304
305 static int icside_dma_on(ide_drive_t *drive)
306 {
307         drive->using_dma = 1;
308
309         return 0;
310 }
311
312 static int icside_dma_end(ide_drive_t *drive)
313 {
314         ide_hwif_t *hwif = HWIF(drive);
315         struct icside_state *state = hwif->hwif_data;
316
317         drive->waiting_for_dma = 0;
318
319         disable_dma(hwif->hw.dma);
320
321         /* Teardown mappings after DMA has completed. */
322         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
323                      hwif->sg_dma_direction);
324
325         return get_dma_residue(hwif->hw.dma) != 0;
326 }
327
328 static void icside_dma_start(ide_drive_t *drive)
329 {
330         ide_hwif_t *hwif = HWIF(drive);
331
332         /* We can not enable DMA on both channels simultaneously. */
333         BUG_ON(dma_channel_active(hwif->hw.dma));
334         enable_dma(hwif->hw.dma);
335 }
336
337 static int icside_dma_setup(ide_drive_t *drive)
338 {
339         ide_hwif_t *hwif = HWIF(drive);
340         struct request *rq = hwif->hwgroup->rq;
341         unsigned int dma_mode;
342
343         if (rq_data_dir(rq))
344                 dma_mode = DMA_MODE_WRITE;
345         else
346                 dma_mode = DMA_MODE_READ;
347
348         /*
349          * We can not enable DMA on both channels.
350          */
351         BUG_ON(dma_channel_active(hwif->hw.dma));
352
353         icside_build_sglist(drive, rq);
354
355         /*
356          * Ensure that we have the right interrupt routed.
357          */
358         icside_maskproc(drive, 0);
359
360         /*
361          * Route the DMA signals to the correct interface.
362          */
363         writeb(hwif->select_data, hwif->config_data);
364
365         /*
366          * Select the correct timing for this drive.
367          */
368         set_dma_speed(hwif->hw.dma, drive->drive_data);
369
370         /*
371          * Tell the DMA engine about the SG table and
372          * data direction.
373          */
374         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
375         set_dma_mode(hwif->hw.dma, dma_mode);
376
377         drive->waiting_for_dma = 1;
378
379         return 0;
380 }
381
382 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
383 {
384         /* issue cmd to drive */
385         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
386 }
387
388 static int icside_dma_test_irq(ide_drive_t *drive)
389 {
390         ide_hwif_t *hwif = HWIF(drive);
391         struct icside_state *state = hwif->hwif_data;
392
393         return readb(state->irq_port +
394                      (hwif->channel ?
395                         ICS_ARCIN_V6_INTRSTAT_2 :
396                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
397 }
398
399 static void icside_dma_timeout(ide_drive_t *drive)
400 {
401         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
402
403         if (icside_dma_test_irq(drive))
404                 return;
405
406         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
407
408         icside_dma_end(drive);
409 }
410
411 static void icside_dma_lost_irq(ide_drive_t *drive)
412 {
413         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
414 }
415
416 static void icside_dma_init(ide_hwif_t *hwif)
417 {
418         printk("    %s: SG-DMA", hwif->name);
419
420         hwif->atapi_dma         = 1;
421         hwif->mwdma_mask        = 7; /* MW0..2 */
422         hwif->swdma_mask        = 7; /* SW0..2 */
423
424         hwif->dmatable_cpu      = NULL;
425         hwif->dmatable_dma      = 0;
426         hwif->set_dma_mode      = icside_set_dma_mode;
427         hwif->autodma           = 1;
428
429         hwif->dma_host_off      = icside_dma_host_off;
430         hwif->dma_off_quietly   = icside_dma_off_quietly;
431         hwif->dma_host_on       = icside_dma_host_on;
432         hwif->ide_dma_on        = icside_dma_on;
433         hwif->dma_setup         = icside_dma_setup;
434         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
435         hwif->dma_start         = icside_dma_start;
436         hwif->ide_dma_end       = icside_dma_end;
437         hwif->ide_dma_test_irq  = icside_dma_test_irq;
438         hwif->dma_timeout       = icside_dma_timeout;
439         hwif->dma_lost_irq      = icside_dma_lost_irq;
440
441         hwif->drives[0].autodma = hwif->autodma;
442         hwif->drives[1].autodma = hwif->autodma;
443
444         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
445 }
446 #else
447 #define icside_dma_init(hwif)   (0)
448 #endif
449
450 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
451 {
452         ide_hwif_t *hwif;
453         int index;
454
455         for (index = 0; index < MAX_HWIFS; ++index) {
456                 hwif = &ide_hwifs[index];
457                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
458                         goto found;
459         }
460
461         for (index = 0; index < MAX_HWIFS; ++index) {
462                 hwif = &ide_hwifs[index];
463                 if (!hwif->io_ports[IDE_DATA_OFFSET])
464                         goto found;
465         }
466
467         hwif = NULL;
468 found:
469         return hwif;
470 }
471
472 static ide_hwif_t *
473 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
474 {
475         unsigned long port = (unsigned long)base + info->dataoffset;
476         ide_hwif_t *hwif;
477
478         hwif = icside_find_hwif(port);
479         if (hwif) {
480                 int i;
481
482                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
483
484                 /*
485                  * Ensure we're using MMIO
486                  */
487                 default_hwif_mmiops(hwif);
488                 hwif->mmio = 1;
489
490                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
491                         hwif->hw.io_ports[i] = port;
492                         hwif->io_ports[i] = port;
493                         port += 1 << info->stepping;
494                 }
495                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
496                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
497                 hwif->hw.irq  = ec->irq;
498                 hwif->irq     = ec->irq;
499                 hwif->noprobe = 0;
500                 hwif->chipset = ide_acorn;
501                 hwif->gendev.parent = &ec->dev;
502         }
503
504         return hwif;
505 }
506
507 static int __init
508 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
509 {
510         ide_hwif_t *hwif;
511         void __iomem *base;
512
513         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
514         if (!base)
515                 return -ENOMEM;
516
517         state->irq_port = base;
518
519         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
520         ec->irqmask  = 1;
521
522         ecard_setirq(ec, &icside_ops_arcin_v5, state);
523
524         /*
525          * Be on the safe side - disable interrupts
526          */
527         icside_irqdisable_arcin_v5(ec, 0);
528
529         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
530         if (!hwif)
531                 return -ENODEV;
532
533         state->hwif[0] = hwif;
534
535         probe_hwif_init(hwif);
536
537         ide_proc_register_port(hwif);
538
539         return 0;
540 }
541
542 static int __init
543 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
544 {
545         ide_hwif_t *hwif, *mate;
546         void __iomem *ioc_base, *easi_base;
547         unsigned int sel = 0;
548         int ret;
549
550         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
551         if (!ioc_base) {
552                 ret = -ENOMEM;
553                 goto out;
554         }
555
556         easi_base = ioc_base;
557
558         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
559                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
560                 if (!easi_base) {
561                         ret = -ENOMEM;
562                         goto out;
563                 }
564
565                 /*
566                  * Enable access to the EASI region.
567                  */
568                 sel = 1 << 5;
569         }
570
571         writeb(sel, ioc_base);
572
573         ecard_setirq(ec, &icside_ops_arcin_v6, state);
574
575         state->irq_port   = easi_base;
576         state->ioc_base   = ioc_base;
577
578         /*
579          * Be on the safe side - disable interrupts
580          */
581         icside_irqdisable_arcin_v6(ec, 0);
582
583         /*
584          * Find and register the interfaces.
585          */
586         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
587         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
588
589         if (!hwif || !mate) {
590                 ret = -ENODEV;
591                 goto out;
592         }
593
594         state->hwif[0]    = hwif;
595         state->hwif[1]    = mate;
596
597         hwif->maskproc    = icside_maskproc;
598         hwif->channel     = 0;
599         hwif->hwif_data   = state;
600         hwif->mate        = mate;
601         hwif->serialized  = 1;
602         hwif->config_data = (unsigned long)ioc_base;
603         hwif->select_data = sel;
604         hwif->hw.dma      = ec->dma;
605
606         mate->maskproc    = icside_maskproc;
607         mate->channel     = 1;
608         mate->hwif_data   = state;
609         mate->mate        = hwif;
610         mate->serialized  = 1;
611         mate->config_data = (unsigned long)ioc_base;
612         mate->select_data = sel | 1;
613         mate->hw.dma      = ec->dma;
614
615         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
616                 icside_dma_init(hwif);
617                 icside_dma_init(mate);
618         }
619
620         probe_hwif_init(hwif);
621         probe_hwif_init(mate);
622
623         ide_proc_register_port(hwif);
624         ide_proc_register_port(mate);
625
626         return 0;
627
628  out:
629         return ret;
630 }
631
632 static int __devinit
633 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
634 {
635         struct icside_state *state;
636         void __iomem *idmem;
637         int ret;
638
639         ret = ecard_request_resources(ec);
640         if (ret)
641                 goto out;
642
643         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
644         if (!state) {
645                 ret = -ENOMEM;
646                 goto release;
647         }
648
649         state->type     = ICS_TYPE_NOTYPE;
650         state->dev      = &ec->dev;
651
652         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
653         if (idmem) {
654                 unsigned int type;
655
656                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
657                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
658                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
659                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
660                 ecardm_iounmap(ec, idmem);
661
662                 state->type = type;
663         }
664
665         switch (state->type) {
666         case ICS_TYPE_A3IN:
667                 dev_warn(&ec->dev, "A3IN unsupported\n");
668                 ret = -ENODEV;
669                 break;
670
671         case ICS_TYPE_A3USER:
672                 dev_warn(&ec->dev, "A3USER unsupported\n");
673                 ret = -ENODEV;
674                 break;
675
676         case ICS_TYPE_V5:
677                 ret = icside_register_v5(state, ec);
678                 break;
679
680         case ICS_TYPE_V6:
681                 ret = icside_register_v6(state, ec);
682                 break;
683
684         default:
685                 dev_warn(&ec->dev, "unknown interface type\n");
686                 ret = -ENODEV;
687                 break;
688         }
689
690         if (ret == 0) {
691                 ecard_set_drvdata(ec, state);
692                 goto out;
693         }
694
695         kfree(state);
696  release:
697         ecard_release_resources(ec);
698  out:
699         return ret;
700 }
701
702 static void __devexit icside_remove(struct expansion_card *ec)
703 {
704         struct icside_state *state = ecard_get_drvdata(ec);
705
706         switch (state->type) {
707         case ICS_TYPE_V5:
708                 /* FIXME: tell IDE to stop using the interface */
709
710                 /* Disable interrupts */
711                 icside_irqdisable_arcin_v5(ec, 0);
712                 break;
713
714         case ICS_TYPE_V6:
715                 /* FIXME: tell IDE to stop using the interface */
716                 if (ec->dma != NO_DMA)
717                         free_dma(ec->dma);
718
719                 /* Disable interrupts */
720                 icside_irqdisable_arcin_v6(ec, 0);
721
722                 /* Reset the ROM pointer/EASI selection */
723                 writeb(0, state->ioc_base);
724                 break;
725         }
726
727         ecard_set_drvdata(ec, NULL);
728
729         kfree(state);
730         ecard_release_resources(ec);
731 }
732
733 static void icside_shutdown(struct expansion_card *ec)
734 {
735         struct icside_state *state = ecard_get_drvdata(ec);
736         unsigned long flags;
737
738         /*
739          * Disable interrupts from this card.  We need to do
740          * this before disabling EASI since we may be accessing
741          * this register via that region.
742          */
743         local_irq_save(flags);
744         ec->ops->irqdisable(ec, 0);
745         local_irq_restore(flags);
746
747         /*
748          * Reset the ROM pointer so that we can read the ROM
749          * after a soft reboot.  This also disables access to
750          * the IDE taskfile via the EASI region.
751          */
752         if (state->ioc_base)
753                 writeb(0, state->ioc_base);
754 }
755
756 static const struct ecard_id icside_ids[] = {
757         { MANU_ICS,  PROD_ICS_IDE  },
758         { MANU_ICS2, PROD_ICS2_IDE },
759         { 0xffff, 0xffff }
760 };
761
762 static struct ecard_driver icside_driver = {
763         .probe          = icside_probe,
764         .remove         = __devexit_p(icside_remove),
765         .shutdown       = icside_shutdown,
766         .id_table       = icside_ids,
767         .drv = {
768                 .name   = "icside",
769         },
770 };
771
772 static int __init icside_init(void)
773 {
774         return ecard_register_driver(&icside_driver);
775 }
776
777 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
778 MODULE_LICENSE("GPL");
779 MODULE_DESCRIPTION("ICS IDE driver");
780
781 module_init(icside_init);