4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <mach/hardware.h>
41 #include <mach/pxa-regs.h>
45 wait_queue_head_t wait;
50 unsigned int slave_addr;
52 struct i2c_adapter adap;
54 #ifdef CONFIG_I2C_PXA_SLAVE
55 struct i2c_slave_client *slave;
58 unsigned int irqlogidx;
62 void __iomem *reg_base;
63 unsigned int reg_shift;
69 unsigned int use_pio :1;
70 unsigned int fast_mode :1;
73 #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
74 #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
75 #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
76 #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
77 #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
80 * I2C Slave mode address
82 #define I2C_PXA_SLAVE_ADDR 0x1
91 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
94 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
96 printk("%s %08x: ", prefix, val);
98 const char *str = val & bits->mask ? bits->set : bits->unset;
105 static const struct bits isr_bits[] = {
106 PXA_BIT(ISR_RWM, "RX", "TX"),
107 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
108 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
109 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
110 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
111 PXA_BIT(ISR_ALD, "ALD", NULL),
112 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
113 PXA_BIT(ISR_IRF, "RxFull", NULL),
114 PXA_BIT(ISR_GCAD, "GenCall", NULL),
115 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
116 PXA_BIT(ISR_BED, "BusErr", NULL),
119 static void decode_ISR(unsigned int val)
121 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
125 static const struct bits icr_bits[] = {
126 PXA_BIT(ICR_START, "START", NULL),
127 PXA_BIT(ICR_STOP, "STOP", NULL),
128 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
129 PXA_BIT(ICR_TB, "TB", NULL),
130 PXA_BIT(ICR_MA, "MA", NULL),
131 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
132 PXA_BIT(ICR_IUE, "IUE", "iue"),
133 PXA_BIT(ICR_GCD, "GCD", NULL),
134 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
135 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
136 PXA_BIT(ICR_BEIE, "BEIE", NULL),
137 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
138 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
139 PXA_BIT(ICR_SADIE, "SADIE", NULL),
140 PXA_BIT(ICR_UR, "UR", "ur"),
143 #ifdef CONFIG_I2C_PXA_SLAVE
144 static void decode_ICR(unsigned int val)
146 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
151 static unsigned int i2c_debug = DEBUG;
153 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
155 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
156 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
159 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
163 #define show_state(i2c) do { } while (0)
164 #define decode_ISR(val) do { } while (0)
165 #define decode_ICR(val) do { } while (0)
168 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
170 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
171 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
173 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
176 printk("i2c: error: %s\n", why);
177 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
178 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
179 printk("i2c: ICR: %08x ISR: %08x\n"
180 "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
181 for (i = 0; i < i2c->irqlogidx; i++)
182 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
186 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
188 return !(readl(_ICR(i2c)) & ICR_SCLE);
191 static void i2c_pxa_abort(struct pxa_i2c *i2c)
195 if (i2c_pxa_is_slavemode(i2c)) {
196 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
200 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
201 unsigned long icr = readl(_ICR(i2c));
204 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
206 writel(icr, _ICR(i2c));
214 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
218 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
220 int timeout = DEF_TIMEOUT;
222 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
223 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
233 return timeout <= 0 ? I2C_RETRY : 0;
236 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
238 unsigned long timeout = jiffies + HZ*4;
240 while (time_before(jiffies, timeout)) {
242 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
243 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
245 if (readl(_ISR(i2c)) & ISR_SAD) {
247 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
251 /* wait for unit and bus being not busy, and we also do a
252 * quick check of the i2c lines themselves to ensure they've
255 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
257 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
265 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
270 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
273 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
275 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
276 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
277 if (!i2c_pxa_wait_master(i2c)) {
278 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
283 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
287 #ifdef CONFIG_I2C_PXA_SLAVE
288 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
290 unsigned long timeout = jiffies + HZ*1;
296 while (time_before(jiffies, timeout)) {
298 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
299 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
301 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
302 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
303 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
305 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
313 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
318 * clear the hold on the bus, and take of anything else
319 * that has been configured
321 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
326 udelay(100); /* simple delay */
328 /* we need to wait for the stop condition to end */
330 /* if we where in stop, then clear... */
331 if (readl(_ICR(i2c)) & ICR_STOP) {
333 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
336 if (!i2c_pxa_wait_slave(i2c)) {
337 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
343 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
344 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
347 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
348 decode_ICR(readl(_ICR(i2c)));
352 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
355 static void i2c_pxa_reset(struct pxa_i2c *i2c)
357 pr_debug("Resetting I2C Controller Unit\n");
359 /* abort any transfer currently under way */
362 /* reset according to 9.8 */
363 writel(ICR_UR, _ICR(i2c));
364 writel(I2C_ISR_INIT, _ISR(i2c));
365 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
367 writel(i2c->slave_addr, _ISAR(i2c));
369 /* set control register values */
370 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
372 #ifdef CONFIG_I2C_PXA_SLAVE
373 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
374 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
377 i2c_pxa_set_slave(i2c, 0);
380 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
385 #ifdef CONFIG_I2C_PXA_SLAVE
390 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
393 /* what should we do here? */
397 if (i2c->slave != NULL)
398 ret = i2c->slave->read(i2c->slave->data);
400 writel(ret, _IDBR(i2c));
401 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
405 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
407 unsigned int byte = readl(_IDBR(i2c));
409 if (i2c->slave != NULL)
410 i2c->slave->write(i2c->slave->data, byte);
412 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
415 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
420 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
421 (isr & ISR_RWM) ? 'r' : 't');
423 if (i2c->slave != NULL)
424 i2c->slave->event(i2c->slave->data,
425 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
428 * slave could interrupt in the middle of us generating a
429 * start condition... if this happens, we'd better back off
430 * and stop holding the poor thing up
432 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
433 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
438 if ((readl(_IBMR(i2c)) & 2) == 2)
444 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
449 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
452 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
455 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
457 if (i2c->slave != NULL)
458 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
461 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
464 * If we have a master-mode message waiting,
465 * kick it off now that the slave has completed.
468 i2c_pxa_master_complete(i2c, I2C_RETRY);
471 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
474 /* what should we do here? */
476 writel(0, _IDBR(i2c));
477 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
481 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
483 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
486 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
491 * slave could interrupt in the middle of us generating a
492 * start condition... if this happens, we'd better back off
493 * and stop holding the poor thing up
495 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
496 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
501 if ((readl(_IBMR(i2c)) & 2) == 2)
507 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
512 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
515 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
518 i2c_pxa_master_complete(i2c, I2C_RETRY);
523 * PXA I2C Master mode
526 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
528 unsigned int addr = (msg->addr & 0x7f) << 1;
530 if (msg->flags & I2C_M_RD)
536 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
541 * Step 1: target slave address into IDBR
543 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
546 * Step 2: initiate the write.
548 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
549 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
552 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
557 * Clear the STOP and ACK flags
559 icr = readl(_ICR(i2c));
560 icr &= ~(ICR_STOP | ICR_ACKNAK);
561 writel(icr, _ICR(i2c));
564 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
566 /* make timeout the same as for interrupt based functions */
567 long timeout = 2 * DEF_TIMEOUT;
570 * Wait for the bus to become free.
572 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
579 dev_err(&i2c->adap.dev,
580 "i2c_pxa: timeout waiting for bus free\n");
587 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
592 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
593 struct i2c_msg *msg, int num)
595 unsigned long timeout = 500000; /* 5 seconds */
598 ret = i2c_pxa_pio_set_master(i2c);
608 i2c_pxa_start_message(i2c);
610 while (timeout-- && i2c->msg_num > 0) {
611 i2c_pxa_handler(0, i2c);
615 i2c_pxa_stop_message(i2c);
618 * We place the return code in i2c->msg_idx.
624 i2c_pxa_scream_blue_murder(i2c, "timeout");
630 * We are protected by the adapter bus mutex.
632 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
638 * Wait for the bus to become free.
640 ret = i2c_pxa_wait_bus_not_busy(i2c);
642 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
649 ret = i2c_pxa_set_master(i2c);
651 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
655 spin_lock_irq(&i2c->lock);
663 i2c_pxa_start_message(i2c);
665 spin_unlock_irq(&i2c->lock);
668 * The rest of the processing occurs in the interrupt handler.
670 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
671 i2c_pxa_stop_message(i2c);
674 * We place the return code in i2c->msg_idx.
679 i2c_pxa_scream_blue_murder(i2c, "timeout");
685 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
686 struct i2c_msg msgs[], int num)
688 struct pxa_i2c *i2c = adap->algo_data;
691 /* If the I2C controller is disabled we need to reset it
692 (probably due to a suspend/resume destroying state). We do
693 this here as we can then avoid worrying about resuming the
694 controller before its users. */
695 if (!(readl(_ICR(i2c)) & ICR_IUE))
698 for (i = adap->retries; i >= 0; i--) {
699 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
700 if (ret != I2C_RETRY)
704 dev_dbg(&adap->dev, "Retrying transmission\n");
707 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
710 i2c_pxa_set_slave(i2c, ret);
715 * i2c_pxa_master_complete - complete the message and wake up.
717 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
729 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
731 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
735 * If ISR_ALD is set, we lost arbitration.
739 * Do we need to do anything here? The PXA docs
740 * are vague about what happens.
742 i2c_pxa_scream_blue_murder(i2c, "ALD set");
745 * We ignore this error. We seem to see spurious ALDs
746 * for seemingly no reason. If we handle them as I think
747 * they should, we end up causing an I2C error, which
748 * is painful for some systems.
757 * I2C bus error - either the device NAK'd us, or
758 * something more serious happened. If we were NAK'd
759 * on the initial address phase, we can retry.
761 if (isr & ISR_ACKNAK) {
762 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
767 i2c_pxa_master_complete(i2c, ret);
768 } else if (isr & ISR_RWM) {
770 * Read mode. We have just sent the address byte, and
771 * now we must initiate the transfer.
773 if (i2c->msg_ptr == i2c->msg->len - 1 &&
774 i2c->msg_idx == i2c->msg_num - 1)
775 icr |= ICR_STOP | ICR_ACKNAK;
777 icr |= ICR_ALDIE | ICR_TB;
778 } else if (i2c->msg_ptr < i2c->msg->len) {
780 * Write mode. Write the next data byte.
782 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
784 icr |= ICR_ALDIE | ICR_TB;
787 * If this is the last byte of the last message, send
790 if (i2c->msg_ptr == i2c->msg->len &&
791 i2c->msg_idx == i2c->msg_num - 1)
793 } else if (i2c->msg_idx < i2c->msg_num - 1) {
795 * Next segment of the message.
802 * If we aren't doing a repeated start and address,
803 * go back and try to send the next byte. Note that
804 * we do not support switching the R/W direction here.
806 if (i2c->msg->flags & I2C_M_NOSTART)
810 * Write the next address.
812 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
815 * And trigger a repeated start, and send the byte.
818 icr |= ICR_START | ICR_TB;
820 if (i2c->msg->len == 0) {
822 * Device probes have a message length of zero
823 * and need the bus to be reset before it can
828 i2c_pxa_master_complete(i2c, 0);
831 i2c->icrlog[i2c->irqlogidx-1] = icr;
833 writel(icr, _ICR(i2c));
837 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
839 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
844 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
846 if (i2c->msg_ptr < i2c->msg->len) {
848 * If this is the last byte of the last
849 * message, send a STOP.
851 if (i2c->msg_ptr == i2c->msg->len - 1)
852 icr |= ICR_STOP | ICR_ACKNAK;
854 icr |= ICR_ALDIE | ICR_TB;
856 i2c_pxa_master_complete(i2c, 0);
859 i2c->icrlog[i2c->irqlogidx-1] = icr;
861 writel(icr, _ICR(i2c));
864 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
866 struct pxa_i2c *i2c = dev_id;
867 u32 isr = readl(_ISR(i2c));
869 if (i2c_debug > 2 && 0) {
870 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
871 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
875 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
876 i2c->isrlog[i2c->irqlogidx++] = isr;
881 * Always clear all pending IRQs.
883 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
886 i2c_pxa_slave_start(i2c, isr);
888 i2c_pxa_slave_stop(i2c);
890 if (i2c_pxa_is_slavemode(i2c)) {
892 i2c_pxa_slave_txempty(i2c, isr);
894 i2c_pxa_slave_rxfull(i2c, isr);
895 } else if (i2c->msg) {
897 i2c_pxa_irq_txempty(i2c, isr);
899 i2c_pxa_irq_rxfull(i2c, isr);
901 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
908 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
910 struct pxa_i2c *i2c = adap->algo_data;
913 for (i = adap->retries; i >= 0; i--) {
914 ret = i2c_pxa_do_xfer(i2c, msgs, num);
915 if (ret != I2C_RETRY)
919 dev_dbg(&adap->dev, "Retrying transmission\n");
922 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
925 i2c_pxa_set_slave(i2c, ret);
929 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
931 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
934 static const struct i2c_algorithm i2c_pxa_algorithm = {
935 .master_xfer = i2c_pxa_xfer,
936 .functionality = i2c_pxa_functionality,
939 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
940 .master_xfer = i2c_pxa_pio_xfer,
941 .functionality = i2c_pxa_functionality,
944 #define res_len(r) ((r)->end - (r)->start + 1)
945 static int i2c_pxa_probe(struct platform_device *dev)
948 struct resource *res;
949 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
953 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
954 irq = platform_get_irq(dev, 0);
955 if (res == NULL || irq < 0)
958 if (!request_mem_region(res->start, res_len(res), res->name))
961 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
967 i2c->adap.owner = THIS_MODULE;
968 i2c->adap.retries = 5;
970 spin_lock_init(&i2c->lock);
971 init_waitqueue_head(&i2c->wait);
974 * If "dev->id" is negative we consider it as zero.
975 * The reason to do so is to avoid sysfs names that only make
976 * sense when there are multiple adapters.
978 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
979 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
982 i2c->clk = clk_get(&dev->dev, "I2CCLK");
983 if (IS_ERR(i2c->clk)) {
984 ret = PTR_ERR(i2c->clk);
988 i2c->reg_base = ioremap(res->start, res_len(res));
989 if (!i2c->reg_base) {
993 i2c->reg_shift = (cpu_is_pxa3xx() && (dev->id == 1)) ? 0 : 1;
995 i2c->iobase = res->start;
996 i2c->iosize = res_len(res);
1000 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1002 #ifdef CONFIG_I2C_PXA_SLAVE
1004 i2c->slave_addr = plat->slave_addr;
1005 i2c->slave = plat->slave;
1009 clk_enable(i2c->clk);
1012 i2c->adap.class = plat->class;
1013 i2c->use_pio = plat->use_pio;
1014 i2c->fast_mode = plat->fast_mode;
1018 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1020 i2c->adap.algo = &i2c_pxa_algorithm;
1021 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1022 i2c->adap.name, i2c);
1029 i2c->adap.algo_data = i2c;
1030 i2c->adap.dev.parent = &dev->dev;
1032 ret = i2c_add_numbered_adapter(&i2c->adap);
1034 printk(KERN_INFO "I2C: Failed to add bus\n");
1038 platform_set_drvdata(dev, i2c);
1040 #ifdef CONFIG_I2C_PXA_SLAVE
1041 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1042 i2c->adap.dev.bus_id, i2c->slave_addr);
1044 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1045 i2c->adap.dev.bus_id);
1053 clk_disable(i2c->clk);
1054 iounmap(i2c->reg_base);
1060 release_mem_region(res->start, res_len(res));
1064 static int __exit i2c_pxa_remove(struct platform_device *dev)
1066 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1068 platform_set_drvdata(dev, NULL);
1070 i2c_del_adapter(&i2c->adap);
1072 free_irq(i2c->irq, i2c);
1074 clk_disable(i2c->clk);
1077 iounmap(i2c->reg_base);
1078 release_mem_region(i2c->iobase, i2c->iosize);
1085 static int i2c_pxa_suspend_late(struct platform_device *dev, pm_message_t state)
1087 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1088 clk_disable(i2c->clk);
1092 static int i2c_pxa_resume_early(struct platform_device *dev)
1094 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1096 clk_enable(i2c->clk);
1102 #define i2c_pxa_suspend_late NULL
1103 #define i2c_pxa_resume_early NULL
1106 static struct platform_driver i2c_pxa_driver = {
1107 .probe = i2c_pxa_probe,
1108 .remove = __exit_p(i2c_pxa_remove),
1109 .suspend_late = i2c_pxa_suspend_late,
1110 .resume_early = i2c_pxa_resume_early,
1112 .name = "pxa2xx-i2c",
1113 .owner = THIS_MODULE,
1117 static int __init i2c_adap_pxa_init(void)
1119 return platform_driver_register(&i2c_pxa_driver);
1122 static void __exit i2c_adap_pxa_exit(void)
1124 platform_driver_unregister(&i2c_pxa_driver);
1127 MODULE_LICENSE("GPL");
1128 MODULE_ALIAS("platform:pxa2xx-i2c");
1130 subsys_initcall(i2c_adap_pxa_init);
1131 module_exit(i2c_adap_pxa_exit);