2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5 * Vitaly Wool <vwool@ru.mvista.com>
7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
26 #include <mach/hardware.h>
29 #include <asm/uaccess.h>
31 #define I2C_PNX_TIMEOUT 10 /* msec */
32 #define I2C_PNX_SPEED_KHZ 100
33 #define I2C_PNX_REGION_SIZE 0x100
34 #define PNX_DEFAULT_FREQ 13 /* MHz */
36 static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
39 (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
43 return (timeout <= 0);
46 static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
49 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
53 return (timeout <= 0);
56 static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap)
58 struct i2c_pnx_algo_data *data = adap->algo_data;
59 struct timer_list *timer = &data->mif.timer;
60 int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
65 del_timer_sync(timer);
67 dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n",
70 timer->expires = jiffies + expires;
71 timer->data = (unsigned long)adap;
77 * i2c_pnx_start - start a device
78 * @slave_addr: slave address
79 * @adap: pointer to adapter structure
81 * Generate a START signal in the desired mode.
83 static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap)
85 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
87 dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__,
88 slave_addr, alg_data->mif.mode);
90 /* Check for 7 bit slave addresses only */
91 if (slave_addr & ~0x7f) {
92 dev_err(&adap->dev, "%s: Invalid slave address %x. "
93 "Only 7-bit addresses are supported\n",
94 adap->name, slave_addr);
98 /* First, make sure bus is idle */
99 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
100 /* Somebody else is monopolizing the bus */
101 dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, "
102 "cntrl = %x, stat = %x\n",
103 adap->name, slave_addr,
104 ioread32(I2C_REG_CTL(alg_data)),
105 ioread32(I2C_REG_STS(alg_data)));
107 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
108 /* Sorry, we lost the bus */
109 dev_err(&adap->dev, "%s: Arbitration failure. "
110 "Slave addr = %02x\n", adap->name, slave_addr);
115 * OK, I2C is enabled and we have the bus.
116 * Clear the current TDI and AFI status flags.
118 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
119 I2C_REG_STS(alg_data));
121 dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__,
122 (slave_addr << 1) | start_bit | alg_data->mif.mode);
124 /* Write the slave address, START bit and R/W bit */
125 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
126 I2C_REG_TX(alg_data));
128 dev_dbg(&adap->dev, "%s(): exit\n", __func__);
134 * i2c_pnx_stop - stop a device
135 * @adap: pointer to I2C adapter structure
137 * Generate a STOP signal to terminate the master transaction.
139 static void i2c_pnx_stop(struct i2c_adapter *adap)
141 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
142 /* Only 1 msec max timeout due to interrupt context */
145 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
146 __func__, ioread32(I2C_REG_STS(alg_data)));
148 /* Write a STOP bit to TX FIFO */
149 iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
151 /* Wait until the STOP is seen. */
152 while (timeout > 0 &&
153 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
154 /* may be called from interrupt context */
159 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
160 __func__, ioread32(I2C_REG_STS(alg_data)));
164 * i2c_pnx_master_xmit - transmit data to slave
165 * @adap: pointer to I2C adapter structure
167 * Sends one byte of data to the slave
169 static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
171 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
174 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
175 __func__, ioread32(I2C_REG_STS(alg_data)));
177 if (alg_data->mif.len > 0) {
178 /* We still have something to talk about... */
179 val = *alg_data->mif.buf++;
181 if (alg_data->mif.len == 1) {
188 iowrite32(val, I2C_REG_TX(alg_data));
190 dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__,
191 val, alg_data->mif.len + 1);
193 if (alg_data->mif.len == 0) {
194 if (alg_data->last) {
195 /* Wait until the STOP is seen. */
196 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
197 dev_err(&adap->dev, "The bus is still "
198 "active after timeout\n");
200 /* Disable master interrupts */
201 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
202 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
203 I2C_REG_CTL(alg_data));
205 del_timer_sync(&alg_data->mif.timer);
207 dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n",
210 complete(&alg_data->mif.complete);
212 } else if (alg_data->mif.len == 0) {
213 /* zero-sized transfer */
216 /* Disable master interrupts. */
217 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
218 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
219 I2C_REG_CTL(alg_data));
222 del_timer_sync(&alg_data->mif.timer);
223 dev_dbg(&adap->dev, "%s(): Waking up xfer routine after "
224 "zero-xfer.\n", __func__);
226 complete(&alg_data->mif.complete);
229 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
230 __func__, ioread32(I2C_REG_STS(alg_data)));
236 * i2c_pnx_master_rcv - receive data from slave
237 * @adap: pointer to I2C adapter structure
239 * Reads one byte data from the slave
241 static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
243 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
244 unsigned int val = 0;
247 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
248 __func__, ioread32(I2C_REG_STS(alg_data)));
250 /* Check, whether there is already data,
251 * or we didn't 'ask' for it yet.
253 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
254 dev_dbg(&adap->dev, "%s(): Write dummy data to fill "
255 "Rx-fifo...\n", __func__);
257 if (alg_data->mif.len == 1) {
258 /* Last byte, do not acknowledge next rcv. */
264 * Enable interrupt RFDAIE (data in Rx fifo),
265 * and disable DRMIE (need data for Tx)
267 ctl = ioread32(I2C_REG_CTL(alg_data));
268 ctl |= mcntrl_rffie | mcntrl_daie;
269 ctl &= ~mcntrl_drmie;
270 iowrite32(ctl, I2C_REG_CTL(alg_data));
274 * Now we'll 'ask' for data:
275 * For each byte we want to receive, we must
276 * write a (dummy) byte to the Tx-FIFO.
278 iowrite32(val, I2C_REG_TX(alg_data));
284 if (alg_data->mif.len > 0) {
285 val = ioread32(I2C_REG_RX(alg_data));
286 *alg_data->mif.buf++ = (u8) (val & 0xff);
287 dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val,
291 if (alg_data->mif.len == 0) {
293 /* Wait until the STOP is seen. */
294 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
295 dev_err(&adap->dev, "The bus is still "
296 "active after timeout\n");
298 /* Disable master interrupts */
299 ctl = ioread32(I2C_REG_CTL(alg_data));
300 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
301 mcntrl_drmie | mcntrl_daie);
302 iowrite32(ctl, I2C_REG_CTL(alg_data));
305 del_timer_sync(&alg_data->mif.timer);
306 complete(&alg_data->mif.complete);
310 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
311 __func__, ioread32(I2C_REG_STS(alg_data)));
316 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
319 struct i2c_adapter *adap = dev_id;
320 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
322 dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n",
324 ioread32(I2C_REG_STS(alg_data)),
325 ioread32(I2C_REG_CTL(alg_data)),
327 stat = ioread32(I2C_REG_STS(alg_data));
329 /* let's see what kind of event this is */
330 if (stat & mstatus_afi) {
331 /* We lost arbitration in the midst of a transfer */
332 alg_data->mif.ret = -EIO;
334 /* Disable master interrupts. */
335 ctl = ioread32(I2C_REG_CTL(alg_data));
336 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
338 iowrite32(ctl, I2C_REG_CTL(alg_data));
340 /* Stop timer, to prevent timeout. */
341 del_timer_sync(&alg_data->mif.timer);
342 complete(&alg_data->mif.complete);
343 } else if (stat & mstatus_nai) {
344 /* Slave did not acknowledge, generate a STOP */
345 dev_dbg(&adap->dev, "%s(): "
346 "Slave did not acknowledge, generating a STOP.\n",
350 /* Disable master interrupts. */
351 ctl = ioread32(I2C_REG_CTL(alg_data));
352 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
354 iowrite32(ctl, I2C_REG_CTL(alg_data));
356 /* Our return value. */
357 alg_data->mif.ret = -EIO;
359 /* Stop timer, to prevent timeout. */
360 del_timer_sync(&alg_data->mif.timer);
361 complete(&alg_data->mif.complete);
365 * - Master Tx needs data.
366 * - There is data in the Rx-fifo
367 * The latter is only the case if we have requested for data,
368 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
369 * We therefore check, as a sanity check, whether that interrupt
372 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
373 if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
374 i2c_pnx_master_xmit(adap);
375 } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
376 i2c_pnx_master_rcv(adap);
381 /* Clear TDI and AFI bits */
382 stat = ioread32(I2C_REG_STS(alg_data));
383 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
385 dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n",
386 __func__, ioread32(I2C_REG_STS(alg_data)),
387 ioread32(I2C_REG_CTL(alg_data)));
392 static void i2c_pnx_timeout(unsigned long data)
394 struct i2c_adapter *adap = (struct i2c_adapter *)data;
395 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
398 dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. "
399 "Resetting master...\n",
400 ioread32(I2C_REG_STS(alg_data)),
401 ioread32(I2C_REG_CTL(alg_data)));
403 /* Reset master and disable interrupts */
404 ctl = ioread32(I2C_REG_CTL(alg_data));
405 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
406 iowrite32(ctl, I2C_REG_CTL(alg_data));
409 iowrite32(ctl, I2C_REG_CTL(alg_data));
410 wait_reset(I2C_PNX_TIMEOUT, alg_data);
411 alg_data->mif.ret = -EIO;
412 complete(&alg_data->mif.complete);
415 static inline void bus_reset_if_active(struct i2c_adapter *adap)
417 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
420 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
422 "%s: Bus is still active after xfer. Reset it...\n",
424 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
425 I2C_REG_CTL(alg_data));
426 wait_reset(I2C_PNX_TIMEOUT, alg_data);
427 } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
428 /* If there is data in the fifo's after transfer,
429 * flush fifo's by reset.
431 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
432 I2C_REG_CTL(alg_data));
433 wait_reset(I2C_PNX_TIMEOUT, alg_data);
434 } else if (stat & mstatus_nai) {
435 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
436 I2C_REG_CTL(alg_data));
437 wait_reset(I2C_PNX_TIMEOUT, alg_data);
442 * i2c_pnx_xfer - generic transfer entry point
443 * @adap: pointer to I2C adapter structure
444 * @msgs: array of messages
445 * @num: number of messages
447 * Initiates the transfer
450 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
452 struct i2c_msg *pmsg;
453 int rc = 0, completed = 0, i;
454 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
455 u32 stat = ioread32(I2C_REG_STS(alg_data));
457 dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n",
458 __func__, num, ioread32(I2C_REG_STS(alg_data)));
460 bus_reset_if_active(adap);
462 /* Process transactions in a loop. */
463 for (i = 0; rc >= 0 && i < num; i++) {
469 if (pmsg->flags & I2C_M_TEN) {
471 "%s: 10 bits addr not supported!\n",
477 alg_data->mif.buf = pmsg->buf;
478 alg_data->mif.len = pmsg->len;
479 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
480 I2C_SMBUS_READ : I2C_SMBUS_WRITE;
481 alg_data->mif.ret = 0;
482 alg_data->last = (i == num - 1);
484 dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__,
488 i2c_pnx_arm_timer(adap);
490 /* initialize the completion var */
491 init_completion(&alg_data->mif.complete);
493 /* Enable master interrupt */
494 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
495 mcntrl_naie | mcntrl_drmie,
496 I2C_REG_CTL(alg_data));
498 /* Put start-code and slave-address on the bus. */
499 rc = i2c_pnx_start(addr, adap);
503 /* Wait for completion */
504 wait_for_completion(&alg_data->mif.complete);
506 if (!(rc = alg_data->mif.ret))
508 dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n",
511 /* Clear TDI and AFI bits in case they are set. */
512 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
514 "%s: TDI still set... clearing now.\n",
516 iowrite32(stat, I2C_REG_STS(alg_data));
518 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
520 "%s: AFI still set... clearing now.\n",
522 iowrite32(stat, I2C_REG_STS(alg_data));
526 bus_reset_if_active(adap);
528 /* Cleanup to be sure... */
529 alg_data->mif.buf = NULL;
530 alg_data->mif.len = 0;
532 dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n",
533 __func__, ioread32(I2C_REG_STS(alg_data)));
535 if (completed != num)
536 return ((rc < 0) ? rc : -EREMOTEIO);
541 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
543 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
546 static struct i2c_algorithm pnx_algorithm = {
547 .master_xfer = i2c_pnx_xfer,
548 .functionality = i2c_pnx_func,
552 static int i2c_pnx_controller_suspend(struct platform_device *pdev,
555 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
556 struct i2c_pnx_algo_data *alg_data = i2c_pnx->adapter->algo_data;
558 /* FIXME: shouldn't this be clk_disable? */
559 clk_enable(alg_data->clk);
564 static int i2c_pnx_controller_resume(struct platform_device *pdev)
566 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
567 struct i2c_pnx_algo_data *alg_data = i2c_pnx->adapter->algo_data;
569 return clk_enable(alg_data->clk);
572 #define i2c_pnx_controller_suspend NULL
573 #define i2c_pnx_controller_resume NULL
576 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
580 struct i2c_pnx_algo_data *alg_data;
582 struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
584 if (!i2c_pnx || !i2c_pnx->adapter) {
585 dev_err(&pdev->dev, "%s: no platform data supplied\n",
591 platform_set_drvdata(pdev, i2c_pnx);
593 i2c_pnx->adapter->algo = &pnx_algorithm;
594 alg_data = i2c_pnx->adapter->algo_data;
596 alg_data->clk = clk_get(&pdev->dev, NULL);
597 if (IS_ERR(alg_data->clk)) {
598 ret = PTR_ERR(alg_data->clk);
602 if (i2c_pnx->calculate_input_freq)
603 freq_mhz = i2c_pnx->calculate_input_freq(pdev);
605 freq_mhz = PNX_DEFAULT_FREQ;
606 dev_info(&pdev->dev, "Setting bus frequency to default value: "
607 "%d MHz\n", freq_mhz);
610 init_timer(&alg_data->mif.timer);
611 alg_data->mif.timer.function = i2c_pnx_timeout;
612 alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter;
614 /* Register I/O resource */
615 if (!request_mem_region(alg_data->base, I2C_PNX_REGION_SIZE,
618 "I/O region 0x%08x for I2C already in use.\n",
624 if (!(alg_data->ioaddr =
625 (u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) {
626 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
631 ret = clk_enable(alg_data->clk);
636 * Clock Divisor High This value is the number of system clocks
637 * the serial clock (SCL) will be high.
638 * For example, if the system clock period is 50 ns and the maximum
639 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
640 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
641 * programmed into CLKHI will vary from this slightly due to
642 * variations in the output pad's rise and fall times as well as
643 * the deglitching filter length.
646 tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
647 iowrite32(tmp, I2C_REG_CKH(alg_data));
648 iowrite32(tmp, I2C_REG_CKL(alg_data));
650 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
651 if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
655 init_completion(&alg_data->mif.complete);
657 ret = request_irq(alg_data->irq, i2c_pnx_interrupt,
658 0, pdev->name, i2c_pnx->adapter);
662 /* Register this adapter with the I2C subsystem */
663 i2c_pnx->adapter->dev.parent = &pdev->dev;
664 i2c_pnx->adapter->nr = pdev->id;
665 ret = i2c_add_numbered_adapter(i2c_pnx->adapter);
667 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
671 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
672 i2c_pnx->adapter->name, alg_data->base, alg_data->irq);
677 free_irq(alg_data->irq, i2c_pnx->adapter);
679 clk_disable(alg_data->clk);
681 iounmap((void *)alg_data->ioaddr);
683 release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE);
685 clk_put(alg_data->clk);
687 platform_set_drvdata(pdev, NULL);
692 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
694 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
695 struct i2c_adapter *adap = i2c_pnx->adapter;
696 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
698 free_irq(alg_data->irq, i2c_pnx->adapter);
699 i2c_del_adapter(adap);
700 clk_disable(alg_data->clk);
701 iounmap((void *)alg_data->ioaddr);
702 release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE);
703 clk_put(alg_data->clk);
704 platform_set_drvdata(pdev, NULL);
709 static struct platform_driver i2c_pnx_driver = {
712 .owner = THIS_MODULE,
714 .probe = i2c_pnx_probe,
715 .remove = __devexit_p(i2c_pnx_remove),
716 .suspend = i2c_pnx_controller_suspend,
717 .resume = i2c_pnx_controller_resume,
720 static int __init i2c_adap_pnx_init(void)
722 return platform_driver_register(&i2c_pnx_driver);
725 static void __exit i2c_adap_pnx_exit(void)
727 platform_driver_unregister(&i2c_pnx_driver);
730 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
731 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
732 MODULE_LICENSE("GPL");
733 MODULE_ALIAS("platform:pnx-i2c");
735 /* We need to make sure I2C is initialized before USB */
736 subsys_initcall(i2c_adap_pnx_init);
737 module_exit(i2c_adap_pnx_exit);