2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5 * Vitaly Wool <vwool@ru.mvista.com>
7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
26 #include <mach/hardware.h>
29 #include <asm/uaccess.h>
31 #define I2C_PNX_TIMEOUT 10 /* msec */
32 #define I2C_PNX_SPEED_KHZ 100
33 #define I2C_PNX_REGION_SIZE 0x100
35 static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
38 (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
42 return (timeout <= 0);
45 static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
48 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
52 return (timeout <= 0);
55 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
57 struct timer_list *timer = &alg_data->mif.timer;
58 int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
63 del_timer_sync(timer);
65 dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %u jiffies.\n",
68 timer->expires = jiffies + expires;
69 timer->data = (unsigned long)&alg_data;
75 * i2c_pnx_start - start a device
76 * @slave_addr: slave address
77 * @adap: pointer to adapter structure
79 * Generate a START signal in the desired mode.
81 static int i2c_pnx_start(unsigned char slave_addr,
82 struct i2c_pnx_algo_data *alg_data)
84 dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
85 slave_addr, alg_data->mif.mode);
87 /* Check for 7 bit slave addresses only */
88 if (slave_addr & ~0x7f) {
89 dev_err(&alg_data->adapter.dev,
90 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
91 alg_data->adapter.name, slave_addr);
95 /* First, make sure bus is idle */
96 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
97 /* Somebody else is monopolizing the bus */
98 dev_err(&alg_data->adapter.dev,
99 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
100 alg_data->adapter.name, slave_addr,
101 ioread32(I2C_REG_CTL(alg_data)),
102 ioread32(I2C_REG_STS(alg_data)));
104 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
105 /* Sorry, we lost the bus */
106 dev_err(&alg_data->adapter.dev,
107 "%s: Arbitration failure. Slave addr = %02x\n",
108 alg_data->adapter.name, slave_addr);
113 * OK, I2C is enabled and we have the bus.
114 * Clear the current TDI and AFI status flags.
116 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
117 I2C_REG_STS(alg_data));
119 dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
120 (slave_addr << 1) | start_bit | alg_data->mif.mode);
122 /* Write the slave address, START bit and R/W bit */
123 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
124 I2C_REG_TX(alg_data));
126 dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
132 * i2c_pnx_stop - stop a device
133 * @adap: pointer to I2C adapter structure
135 * Generate a STOP signal to terminate the master transaction.
137 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
139 /* Only 1 msec max timeout due to interrupt context */
142 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
143 __func__, ioread32(I2C_REG_STS(alg_data)));
145 /* Write a STOP bit to TX FIFO */
146 iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
148 /* Wait until the STOP is seen. */
149 while (timeout > 0 &&
150 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
151 /* may be called from interrupt context */
156 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
157 __func__, ioread32(I2C_REG_STS(alg_data)));
161 * i2c_pnx_master_xmit - transmit data to slave
162 * @adap: pointer to I2C adapter structure
164 * Sends one byte of data to the slave
166 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
170 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
171 __func__, ioread32(I2C_REG_STS(alg_data)));
173 if (alg_data->mif.len > 0) {
174 /* We still have something to talk about... */
175 val = *alg_data->mif.buf++;
177 if (alg_data->mif.len == 1) {
184 iowrite32(val, I2C_REG_TX(alg_data));
186 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
187 __func__, val, alg_data->mif.len + 1);
189 if (alg_data->mif.len == 0) {
190 if (alg_data->last) {
191 /* Wait until the STOP is seen. */
192 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
193 dev_err(&alg_data->adapter.dev,
194 "The bus is still active after timeout\n");
196 /* Disable master interrupts */
197 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
198 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
199 I2C_REG_CTL(alg_data));
201 del_timer_sync(&alg_data->mif.timer);
203 dev_dbg(&alg_data->adapter.dev,
204 "%s(): Waking up xfer routine.\n",
207 complete(&alg_data->mif.complete);
209 } else if (alg_data->mif.len == 0) {
210 /* zero-sized transfer */
211 i2c_pnx_stop(alg_data);
213 /* Disable master interrupts. */
214 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
215 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
216 I2C_REG_CTL(alg_data));
219 del_timer_sync(&alg_data->mif.timer);
220 dev_dbg(&alg_data->adapter.dev,
221 "%s(): Waking up xfer routine after zero-xfer.\n",
224 complete(&alg_data->mif.complete);
227 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
228 __func__, ioread32(I2C_REG_STS(alg_data)));
234 * i2c_pnx_master_rcv - receive data from slave
235 * @adap: pointer to I2C adapter structure
237 * Reads one byte data from the slave
239 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
241 unsigned int val = 0;
244 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
245 __func__, ioread32(I2C_REG_STS(alg_data)));
247 /* Check, whether there is already data,
248 * or we didn't 'ask' for it yet.
250 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
251 dev_dbg(&alg_data->adapter.dev,
252 "%s(): Write dummy data to fill Rx-fifo...\n",
255 if (alg_data->mif.len == 1) {
256 /* Last byte, do not acknowledge next rcv. */
262 * Enable interrupt RFDAIE (data in Rx fifo),
263 * and disable DRMIE (need data for Tx)
265 ctl = ioread32(I2C_REG_CTL(alg_data));
266 ctl |= mcntrl_rffie | mcntrl_daie;
267 ctl &= ~mcntrl_drmie;
268 iowrite32(ctl, I2C_REG_CTL(alg_data));
272 * Now we'll 'ask' for data:
273 * For each byte we want to receive, we must
274 * write a (dummy) byte to the Tx-FIFO.
276 iowrite32(val, I2C_REG_TX(alg_data));
282 if (alg_data->mif.len > 0) {
283 val = ioread32(I2C_REG_RX(alg_data));
284 *alg_data->mif.buf++ = (u8) (val & 0xff);
285 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
286 __func__, val, alg_data->mif.len);
289 if (alg_data->mif.len == 0) {
291 /* Wait until the STOP is seen. */
292 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
293 dev_err(&alg_data->adapter.dev,
294 "The bus is still active after timeout\n");
296 /* Disable master interrupts */
297 ctl = ioread32(I2C_REG_CTL(alg_data));
298 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
299 mcntrl_drmie | mcntrl_daie);
300 iowrite32(ctl, I2C_REG_CTL(alg_data));
303 del_timer_sync(&alg_data->mif.timer);
304 complete(&alg_data->mif.complete);
308 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
309 __func__, ioread32(I2C_REG_STS(alg_data)));
314 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
316 struct i2c_pnx_algo_data *alg_data = dev_id;
319 dev_dbg(&alg_data->adapter.dev,
320 "%s(): mstat = %x mctrl = %x, mode = %d\n",
322 ioread32(I2C_REG_STS(alg_data)),
323 ioread32(I2C_REG_CTL(alg_data)),
325 stat = ioread32(I2C_REG_STS(alg_data));
327 /* let's see what kind of event this is */
328 if (stat & mstatus_afi) {
329 /* We lost arbitration in the midst of a transfer */
330 alg_data->mif.ret = -EIO;
332 /* Disable master interrupts. */
333 ctl = ioread32(I2C_REG_CTL(alg_data));
334 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
336 iowrite32(ctl, I2C_REG_CTL(alg_data));
338 /* Stop timer, to prevent timeout. */
339 del_timer_sync(&alg_data->mif.timer);
340 complete(&alg_data->mif.complete);
341 } else if (stat & mstatus_nai) {
342 /* Slave did not acknowledge, generate a STOP */
343 dev_dbg(&alg_data->adapter.dev,
344 "%s(): Slave did not acknowledge, generating a STOP.\n",
346 i2c_pnx_stop(alg_data);
348 /* Disable master interrupts. */
349 ctl = ioread32(I2C_REG_CTL(alg_data));
350 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
352 iowrite32(ctl, I2C_REG_CTL(alg_data));
354 /* Our return value. */
355 alg_data->mif.ret = -EIO;
357 /* Stop timer, to prevent timeout. */
358 del_timer_sync(&alg_data->mif.timer);
359 complete(&alg_data->mif.complete);
363 * - Master Tx needs data.
364 * - There is data in the Rx-fifo
365 * The latter is only the case if we have requested for data,
366 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
367 * We therefore check, as a sanity check, whether that interrupt
370 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
371 if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
372 i2c_pnx_master_xmit(alg_data);
373 } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
374 i2c_pnx_master_rcv(alg_data);
379 /* Clear TDI and AFI bits */
380 stat = ioread32(I2C_REG_STS(alg_data));
381 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
383 dev_dbg(&alg_data->adapter.dev,
384 "%s(): exiting, stat = %x ctrl = %x.\n",
385 __func__, ioread32(I2C_REG_STS(alg_data)),
386 ioread32(I2C_REG_CTL(alg_data)));
391 static void i2c_pnx_timeout(unsigned long data)
393 struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
396 dev_err(&alg_data->adapter.dev,
397 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
398 ioread32(I2C_REG_STS(alg_data)),
399 ioread32(I2C_REG_CTL(alg_data)));
401 /* Reset master and disable interrupts */
402 ctl = ioread32(I2C_REG_CTL(alg_data));
403 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
404 iowrite32(ctl, I2C_REG_CTL(alg_data));
407 iowrite32(ctl, I2C_REG_CTL(alg_data));
408 wait_reset(I2C_PNX_TIMEOUT, alg_data);
409 alg_data->mif.ret = -EIO;
410 complete(&alg_data->mif.complete);
413 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
417 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
418 dev_err(&alg_data->adapter.dev,
419 "%s: Bus is still active after xfer. Reset it...\n",
420 alg_data->adapter.name);
421 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
422 I2C_REG_CTL(alg_data));
423 wait_reset(I2C_PNX_TIMEOUT, alg_data);
424 } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
425 /* If there is data in the fifo's after transfer,
426 * flush fifo's by reset.
428 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
429 I2C_REG_CTL(alg_data));
430 wait_reset(I2C_PNX_TIMEOUT, alg_data);
431 } else if (stat & mstatus_nai) {
432 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
433 I2C_REG_CTL(alg_data));
434 wait_reset(I2C_PNX_TIMEOUT, alg_data);
439 * i2c_pnx_xfer - generic transfer entry point
440 * @adap: pointer to I2C adapter structure
441 * @msgs: array of messages
442 * @num: number of messages
444 * Initiates the transfer
447 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
449 struct i2c_msg *pmsg;
450 int rc = 0, completed = 0, i;
451 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
452 u32 stat = ioread32(I2C_REG_STS(alg_data));
454 dev_dbg(&alg_data->adapter.dev,
455 "%s(): entering: %d messages, stat = %04x.\n",
456 __func__, num, ioread32(I2C_REG_STS(alg_data)));
458 bus_reset_if_active(alg_data);
460 /* Process transactions in a loop. */
461 for (i = 0; rc >= 0 && i < num; i++) {
467 if (pmsg->flags & I2C_M_TEN) {
468 dev_err(&alg_data->adapter.dev,
469 "%s: 10 bits addr not supported!\n",
470 alg_data->adapter.name);
475 alg_data->mif.buf = pmsg->buf;
476 alg_data->mif.len = pmsg->len;
477 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
478 I2C_SMBUS_READ : I2C_SMBUS_WRITE;
479 alg_data->mif.ret = 0;
480 alg_data->last = (i == num - 1);
482 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
483 __func__, alg_data->mif.mode, alg_data->mif.len);
485 i2c_pnx_arm_timer(alg_data);
487 /* initialize the completion var */
488 init_completion(&alg_data->mif.complete);
490 /* Enable master interrupt */
491 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
492 mcntrl_naie | mcntrl_drmie,
493 I2C_REG_CTL(alg_data));
495 /* Put start-code and slave-address on the bus. */
496 rc = i2c_pnx_start(addr, alg_data);
500 /* Wait for completion */
501 wait_for_completion(&alg_data->mif.complete);
503 if (!(rc = alg_data->mif.ret))
505 dev_dbg(&alg_data->adapter.dev,
506 "%s(): Complete, return code = %d.\n",
509 /* Clear TDI and AFI bits in case they are set. */
510 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
511 dev_dbg(&alg_data->adapter.dev,
512 "%s: TDI still set... clearing now.\n",
513 alg_data->adapter.name);
514 iowrite32(stat, I2C_REG_STS(alg_data));
516 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
517 dev_dbg(&alg_data->adapter.dev,
518 "%s: AFI still set... clearing now.\n",
519 alg_data->adapter.name);
520 iowrite32(stat, I2C_REG_STS(alg_data));
524 bus_reset_if_active(alg_data);
526 /* Cleanup to be sure... */
527 alg_data->mif.buf = NULL;
528 alg_data->mif.len = 0;
530 dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
531 __func__, ioread32(I2C_REG_STS(alg_data)));
533 if (completed != num)
534 return ((rc < 0) ? rc : -EREMOTEIO);
539 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
541 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
544 static struct i2c_algorithm pnx_algorithm = {
545 .master_xfer = i2c_pnx_xfer,
546 .functionality = i2c_pnx_func,
550 static int i2c_pnx_controller_suspend(struct platform_device *pdev,
553 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
555 /* FIXME: shouldn't this be clk_disable? */
556 clk_enable(alg_data->clk);
561 static int i2c_pnx_controller_resume(struct platform_device *pdev)
563 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
565 return clk_enable(alg_data->clk);
568 #define i2c_pnx_controller_suspend NULL
569 #define i2c_pnx_controller_resume NULL
572 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
576 struct i2c_pnx_algo_data *alg_data;
578 struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
580 if (!i2c_pnx || !i2c_pnx->name) {
581 dev_err(&pdev->dev, "%s: no platform data supplied\n",
587 alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
593 platform_set_drvdata(pdev, alg_data);
595 strlcpy(alg_data->adapter.name, i2c_pnx->name,
596 sizeof(alg_data->adapter.name));
597 alg_data->adapter.dev.parent = &pdev->dev;
598 alg_data->adapter.algo = &pnx_algorithm;
599 alg_data->adapter.algo_data = alg_data;
600 alg_data->adapter.nr = pdev->id;
601 alg_data->i2c_pnx = i2c_pnx;
603 alg_data->clk = clk_get(&pdev->dev, NULL);
604 if (IS_ERR(alg_data->clk)) {
605 ret = PTR_ERR(alg_data->clk);
609 init_timer(&alg_data->mif.timer);
610 alg_data->mif.timer.function = i2c_pnx_timeout;
611 alg_data->mif.timer.data = (unsigned long)alg_data;
613 /* Register I/O resource */
614 if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
617 "I/O region 0x%08x for I2C already in use.\n",
623 alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
624 if (!alg_data->ioaddr) {
625 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
630 ret = clk_enable(alg_data->clk);
634 freq = clk_get_rate(alg_data->clk);
637 * Clock Divisor High This value is the number of system clocks
638 * the serial clock (SCL) will be high.
639 * For example, if the system clock period is 50 ns and the maximum
640 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
641 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
642 * programmed into CLKHI will vary from this slightly due to
643 * variations in the output pad's rise and fall times as well as
644 * the deglitching filter length.
647 tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
648 iowrite32(tmp, I2C_REG_CKH(alg_data));
649 iowrite32(tmp, I2C_REG_CKL(alg_data));
651 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
652 if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
656 init_completion(&alg_data->mif.complete);
658 ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
659 0, pdev->name, alg_data);
663 /* Register this adapter with the I2C subsystem */
664 ret = i2c_add_numbered_adapter(&alg_data->adapter);
666 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
670 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
671 alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
676 free_irq(i2c_pnx->irq, alg_data);
678 clk_disable(alg_data->clk);
680 iounmap(alg_data->ioaddr);
682 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
684 clk_put(alg_data->clk);
688 platform_set_drvdata(pdev, NULL);
693 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
695 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
696 struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
698 free_irq(i2c_pnx->irq, alg_data);
699 i2c_del_adapter(&alg_data->adapter);
700 clk_disable(alg_data->clk);
701 iounmap(alg_data->ioaddr);
702 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
703 clk_put(alg_data->clk);
705 platform_set_drvdata(pdev, NULL);
710 static struct platform_driver i2c_pnx_driver = {
713 .owner = THIS_MODULE,
715 .probe = i2c_pnx_probe,
716 .remove = __devexit_p(i2c_pnx_remove),
717 .suspend = i2c_pnx_controller_suspend,
718 .resume = i2c_pnx_controller_resume,
721 static int __init i2c_adap_pnx_init(void)
723 return platform_driver_register(&i2c_pnx_driver);
726 static void __exit i2c_adap_pnx_exit(void)
728 platform_driver_unregister(&i2c_pnx_driver);
731 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
732 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
733 MODULE_LICENSE("GPL");
734 MODULE_ALIAS("platform:pnx-i2c");
736 /* We need to make sure I2C is initialized before USB */
737 subsys_initcall(i2c_adap_pnx_init);
738 module_exit(i2c_adap_pnx_exit);