SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/slab.h>
  41
  42 /* I2C controller revisions */
  43 #define OMAP_I2C_REV_2                  0x20
  44
  45 /* I2C controller revisions present on specific hardware */
  46 #define OMAP_I2C_REV_ON_2430            0x36
  47 #define OMAP_I2C_REV_ON_3430            0x3C
  48 #define OMAP_I2C_REV_ON_4430            0x40
  49
  50 /* timeout waiting for the controller to respond */
  51 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  52
  53 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  54 enum {
  55         OMAP_I2C_REV_REG = 0,
  56         OMAP_I2C_IE_REG,
  57         OMAP_I2C_STAT_REG,
  58         OMAP_I2C_IV_REG,
  59         OMAP_I2C_WE_REG,
  60         OMAP_I2C_SYSS_REG,
  61         OMAP_I2C_BUF_REG,
  62         OMAP_I2C_CNT_REG,
  63         OMAP_I2C_DATA_REG,
  64         OMAP_I2C_SYSC_REG,
  65         OMAP_I2C_CON_REG,
  66         OMAP_I2C_OA_REG,
  67         OMAP_I2C_SA_REG,
  68         OMAP_I2C_PSC_REG,
  69         OMAP_I2C_SCLL_REG,
  70         OMAP_I2C_SCLH_REG,
  71         OMAP_I2C_SYSTEST_REG,
  72         OMAP_I2C_BUFSTAT_REG,
  73         OMAP_I2C_REVNB_LO,
  74         OMAP_I2C_REVNB_HI,
  75         OMAP_I2C_IRQSTATUS_RAW,
  76         OMAP_I2C_IRQENABLE_SET,
  77         OMAP_I2C_IRQENABLE_CLR,
  78 };
  79
  80 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  81 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  82 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  83 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  84 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  85 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  86 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  87 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  88
  89 /* I2C Status Register (OMAP_I2C_STAT): */
  90 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  91 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  92 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  93 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  94 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  95 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  96 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  97 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  98 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  99 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 100 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 101 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 102
 103 /* I2C WE wakeup enable register */
 104 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 105 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 106 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 107 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 108 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 109 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 110 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 111 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 112 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 113 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 114
 115 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 116                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 117                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 118                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 119                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 120
 121 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 122 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 123 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 124 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 125 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 126
 127 /* I2C Configuration Register (OMAP_I2C_CON): */
 128 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 129 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 130 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 131 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 132 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 133 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 134 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 135 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 136 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 137 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 138
 139 /* I2C SCL time value when Master */
 140 #define OMAP_I2C_SCLL_HSSCLL    8
 141 #define OMAP_I2C_SCLH_HSSCLH    8
 142
 143 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 144 #ifdef DEBUG
 145 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 146 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 147 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 148 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 149 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 150 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 151 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 152 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 153 #endif
 154
 155 /* OCP_SYSSTATUS bit definitions */
 156 #define SYSS_RESETDONE_MASK             (1 << 0)
 157
 158 /* OCP_SYSCONFIG bit definitions */
 159 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 160 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 161 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 162 #define SYSC_SOFTRESET_MASK             (1 << 1)
 163 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 164
 165 #define SYSC_IDLEMODE_SMART             0x2
 166 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 167
 168
 169 struct omap_i2c_dev {
 170         struct device           *dev;
 171         void __iomem            *base;          /* virtual */
 172         int                     irq;
 173         int                     reg_shift;      /* bit shift for I2C register addresses */
 174         struct clk              *iclk;          /* Interface clock */
 175         struct clk              *fclk;          /* Functional clock */
 176         struct completion       cmd_complete;
 177         struct resource         *ioarea;
 178         u32                     speed;          /* Speed of bus in Khz */
 179         u16                     cmd_err;
 180         u8                      *buf;
 181         u8                      *regs;
 182         size_t                  buf_len;
 183         struct i2c_adapter      adapter;
 184         u8                      fifo_size;      /* use as flag and value
 185                                                  * fifo_size==0 implies no fifo
 186                                                  * if set, should be trsh+1
 187                                                  */
 188         u8                      rev;
 189         unsigned                b_hw:1;         /* bad h/w fixes */
 190         unsigned                idle:1;
 191         u16                     iestate;        /* Saved interrupt register */
 192         u16                     pscstate;
 193         u16                     scllstate;
 194         u16                     sclhstate;
 195         u16                     bufstate;
 196         u16                     syscstate;
 197         u16                     westate;
 198 };
 199
 200 const static u8 reg_map[] = {
 201         [OMAP_I2C_REV_REG] = 0x00,
 202         [OMAP_I2C_IE_REG] = 0x01,
 203         [OMAP_I2C_STAT_REG] = 0x02,
 204         [OMAP_I2C_IV_REG] = 0x03,
 205         [OMAP_I2C_WE_REG] = 0x03,
 206         [OMAP_I2C_SYSS_REG] = 0x04,
 207         [OMAP_I2C_BUF_REG] = 0x05,
 208         [OMAP_I2C_CNT_REG] = 0x06,
 209         [OMAP_I2C_DATA_REG] = 0x07,
 210         [OMAP_I2C_SYSC_REG] = 0x08,
 211         [OMAP_I2C_CON_REG] = 0x09,
 212         [OMAP_I2C_OA_REG] = 0x0a,
 213         [OMAP_I2C_SA_REG] = 0x0b,
 214         [OMAP_I2C_PSC_REG] = 0x0c,
 215         [OMAP_I2C_SCLL_REG] = 0x0d,
 216         [OMAP_I2C_SCLH_REG] = 0x0e,
 217         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 218         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 219 };
 220
 221 const static u8 omap4_reg_map[] = {
 222         [OMAP_I2C_REV_REG] = 0x04,
 223         [OMAP_I2C_IE_REG] = 0x2c,
 224         [OMAP_I2C_STAT_REG] = 0x28,
 225         [OMAP_I2C_IV_REG] = 0x34,
 226         [OMAP_I2C_WE_REG] = 0x34,
 227         [OMAP_I2C_SYSS_REG] = 0x90,
 228         [OMAP_I2C_BUF_REG] = 0x94,
 229         [OMAP_I2C_CNT_REG] = 0x98,
 230         [OMAP_I2C_DATA_REG] = 0x9c,
 231         [OMAP_I2C_SYSC_REG] = 0x20,
 232         [OMAP_I2C_CON_REG] = 0xa4,
 233         [OMAP_I2C_OA_REG] = 0xa8,
 234         [OMAP_I2C_SA_REG] = 0xac,
 235         [OMAP_I2C_PSC_REG] = 0xb0,
 236         [OMAP_I2C_SCLL_REG] = 0xb4,
 237         [OMAP_I2C_SCLH_REG] = 0xb8,
 238         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 239         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 240         [OMAP_I2C_REVNB_LO] = 0x00,
 241         [OMAP_I2C_REVNB_HI] = 0x04,
 242         [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
 243         [OMAP_I2C_IRQENABLE_SET] = 0x2c,
 244         [OMAP_I2C_IRQENABLE_CLR] = 0x30,
 245 };
 246
 247 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 248                                       int reg, u16 val)
 249 {
 250         __raw_writew(val, i2c_dev->base +
 251                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 252 }
 253
 254 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 255 {
 256         return __raw_readw(i2c_dev->base +
 257                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 258 }
 259
 260 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 261 {
 262         int ret;
 263
 264         dev->iclk = clk_get(dev->dev, "ick");
 265         if (IS_ERR(dev->iclk)) {
 266                 ret = PTR_ERR(dev->iclk);
 267                 dev->iclk = NULL;
 268                 return ret;
 269         }
 270
 271         dev->fclk = clk_get(dev->dev, "fck");
 272         if (IS_ERR(dev->fclk)) {
 273                 ret = PTR_ERR(dev->fclk);
 274                 if (dev->iclk != NULL) {
 275                         clk_put(dev->iclk);
 276                         dev->iclk = NULL;
 277                 }
 278                 dev->fclk = NULL;
 279                 return ret;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 286 {
 287         clk_put(dev->fclk);
 288         dev->fclk = NULL;
 289         clk_put(dev->iclk);
 290         dev->iclk = NULL;
 291 }
 292
 293 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 294 {
 295         WARN_ON(!dev->idle);
 296
 297         clk_enable(dev->iclk);
 298         clk_enable(dev->fclk);
 299         if (cpu_is_omap34xx()) {
 300                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 301                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 302                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 303                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 304                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 305                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 306                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 307                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 308         }
 309         dev->idle = 0;
 310
 311         /*
 312          * Don't write to this register if the IE state is 0 as it can
 313          * cause deadlock.
 314          */
 315         if (dev->iestate)
 316                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 317 }
 318
 319 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 320 {
 321         u16 iv;
 322
 323         WARN_ON(dev->idle);
 324
 325         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 326         if (dev->rev >= OMAP_I2C_REV_ON_4430)
 327                 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
 328         else
 329                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 330
 331         if (dev->rev < OMAP_I2C_REV_2) {
 332                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 333         } else {
 334                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 335
 336                 /* Flush posted write before the dev->idle store occurs */
 337                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 338         }
 339         dev->idle = 1;
 340         clk_disable(dev->fclk);
 341         clk_disable(dev->iclk);
 342 }
 343
 344 static int omap_i2c_init(struct omap_i2c_dev *dev)
 345 {
 346         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 347         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 348         unsigned long fclk_rate = 12000000;
 349         unsigned long timeout;
 350         unsigned long internal_clk = 0;
 351
 352         if (dev->rev >= OMAP_I2C_REV_2) {
 353                 /* Disable I2C controller before soft reset */
 354                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 355                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 356                                 ~(OMAP_I2C_CON_EN));
 357
 358                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 359                 /* For some reason we need to set the EN bit before the
 360                  * reset done bit gets set. */
 361                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 362                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 363                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 364                          SYSS_RESETDONE_MASK)) {
 365                         if (time_after(jiffies, timeout)) {
 366                                 dev_warn(dev->dev, "timeout waiting "
 367                                                 "for controller reset\n");
 368                                 return -ETIMEDOUT;
 369                         }
 370                         msleep(1);
 371                 }
 372
 373                 /* SYSC register is cleared by the reset; rewrite it */
 374                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 375
 376                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 377                                            SYSC_AUTOIDLE_MASK);
 378
 379                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 380                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 381                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 382                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 383                               __ffs(SYSC_SIDLEMODE_MASK));
 384                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 385                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 386
 387                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 388                                                         dev->syscstate);
 389                         /*
 390                          * Enabling all wakup sources to stop I2C freezing on
 391                          * WFI instruction.
 392                          * REVISIT: Some wkup sources might not be needed.
 393                          */
 394                         dev->westate = OMAP_I2C_WE_ALL;
 395                         if (dev->rev < OMAP_I2C_REV_ON_4430)
 396                                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
 397                                                                 dev->westate);
 398                 }
 399         }
 400         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 401
 402         if (cpu_class_is_omap1()) {
 403                 /*
 404                  * The I2C functional clock is the armxor_ck, so there's
 405                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 406                  * always returns 12MHz for the functional clock, we can
 407                  * do this bit unconditionally.
 408                  */
 409                 fclk_rate = clk_get_rate(dev->fclk);
 410
 411                 /* TRM for 5912 says the I2C clock must be prescaled to be
 412                  * between 7 - 12 MHz. The XOR input clock is typically
 413                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 414                  *
 415                  * XOR MHz      Divider         Prescaler
 416                  * 12           1               0
 417                  * 13           2               1
 418                  * 19.2         2               1
 419                  */
 420                 if (fclk_rate > 12000000)
 421                         psc = fclk_rate / 12000000;
 422         }
 423
 424         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
 425
 426                 /*
 427                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 428                  * HS and for all modes on 2430. On 34xx we can use lower rate
 429                  * to get longer filter period for better noise suppression.
 430                  * The filter is iclk (fclk for HS) period.
 431                  */
 432                 if (dev->speed > 400 || cpu_is_omap2430())
 433                         internal_clk = 19200;
 434                 else if (dev->speed > 100)
 435                         internal_clk = 9600;
 436                 else
 437                         internal_clk = 4000;
 438                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 439
 440                 /* Compute prescaler divisor */
 441                 psc = fclk_rate / internal_clk;
 442                 psc = psc - 1;
 443
 444                 /* If configured for High Speed */
 445                 if (dev->speed > 400) {
 446                         unsigned long scl;
 447
 448                         /* For first phase of HS mode */
 449                         scl = internal_clk / 400;
 450                         fsscll = scl - (scl / 3) - 7;
 451                         fssclh = (scl / 3) - 5;
 452
 453                         /* For second phase of HS mode */
 454                         scl = fclk_rate / dev->speed;
 455                         hsscll = scl - (scl / 3) - 7;
 456                         hssclh = (scl / 3) - 5;
 457                 } else if (dev->speed > 100) {
 458                         unsigned long scl;
 459
 460                         /* Fast mode */
 461                         scl = internal_clk / dev->speed;
 462                         fsscll = scl - (scl / 3) - 7;
 463                         fssclh = (scl / 3) - 5;
 464                 } else {
 465                         /* Standard mode */
 466                         fsscll = internal_clk / (dev->speed * 2) - 7;
 467                         fssclh = internal_clk / (dev->speed * 2) - 5;
 468                 }
 469                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 470                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 471         } else {
 472                 /* Program desired operating rate */
 473                 fclk_rate /= (psc + 1) * 1000;
 474                 if (psc > 2)
 475                         psc = 2;
 476                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 477                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 478         }
 479
 480         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 481         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 482
 483         /* SCL low and high time values */
 484         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 485         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 486
 487         if (dev->fifo_size) {
 488                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 489                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 490                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 491                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 492         }
 493
 494         /* Take the I2C module out of reset: */
 495         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 496
 497         /* Enable interrupts */
 498         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 499                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 500                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 501                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 502         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 503         if (cpu_is_omap34xx()) {
 504                 dev->pscstate = psc;
 505                 dev->scllstate = scll;
 506                 dev->sclhstate = sclh;
 507                 dev->bufstate = buf;
 508         }
 509         return 0;
 510 }
 511
 512 /*
 513  * Waiting on Bus Busy
 514  */
 515 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 516 {
 517         unsigned long timeout;
 518
 519         timeout = jiffies + OMAP_I2C_TIMEOUT;
 520         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 521                 if (time_after(jiffies, timeout)) {
 522                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 523                         return -ETIMEDOUT;
 524                 }
 525                 msleep(1);
 526         }
 527
 528         return 0;
 529 }
 530
 531 /*
 532  * Low level master read/write transaction.
 533  */
 534 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 535                              struct i2c_msg *msg, int stop)
 536 {
 537         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 538         int r;
 539         u16 w;
 540
 541         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 542                 msg->addr, msg->len, msg->flags, stop);
 543
 544         if (msg->len == 0)
 545                 return -EINVAL;
 546
 547         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 548
 549         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 550         dev->buf = msg->buf;
 551         dev->buf_len = msg->len;
 552
 553         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 554
 555         /* Clear the FIFO Buffers */
 556         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 557         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 558         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 559
 560         init_completion(&dev->cmd_complete);
 561         dev->cmd_err = 0;
 562
 563         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 564
 565         /* High speed configuration */
 566         if (dev->speed > 400)
 567                 w |= OMAP_I2C_CON_OPMODE_HS;
 568
 569         if (msg->flags & I2C_M_TEN)
 570                 w |= OMAP_I2C_CON_XA;
 571         if (!(msg->flags & I2C_M_RD))
 572                 w |= OMAP_I2C_CON_TRX;
 573
 574         if (!dev->b_hw && stop)
 575                 w |= OMAP_I2C_CON_STP;
 576
 577         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 578
 579         /*
 580          * Don't write stt and stp together on some hardware.
 581          */
 582         if (dev->b_hw && stop) {
 583                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 584                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 585                 while (con & OMAP_I2C_CON_STT) {
 586                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 587
 588                         /* Let the user know if i2c is in a bad state */
 589                         if (time_after(jiffies, delay)) {
 590                                 dev_err(dev->dev, "controller timed out "
 591                                 "waiting for start condition to finish\n");
 592                                 return -ETIMEDOUT;
 593                         }
 594                         cpu_relax();
 595                 }
 596
 597                 w |= OMAP_I2C_CON_STP;
 598                 w &= ~OMAP_I2C_CON_STT;
 599                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 600         }
 601
 602         /*
 603          * REVISIT: We should abort the transfer on signals, but the bus goes
 604          * into arbitration and we're currently unable to recover from it.
 605          */
 606         r = wait_for_completion_timeout(&dev->cmd_complete,
 607                                         OMAP_I2C_TIMEOUT);
 608         dev->buf_len = 0;
 609         if (r < 0)
 610                 return r;
 611         if (r == 0) {
 612                 dev_err(dev->dev, "controller timed out\n");
 613                 omap_i2c_init(dev);
 614                 return -ETIMEDOUT;
 615         }
 616
 617         if (likely(!dev->cmd_err))
 618                 return 0;
 619
 620         /* We have an error */
 621         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 622                             OMAP_I2C_STAT_XUDF)) {
 623                 omap_i2c_init(dev);
 624                 return -EIO;
 625         }
 626
 627         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 628                 if (msg->flags & I2C_M_IGNORE_NAK)
 629                         return 0;
 630                 if (stop) {
 631                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 632                         w |= OMAP_I2C_CON_STP;
 633                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 634                 }
 635                 return -EREMOTEIO;
 636         }
 637         return -EIO;
 638 }
 639
 640
 641 /*
 642  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 643  * to do the work during IRQ processing.
 644  */
 645 static int
 646 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 647 {
 648         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 649         int i;
 650         int r;
 651
 652         omap_i2c_unidle(dev);
 653
 654         r = omap_i2c_wait_for_bb(dev);
 655         if (r < 0)
 656                 goto out;
 657
 658         for (i = 0; i < num; i++) {
 659                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 660                 if (r != 0)
 661                         break;
 662         }
 663
 664         if (r == 0)
 665                 r = num;
 666 out:
 667         omap_i2c_idle(dev);
 668         return r;
 669 }
 670
 671 static u32
 672 omap_i2c_func(struct i2c_adapter *adap)
 673 {
 674         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 675 }
 676
 677 static inline void
 678 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 679 {
 680         dev->cmd_err |= err;
 681         complete(&dev->cmd_complete);
 682 }
 683
 684 static inline void
 685 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 686 {
 687         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 688 }
 689
 690 /* rev1 devices are apparently only on some 15xx */
 691 #ifdef CONFIG_ARCH_OMAP15XX
 692
 693 static irqreturn_t
 694 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 695 {
 696         struct omap_i2c_dev *dev = dev_id;
 697         u16 iv, w;
 698
 699         if (dev->idle)
 700                 return IRQ_NONE;
 701
 702         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 703         switch (iv) {
 704         case 0x00:      /* None */
 705                 break;
 706         case 0x01:      /* Arbitration lost */
 707                 dev_err(dev->dev, "Arbitration lost\n");
 708                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 709                 break;
 710         case 0x02:      /* No acknowledgement */
 711                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 712                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 713                 break;
 714         case 0x03:      /* Register access ready */
 715                 omap_i2c_complete_cmd(dev, 0);
 716                 break;
 717         case 0x04:      /* Receive data ready */
 718                 if (dev->buf_len) {
 719                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 720                         *dev->buf++ = w;
 721                         dev->buf_len--;
 722                         if (dev->buf_len) {
 723                                 *dev->buf++ = w >> 8;
 724                                 dev->buf_len--;
 725                         }
 726                 } else
 727                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 728                 break;
 729         case 0x05:      /* Transmit data ready */
 730                 if (dev->buf_len) {
 731                         w = *dev->buf++;
 732                         dev->buf_len--;
 733                         if (dev->buf_len) {
 734                                 w |= *dev->buf++ << 8;
 735                                 dev->buf_len--;
 736                         }
 737                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 738                 } else
 739                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 740                 break;
 741         default:
 742                 return IRQ_NONE;
 743         }
 744
 745         return IRQ_HANDLED;
 746 }
 747 #else
 748 #define omap_i2c_rev1_isr               NULL
 749 #endif
 750
 751 static irqreturn_t
 752 omap_i2c_isr(int this_irq, void *dev_id)
 753 {
 754         struct omap_i2c_dev *dev = dev_id;
 755         u16 bits;
 756         u16 stat, w;
 757         int err, count = 0;
 758
 759         if (dev->idle)
 760                 return IRQ_NONE;
 761
 762         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 763         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 764                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 765                 if (count++ == 100) {
 766                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 767                         break;
 768                 }
 769
 770                 err = 0;
 771 complete:
 772                 /*
 773                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 774                  * acked after the data operation is complete.
 775                  * Ref: TRM SWPU114Q Figure 18-31
 776                  */
 777                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 778                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 779                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 780
 781                 if (stat & OMAP_I2C_STAT_NACK) {
 782                         err |= OMAP_I2C_STAT_NACK;
 783                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 784                                            OMAP_I2C_CON_STP);
 785                 }
 786                 if (stat & OMAP_I2C_STAT_AL) {
 787                         dev_err(dev->dev, "Arbitration lost\n");
 788                         err |= OMAP_I2C_STAT_AL;
 789                 }
 790                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 791                                         OMAP_I2C_STAT_AL)) {
 792                         omap_i2c_ack_stat(dev, stat &
 793                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 794                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 795                         omap_i2c_complete_cmd(dev, err);
 796                         return IRQ_HANDLED;
 797                 }
 798                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 799                         u8 num_bytes = 1;
 800                         if (dev->fifo_size) {
 801                                 if (stat & OMAP_I2C_STAT_RRDY)
 802                                         num_bytes = dev->fifo_size;
 803                                 else    /* read RXSTAT on RDR interrupt */
 804                                         num_bytes = (omap_i2c_read_reg(dev,
 805                                                         OMAP_I2C_BUFSTAT_REG)
 806                                                         >> 8) & 0x3F;
 807                         }
 808                         while (num_bytes) {
 809                                 num_bytes--;
 810                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 811                                 if (dev->buf_len) {
 812                                         *dev->buf++ = w;
 813                                         dev->buf_len--;
 814                                         /*
 815                                          * Data reg in 2430, omap3 and
 816                                          * omap4 is 8 bit wide
 817                                          */
 818                                         if (cpu_class_is_omap1() ||
 819                                                         cpu_is_omap2420()) {
 820                                                 if (dev->buf_len) {
 821                                                         *dev->buf++ = w >> 8;
 822                                                         dev->buf_len--;
 823                                                 }
 824                                         }
 825                                 } else {
 826                                         if (stat & OMAP_I2C_STAT_RRDY)
 827                                                 dev_err(dev->dev,
 828                                                         "RRDY IRQ while no data"
 829                                                                 " requested\n");
 830                                         if (stat & OMAP_I2C_STAT_RDR)
 831                                                 dev_err(dev->dev,
 832                                                         "RDR IRQ while no data"
 833                                                                 " requested\n");
 834                                         break;
 835                                 }
 836                         }
 837                         omap_i2c_ack_stat(dev,
 838                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 839                         continue;
 840                 }
 841                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 842                         u8 num_bytes = 1;
 843                         if (dev->fifo_size) {
 844                                 if (stat & OMAP_I2C_STAT_XRDY)
 845                                         num_bytes = dev->fifo_size;
 846                                 else    /* read TXSTAT on XDR interrupt */
 847                                         num_bytes = omap_i2c_read_reg(dev,
 848                                                         OMAP_I2C_BUFSTAT_REG)
 849                                                         & 0x3F;
 850                         }
 851                         while (num_bytes) {
 852                                 num_bytes--;
 853                                 w = 0;
 854                                 if (dev->buf_len) {
 855                                         w = *dev->buf++;
 856                                         dev->buf_len--;
 857                                         /*
 858                                          * Data reg in 2430, omap3 and
 859                                          * omap4 is 8 bit wide
 860                                          */
 861                                         if (cpu_class_is_omap1() ||
 862                                                         cpu_is_omap2420()) {
 863                                                 if (dev->buf_len) {
 864                                                         w |= *dev->buf++ << 8;
 865                                                         dev->buf_len--;
 866                                                 }
 867                                         }
 868                                 } else {
 869                                         if (stat & OMAP_I2C_STAT_XRDY)
 870                                                 dev_err(dev->dev,
 871                                                         "XRDY IRQ while no "
 872                                                         "data to send\n");
 873                                         if (stat & OMAP_I2C_STAT_XDR)
 874                                                 dev_err(dev->dev,
 875                                                         "XDR IRQ while no "
 876                                                         "data to send\n");
 877                                         break;
 878                                 }
 879
 880                                 /*
 881                                  * OMAP3430 Errata 1.153: When an XRDY/XDR
 882                                  * is hit, wait for XUDF before writing data
 883                                  * to DATA_REG. Otherwise some data bytes can
 884                                  * be lost while transferring them from the
 885                                  * memory to the I2C interface.
 886                                  */
 887
 888                                 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
 889                                                 while (!(stat & OMAP_I2C_STAT_XUDF)) {
 890                                                         if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 891                                                                 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 892                                                                 err |= OMAP_I2C_STAT_XUDF;
 893                                                                 goto complete;
 894                                                         }
 895                                                         cpu_relax();
 896                                                         stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 897                                                 }
 898                                 }
 899
 900                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 901                         }
 902                         omap_i2c_ack_stat(dev,
 903                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 904                         continue;
 905                 }
 906                 if (stat & OMAP_I2C_STAT_ROVR) {
 907                         dev_err(dev->dev, "Receive overrun\n");
 908                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 909                 }
 910                 if (stat & OMAP_I2C_STAT_XUDF) {
 911                         dev_err(dev->dev, "Transmit underflow\n");
 912                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 913                 }
 914         }
 915
 916         return count ? IRQ_HANDLED : IRQ_NONE;
 917 }
 918
 919 static const struct i2c_algorithm omap_i2c_algo = {
 920         .master_xfer    = omap_i2c_xfer,
 921         .functionality  = omap_i2c_func,
 922 };
 923
 924 static int __devinit
 925 omap_i2c_probe(struct platform_device *pdev)
 926 {
 927         struct omap_i2c_dev     *dev;
 928         struct i2c_adapter      *adap;
 929         struct resource         *mem, *irq, *ioarea;
 930         irq_handler_t isr;
 931         int r;
 932         u32 speed = 0;
 933
 934         /* NOTE: driver uses the static register mapping */
 935         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 936         if (!mem) {
 937                 dev_err(&pdev->dev, "no mem resource?\n");
 938                 return -ENODEV;
 939         }
 940         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 941         if (!irq) {
 942                 dev_err(&pdev->dev, "no irq resource?\n");
 943                 return -ENODEV;
 944         }
 945
 946         ioarea = request_mem_region(mem->start, resource_size(mem),
 947                         pdev->name);
 948         if (!ioarea) {
 949                 dev_err(&pdev->dev, "I2C region already claimed\n");
 950                 return -EBUSY;
 951         }
 952
 953         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 954         if (!dev) {
 955                 r = -ENOMEM;
 956                 goto err_release_region;
 957         }
 958
 959         if (pdev->dev.platform_data != NULL)
 960                 speed = *(u32 *)pdev->dev.platform_data;
 961         else
 962                 speed = 100;    /* Defualt speed */
 963
 964         dev->speed = speed;
 965         dev->idle = 1;
 966         dev->dev = &pdev->dev;
 967         dev->irq = irq->start;
 968         dev->base = ioremap(mem->start, resource_size(mem));
 969         if (!dev->base) {
 970                 r = -ENOMEM;
 971                 goto err_free_mem;
 972         }
 973
 974         platform_set_drvdata(pdev, dev);
 975
 976         if (cpu_is_omap7xx())
 977                 dev->reg_shift = 1;
 978         else if (cpu_is_omap44xx())
 979                 dev->reg_shift = 0;
 980         else
 981                 dev->reg_shift = 2;
 982
 983         if ((r = omap_i2c_get_clocks(dev)) != 0)
 984                 goto err_iounmap;
 985
 986         if (cpu_is_omap44xx())
 987                 dev->regs = (u8 *) omap4_reg_map;
 988         else
 989                 dev->regs = (u8 *) reg_map;
 990
 991         omap_i2c_unidle(dev);
 992
 993         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 994
 995         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
 996                 u16 s;
 997
 998                 /* Set up the fifo size - Get total size */
 999                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1000                 dev->fifo_size = 0x8 << s;
1001
1002                 /*
1003                  * Set up notification threshold as half the total available
1004                  * size. This is to ensure that we can handle the status on int
1005                  * call back latencies.
1006                  */
1007                 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1008                         dev->fifo_size = 0;
1009                         dev->b_hw = 0; /* Disable hardware fixes */
1010                 } else {
1011                         dev->fifo_size = (dev->fifo_size / 2);
1012                         dev->b_hw = 1; /* Enable hardware fixes */
1013                 }
1014         }
1015
1016         /* reset ASAP, clearing any IRQs */
1017         omap_i2c_init(dev);
1018
1019         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1020         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1021
1022         if (r) {
1023                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1024                 goto err_unuse_clocks;
1025         }
1026
1027         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1028                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1029
1030         omap_i2c_idle(dev);
1031
1032         adap = &dev->adapter;
1033         i2c_set_adapdata(adap, dev);
1034         adap->owner = THIS_MODULE;
1035         adap->class = I2C_CLASS_HWMON;
1036         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1037         adap->algo = &omap_i2c_algo;
1038         adap->dev.parent = &pdev->dev;
1039
1040         /* i2c device drivers may be active on return from add_adapter() */
1041         adap->nr = pdev->id;
1042         r = i2c_add_numbered_adapter(adap);
1043         if (r) {
1044                 dev_err(dev->dev, "failure adding adapter\n");
1045                 goto err_free_irq;
1046         }
1047
1048         return 0;
1049
1050 err_free_irq:
1051         free_irq(dev->irq, dev);
1052 err_unuse_clocks:
1053         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1054         omap_i2c_idle(dev);
1055         omap_i2c_put_clocks(dev);
1056 err_iounmap:
1057         iounmap(dev->base);
1058 err_free_mem:
1059         platform_set_drvdata(pdev, NULL);
1060         kfree(dev);
1061 err_release_region:
1062         release_mem_region(mem->start, resource_size(mem));
1063
1064         return r;
1065 }
1066
1067 static int
1068 omap_i2c_remove(struct platform_device *pdev)
1069 {
1070         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1071         struct resource         *mem;
1072
1073         platform_set_drvdata(pdev, NULL);
1074
1075         free_irq(dev->irq, dev);
1076         i2c_del_adapter(&dev->adapter);
1077         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1078         omap_i2c_put_clocks(dev);
1079         iounmap(dev->base);
1080         kfree(dev);
1081         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082         release_mem_region(mem->start, resource_size(mem));
1083         return 0;
1084 }
1085
1086 static struct platform_driver omap_i2c_driver = {
1087         .probe          = omap_i2c_probe,
1088         .remove         = omap_i2c_remove,
1089         .driver         = {
1090                 .name   = "i2c_omap",
1091                 .owner  = THIS_MODULE,
1092         },
1093 };
1094
1095 /* I2C may be needed to bring up other drivers */
1096 static int __init
1097 omap_i2c_init_driver(void)
1098 {
1099         return platform_driver_register(&omap_i2c_driver);
1100 }
1101 subsys_initcall(omap_i2c_init_driver);
1102
1103 static void __exit omap_i2c_exit_driver(void)
1104 {
1105         platform_driver_unregister(&omap_i2c_driver);
1106 }
1107 module_exit(omap_i2c_exit_driver);
1108
1109 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1110 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1111 MODULE_LICENSE("GPL");
1112 MODULE_ALIAS("platform:i2c_omap");