2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
29 #define DRV_NAME "mpc-i2c"
31 #define MPC_I2C_FDR 0x04
32 #define MPC_I2C_CR 0x08
33 #define MPC_I2C_SR 0x0c
34 #define MPC_I2C_DR 0x10
35 #define MPC_I2C_DFSRR 0x14
55 wait_queue_head_t queue;
56 struct i2c_adapter adap;
61 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
63 writeb(x, i2c->base + MPC_I2C_CR);
66 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
68 struct mpc_i2c *i2c = dev_id;
69 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
70 /* Read again to allow register to stabilise */
71 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
72 writeb(0, i2c->base + MPC_I2C_SR);
78 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
79 * the bus, because it wants to send ACK.
80 * Following sequence of enabling/disabling and sending start/stop generates
81 * the pulse, so it's all OK.
83 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
87 writeccr(i2c, CCR_MEN);
89 writeccr(i2c, CCR_MSTA | CCR_MTX);
91 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
93 writeccr(i2c, CCR_MEN);
97 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
99 unsigned long orig_jiffies = jiffies;
103 if (i2c->irq == NO_IRQ) {
104 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
106 if (time_after(jiffies, orig_jiffies + timeout)) {
107 pr_debug("I2C: timeout\n");
113 x = readb(i2c->base + MPC_I2C_SR);
114 writeb(0, i2c->base + MPC_I2C_SR);
117 result = wait_event_timeout(i2c->queue,
118 (i2c->interrupt & CSR_MIF), timeout);
120 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
121 pr_debug("I2C: wait timeout\n");
133 if (!(x & CSR_MCF)) {
134 pr_debug("I2C: unfinished\n");
139 pr_debug("I2C: MAL\n");
143 if (writing && (x & CSR_RXAK)) {
144 pr_debug("I2C: No RXAK\n");
146 writeccr(i2c, CCR_MEN);
152 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
154 /* Set clock and filters */
155 if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
156 writeb(0x31, i2c->base + MPC_I2C_FDR);
157 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
158 } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
159 writeb(0x3f, i2c->base + MPC_I2C_FDR);
161 writel(0x1031, i2c->base + MPC_I2C_FDR);
164 static void mpc_i2c_start(struct mpc_i2c *i2c)
166 /* Clear arbitration */
167 writeb(0, i2c->base + MPC_I2C_SR);
169 writeccr(i2c, CCR_MEN);
172 static void mpc_i2c_stop(struct mpc_i2c *i2c)
174 writeccr(i2c, CCR_MEN);
177 static int mpc_write(struct mpc_i2c *i2c, int target,
178 const u8 *data, int length, int restart)
181 unsigned timeout = i2c->adap.timeout;
182 u32 flags = restart ? CCR_RSTA : 0;
186 writeccr(i2c, CCR_MEN);
187 /* Start as master */
188 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
189 /* Write target byte */
190 writeb((target << 1), i2c->base + MPC_I2C_DR);
192 result = i2c_wait(i2c, timeout, 1);
196 for (i = 0; i < length; i++) {
197 /* Write data byte */
198 writeb(data[i], i2c->base + MPC_I2C_DR);
200 result = i2c_wait(i2c, timeout, 1);
208 static int mpc_read(struct mpc_i2c *i2c, int target,
209 u8 *data, int length, int restart)
211 unsigned timeout = i2c->adap.timeout;
213 u32 flags = restart ? CCR_RSTA : 0;
217 writeccr(i2c, CCR_MEN);
218 /* Switch to read - restart */
219 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
220 /* Write target address byte - this time with the read flag set */
221 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
223 result = i2c_wait(i2c, timeout, 1);
229 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
231 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
233 readb(i2c->base + MPC_I2C_DR);
236 for (i = 0; i < length; i++) {
237 result = i2c_wait(i2c, timeout, 0);
241 /* Generate txack on next to last byte */
243 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
244 /* Generate stop on last byte */
246 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
247 data[i] = readb(i2c->base + MPC_I2C_DR);
253 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
255 struct i2c_msg *pmsg;
258 unsigned long orig_jiffies = jiffies;
259 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
263 /* Allow bus up to 1s to become not busy */
264 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
265 if (signal_pending(current)) {
266 pr_debug("I2C: Interrupted\n");
270 if (time_after(jiffies, orig_jiffies + HZ)) {
271 pr_debug("I2C: timeout\n");
272 if (readb(i2c->base + MPC_I2C_SR) ==
273 (CSR_MCF | CSR_MBB | CSR_RXAK))
280 for (i = 0; ret >= 0 && i < num; i++) {
282 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
283 pmsg->flags & I2C_M_RD ? "read" : "write",
284 pmsg->len, pmsg->addr, i + 1, num);
285 if (pmsg->flags & I2C_M_RD)
287 mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
290 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
293 return (ret < 0) ? ret : num;
296 static u32 mpc_functionality(struct i2c_adapter *adap)
298 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
301 static const struct i2c_algorithm mpc_algo = {
302 .master_xfer = mpc_xfer,
303 .functionality = mpc_functionality,
306 static struct i2c_adapter mpc_ops = {
307 .owner = THIS_MODULE,
308 .name = "MPC adapter",
313 static int __devinit fsl_i2c_probe(struct of_device *op,
314 const struct of_device_id *match)
319 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
323 if (of_get_property(op->node, "dfsrr", NULL))
324 i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
326 if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
327 of_device_is_compatible(op->node, "mpc5200-i2c"))
328 i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
330 init_waitqueue_head(&i2c->queue);
332 i2c->base = of_iomap(op->node, 0);
334 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
339 i2c->irq = irq_of_parse_and_map(op->node, 0);
340 if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
341 result = request_irq(i2c->irq, mpc_i2c_isr,
342 IRQF_SHARED, "i2c-mpc", i2c);
345 "i2c-mpc - failed to attach interrupt\n");
350 mpc_i2c_setclock(i2c);
352 dev_set_drvdata(&op->dev, i2c);
355 i2c_set_adapdata(&i2c->adap, i2c);
356 i2c->adap.dev.parent = &op->dev;
358 result = i2c_add_adapter(&i2c->adap);
360 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
363 of_register_i2c_devices(&i2c->adap, op->node);
368 dev_set_drvdata(&op->dev, NULL);
369 free_irq(i2c->irq, i2c);
371 irq_dispose_mapping(i2c->irq);
378 static int __devexit fsl_i2c_remove(struct of_device *op)
380 struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
382 i2c_del_adapter(&i2c->adap);
383 dev_set_drvdata(&op->dev, NULL);
385 if (i2c->irq != NO_IRQ)
386 free_irq(i2c->irq, i2c);
388 irq_dispose_mapping(i2c->irq);
394 static const struct of_device_id mpc_i2c_of_match[] = {
395 {.compatible = "fsl-i2c",},
398 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
401 /* Structure for a device driver */
402 static struct of_platform_driver mpc_i2c_driver = {
403 .match_table = mpc_i2c_of_match,
404 .probe = fsl_i2c_probe,
405 .remove = __devexit_p(fsl_i2c_remove),
407 .owner = THIS_MODULE,
412 static int __init fsl_i2c_init(void)
416 rv = of_register_platform_driver(&mpc_i2c_driver);
418 printk(KERN_ERR DRV_NAME
419 " of_register_platform_driver failed (%i)\n", rv);
423 static void __exit fsl_i2c_exit(void)
425 of_unregister_platform_driver(&mpc_i2c_driver);
428 module_init(fsl_i2c_init);
429 module_exit(fsl_i2c_exit);
431 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
432 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
433 "MPC824x/85xx/52xx processors");
434 MODULE_LICENSE("GPL");