2 * Synopsys Designware I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/i2c.h>
32 #include <linux/clk.h>
33 #include <linux/errno.h>
34 #include <linux/sched.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
45 #define DW_IC_DATA_CMD 0x10
46 #define DW_IC_SS_SCL_HCNT 0x14
47 #define DW_IC_SS_SCL_LCNT 0x18
48 #define DW_IC_FS_SCL_HCNT 0x1c
49 #define DW_IC_FS_SCL_LCNT 0x20
50 #define DW_IC_INTR_STAT 0x2c
51 #define DW_IC_INTR_MASK 0x30
52 #define DW_IC_RAW_INTR_STAT 0x34
53 #define DW_IC_CLR_INTR 0x40
54 #define DW_IC_CLR_RX_UNDER 0x44
55 #define DW_IC_CLR_RX_OVER 0x48
56 #define DW_IC_CLR_TX_OVER 0x4c
57 #define DW_IC_CLR_RD_REQ 0x50
58 #define DW_IC_CLR_TX_ABRT 0x54
59 #define DW_IC_CLR_RX_DONE 0x58
60 #define DW_IC_CLR_ACTIVITY 0x5c
61 #define DW_IC_CLR_STOP_DET 0x60
62 #define DW_IC_CLR_START_DET 0x64
63 #define DW_IC_CLR_GEN_CALL 0x68
64 #define DW_IC_ENABLE 0x6c
65 #define DW_IC_STATUS 0x70
66 #define DW_IC_TXFLR 0x74
67 #define DW_IC_RXFLR 0x78
68 #define DW_IC_COMP_PARAM_1 0xf4
69 #define DW_IC_TX_ABRT_SOURCE 0x80
71 #define DW_IC_CON_MASTER 0x1
72 #define DW_IC_CON_SPEED_STD 0x2
73 #define DW_IC_CON_SPEED_FAST 0x4
74 #define DW_IC_CON_10BITADDR_MASTER 0x10
75 #define DW_IC_CON_RESTART_EN 0x20
76 #define DW_IC_CON_SLAVE_DISABLE 0x40
78 #define DW_IC_INTR_RX_UNDER 0x001
79 #define DW_IC_INTR_RX_OVER 0x002
80 #define DW_IC_INTR_RX_FULL 0x004
81 #define DW_IC_INTR_TX_OVER 0x008
82 #define DW_IC_INTR_TX_EMPTY 0x010
83 #define DW_IC_INTR_RD_REQ 0x020
84 #define DW_IC_INTR_TX_ABRT 0x040
85 #define DW_IC_INTR_RX_DONE 0x080
86 #define DW_IC_INTR_ACTIVITY 0x100
87 #define DW_IC_INTR_STOP_DET 0x200
88 #define DW_IC_INTR_START_DET 0x400
89 #define DW_IC_INTR_GEN_CALL 0x800
91 #define DW_IC_STATUS_ACTIVITY 0x1
93 #define DW_IC_ERR_TX_ABRT 0x1
98 #define STATUS_IDLE 0x0
99 #define STATUS_WRITE_IN_PROGRESS 0x1
100 #define STATUS_READ_IN_PROGRESS 0x2
102 #define TIMEOUT 20 /* ms */
105 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
107 * only expected abort codes are listed here
108 * refer to the datasheet for the full list
110 #define ABRT_7B_ADDR_NOACK 0
111 #define ABRT_10ADDR1_NOACK 1
112 #define ABRT_10ADDR2_NOACK 2
113 #define ABRT_TXDATA_NOACK 3
114 #define ABRT_GCALL_NOACK 4
115 #define ABRT_GCALL_READ 5
116 #define ABRT_SBYTE_ACKDET 7
117 #define ABRT_SBYTE_NORSTRT 9
118 #define ABRT_10B_RD_NORSTRT 10
119 #define ARB_MASTER_DIS 11
122 static char *abort_sources[] = {
123 [ABRT_7B_ADDR_NOACK] =
124 "slave address not acknowledged (7bit mode)",
125 [ABRT_10ADDR1_NOACK] =
126 "first address byte not acknowledged (10bit mode)",
127 [ABRT_10ADDR2_NOACK] =
128 "second address byte not acknowledged (10bit mode)",
129 [ABRT_TXDATA_NOACK] =
130 "data not acknowledged",
132 "no acknowledgement for a general call",
134 "read after general call",
135 [ABRT_SBYTE_ACKDET] =
136 "start byte acknowledged",
137 [ABRT_SBYTE_NORSTRT] =
138 "trying to send start byte when restart is disabled",
139 [ABRT_10B_RD_NORSTRT] =
140 "trying to read when restart is disabled (10bit mode)",
142 "trying to use disabled adapter",
148 * struct dw_i2c_dev - private i2c-designware data
149 * @dev: driver model device node
150 * @base: IO registers pointer
151 * @cmd_complete: tx completion indicator
152 * @pump_msg: continue in progress transfers
153 * @lock: protect this struct and IO registers
154 * @clk: input reference clock
155 * @cmd_err: run time hadware error code
156 * @msgs: points to an array of messages currently being transfered
157 * @msgs_num: the number of elements in msgs
158 * @msg_write_idx: the element index of the current tx message in the msgs
160 * @tx_buf_len: the length of the current tx buffer
161 * @tx_buf: the current tx buffer
162 * @msg_read_idx: the element index of the current rx message in the msgs
164 * @rx_buf_len: the length of the current rx buffer
165 * @rx_buf: the current rx buffer
166 * @msg_err: error status of the current transfer
167 * @status: i2c master status, one of STATUS_*
168 * @abort_source: copy of the TX_ABRT_SOURCE register
169 * @irq: interrupt number for the i2c master
170 * @adapter: i2c subsystem adapter node
171 * @tx_fifo_depth: depth of the hardware tx fifo
172 * @rx_fifo_depth: depth of the hardware rx fifo
177 struct completion cmd_complete;
178 struct tasklet_struct pump_msg;
182 struct i2c_msg *msgs;
194 struct i2c_adapter adapter;
195 unsigned int tx_fifo_depth;
196 unsigned int rx_fifo_depth;
200 * i2c_dw_init() - initialize the designware i2c master hardware
201 * @dev: device private data
203 * This functions configures and enables the I2C master.
204 * This function is called during I2C init function, and in case of timeout at
207 static void i2c_dw_init(struct dw_i2c_dev *dev)
209 u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
212 /* Disable the adapter */
213 writel(0, dev->base + DW_IC_ENABLE);
215 /* set standard and fast speed deviders for high/low periods */
216 writel((input_clock_khz * 40 / 10000)+1, /* std speed high, 4us */
217 dev->base + DW_IC_SS_SCL_HCNT);
218 writel((input_clock_khz * 47 / 10000)+1, /* std speed low, 4.7us */
219 dev->base + DW_IC_SS_SCL_LCNT);
220 writel((input_clock_khz * 6 / 10000)+1, /* fast speed high, 0.6us */
221 dev->base + DW_IC_FS_SCL_HCNT);
222 writel((input_clock_khz * 13 / 10000)+1, /* fast speed low, 1.3us */
223 dev->base + DW_IC_FS_SCL_LCNT);
225 /* configure the i2c master */
226 ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
227 DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
228 writel(ic_con, dev->base + DW_IC_CON);
232 * Waiting for bus not busy
234 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
236 int timeout = TIMEOUT;
238 while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
240 dev_warn(dev->dev, "timeout waiting for bus ready\n");
251 * Initiate low level master read/write transaction.
252 * This function is called from i2c_dw_xfer when starting a transfer.
253 * This function is also called from dw_i2c_pump_msg to continue a transfer
254 * that is longer than the size of the TX FIFO.
257 i2c_dw_xfer_msg(struct i2c_adapter *adap)
259 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
260 struct i2c_msg *msgs = dev->msgs;
261 int num = dev->msgs_num;
262 u32 ic_con, intr_mask;
263 int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
264 int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
265 u32 addr = msgs[dev->msg_write_idx].addr;
266 u32 buf_len = dev->tx_buf_len;
268 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
269 /* Disable the adapter */
270 writel(0, dev->base + DW_IC_ENABLE);
272 /* set the slave (target) address */
273 writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
275 /* if the slave address is ten bit address, enable 10BITADDR */
276 ic_con = readl(dev->base + DW_IC_CON);
277 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
278 ic_con |= DW_IC_CON_10BITADDR_MASTER;
280 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
281 writel(ic_con, dev->base + DW_IC_CON);
283 /* Enable the adapter */
284 writel(1, dev->base + DW_IC_ENABLE);
287 for (; dev->msg_write_idx < num; dev->msg_write_idx++) {
288 /* if target address has changed, we need to
289 * reprogram the target address in the i2c
290 * adapter when we are done with this transfer
292 if (msgs[dev->msg_write_idx].addr != addr)
295 if (msgs[dev->msg_write_idx].len == 0) {
297 "%s: invalid message length\n", __func__);
298 dev->msg_err = -EINVAL;
302 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
304 dev->tx_buf = msgs[dev->msg_write_idx].buf;
305 buf_len = msgs[dev->msg_write_idx].len;
308 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
309 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
310 writel(0x100, dev->base + DW_IC_DATA_CMD);
313 writel(*(dev->tx_buf++),
314 dev->base + DW_IC_DATA_CMD);
315 tx_limit--; buf_len--;
319 intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT;
320 if (buf_len > 0) { /* more bytes to be written */
321 intr_mask |= DW_IC_INTR_TX_EMPTY;
322 dev->status |= STATUS_WRITE_IN_PROGRESS;
324 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
325 writel(intr_mask, dev->base + DW_IC_INTR_MASK);
327 dev->tx_buf_len = buf_len;
331 i2c_dw_read(struct i2c_adapter *adap)
333 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
334 struct i2c_msg *msgs = dev->msgs;
335 int num = dev->msgs_num;
336 u32 addr = msgs[dev->msg_read_idx].addr;
337 int rx_valid = readl(dev->base + DW_IC_RXFLR);
339 for (; dev->msg_read_idx < num; dev->msg_read_idx++) {
343 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
346 /* different i2c client, reprogram the i2c adapter */
347 if (msgs[dev->msg_read_idx].addr != addr)
350 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
351 len = msgs[dev->msg_read_idx].len;
352 buf = msgs[dev->msg_read_idx].buf;
354 len = dev->rx_buf_len;
358 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
359 *buf++ = readl(dev->base + DW_IC_DATA_CMD);
362 dev->status |= STATUS_READ_IN_PROGRESS;
363 dev->rx_buf_len = len;
367 dev->status &= ~STATUS_READ_IN_PROGRESS;
372 * Prepare controller for a transaction and call i2c_dw_xfer_msg
375 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
377 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
380 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
382 mutex_lock(&dev->lock);
384 INIT_COMPLETION(dev->cmd_complete);
388 dev->msg_write_idx = 0;
389 dev->msg_read_idx = 0;
391 dev->status = STATUS_IDLE;
393 ret = i2c_dw_wait_bus_not_busy(dev);
397 /* start the transfers */
398 i2c_dw_xfer_msg(adap);
400 /* wait for tx to complete */
401 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
403 dev_err(dev->dev, "controller timed out\n");
416 if (likely(!dev->cmd_err)) {
417 /* read rx fifo, and disable the adapter */
420 } while (dev->status & STATUS_READ_IN_PROGRESS);
421 writel(0, dev->base + DW_IC_ENABLE);
426 /* We have an error */
427 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
428 unsigned long abort_source = dev->abort_source;
431 for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) {
432 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
438 mutex_unlock(&dev->lock);
443 static u32 i2c_dw_func(struct i2c_adapter *adap)
445 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
448 static void dw_i2c_pump_msg(unsigned long data)
450 struct dw_i2c_dev *dev = (struct dw_i2c_dev *) data;
453 i2c_dw_read(&dev->adapter);
454 i2c_dw_xfer_msg(&dev->adapter);
456 intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT;
457 if (dev->status & STATUS_WRITE_IN_PROGRESS)
458 intr_mask |= DW_IC_INTR_TX_EMPTY;
459 writel(intr_mask, dev->base + DW_IC_INTR_MASK);
462 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
467 * The IC_INTR_STAT register just indicates "enabled" interrupts.
468 * Ths unmasked raw version of interrupt status bits are available
469 * in the IC_RAW_INTR_STAT register.
472 * stat = readl(IC_INTR_STAT);
474 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
476 * The raw version might be useful for debugging purposes.
478 stat = readl(dev->base + DW_IC_INTR_STAT);
481 * Do not use the IC_CLR_INTR register to clear interrupts, or
482 * you'll miss some interrupts, triggered during the period from
483 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
485 * Instead, use the separately-prepared IC_CLR_* registers.
487 if (stat & DW_IC_INTR_RX_UNDER)
488 readl(dev->base + DW_IC_CLR_RX_UNDER);
489 if (stat & DW_IC_INTR_RX_OVER)
490 readl(dev->base + DW_IC_CLR_RX_OVER);
491 if (stat & DW_IC_INTR_TX_OVER)
492 readl(dev->base + DW_IC_CLR_TX_OVER);
493 if (stat & DW_IC_INTR_RD_REQ)
494 readl(dev->base + DW_IC_CLR_RD_REQ);
495 if (stat & DW_IC_INTR_TX_ABRT) {
497 * The IC_TX_ABRT_SOURCE register is cleared whenever
498 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
500 dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE);
501 readl(dev->base + DW_IC_CLR_TX_ABRT);
503 if (stat & DW_IC_INTR_RX_DONE)
504 readl(dev->base + DW_IC_CLR_RX_DONE);
505 if (stat & DW_IC_INTR_ACTIVITY)
506 readl(dev->base + DW_IC_CLR_ACTIVITY);
507 if (stat & DW_IC_INTR_STOP_DET)
508 readl(dev->base + DW_IC_CLR_STOP_DET);
509 if (stat & DW_IC_INTR_START_DET)
510 readl(dev->base + DW_IC_CLR_START_DET);
511 if (stat & DW_IC_INTR_GEN_CALL)
512 readl(dev->base + DW_IC_CLR_GEN_CALL);
518 * Interrupt service routine. This gets called whenever an I2C interrupt
521 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
523 struct dw_i2c_dev *dev = dev_id;
526 stat = i2c_dw_read_clear_intrbits(dev);
527 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
529 if (stat & DW_IC_INTR_TX_ABRT) {
530 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
531 dev->status = STATUS_IDLE;
532 } else if (stat & DW_IC_INTR_TX_EMPTY)
533 tasklet_schedule(&dev->pump_msg);
535 writel(0, dev->base + DW_IC_INTR_MASK); /* disable interrupts */
536 if (stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET))
537 complete(&dev->cmd_complete);
542 static struct i2c_algorithm i2c_dw_algo = {
543 .master_xfer = i2c_dw_xfer,
544 .functionality = i2c_dw_func,
547 static int __devinit dw_i2c_probe(struct platform_device *pdev)
549 struct dw_i2c_dev *dev;
550 struct i2c_adapter *adap;
551 struct resource *mem, *ioarea;
554 /* NOTE: driver uses the static register mapping */
555 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557 dev_err(&pdev->dev, "no mem resource?\n");
561 irq = platform_get_irq(pdev, 0);
563 dev_err(&pdev->dev, "no irq resource?\n");
564 return irq; /* -ENXIO */
567 ioarea = request_mem_region(mem->start, resource_size(mem),
570 dev_err(&pdev->dev, "I2C region already claimed\n");
574 dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
577 goto err_release_region;
580 init_completion(&dev->cmd_complete);
581 tasklet_init(&dev->pump_msg, dw_i2c_pump_msg, (unsigned long) dev);
582 mutex_init(&dev->lock);
583 dev->dev = get_device(&pdev->dev);
585 platform_set_drvdata(pdev, dev);
587 dev->clk = clk_get(&pdev->dev, NULL);
588 if (IS_ERR(dev->clk)) {
592 clk_enable(dev->clk);
594 dev->base = ioremap(mem->start, resource_size(mem));
595 if (dev->base == NULL) {
596 dev_err(&pdev->dev, "failure mapping io resources\n");
598 goto err_unuse_clocks;
601 u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1);
603 dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
604 dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
608 writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */
609 r = request_irq(dev->irq, i2c_dw_isr, 0, pdev->name, dev);
611 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
615 adap = &dev->adapter;
616 i2c_set_adapdata(adap, dev);
617 adap->owner = THIS_MODULE;
618 adap->class = I2C_CLASS_HWMON;
619 strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
621 adap->algo = &i2c_dw_algo;
622 adap->dev.parent = &pdev->dev;
625 r = i2c_add_numbered_adapter(adap);
627 dev_err(&pdev->dev, "failure adding adapter\n");
634 free_irq(dev->irq, dev);
638 clk_disable(dev->clk);
642 platform_set_drvdata(pdev, NULL);
643 put_device(&pdev->dev);
646 release_mem_region(mem->start, resource_size(mem));
651 static int __devexit dw_i2c_remove(struct platform_device *pdev)
653 struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
654 struct resource *mem;
656 platform_set_drvdata(pdev, NULL);
657 i2c_del_adapter(&dev->adapter);
658 put_device(&pdev->dev);
660 clk_disable(dev->clk);
664 writel(0, dev->base + DW_IC_ENABLE);
665 free_irq(dev->irq, dev);
668 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
669 release_mem_region(mem->start, resource_size(mem));
673 /* work with hotplug and coldplug */
674 MODULE_ALIAS("platform:i2c_designware");
676 static struct platform_driver dw_i2c_driver = {
677 .remove = __devexit_p(dw_i2c_remove),
679 .name = "i2c_designware",
680 .owner = THIS_MODULE,
684 static int __init dw_i2c_init_driver(void)
686 return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
688 module_init(dw_i2c_init_driver);
690 static void __exit dw_i2c_exit_driver(void)
692 platform_driver_unregister(&dw_i2c_driver);
694 module_exit(dw_i2c_exit_driver);
696 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
697 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
698 MODULE_LICENSE("GPL");