2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
43 #include "rs600_reg_safe.h"
45 void rs600_gpu_init(struct radeon_device *rdev);
46 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
51 void rs600_gart_tlb_flush(struct radeon_device *rdev)
55 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
56 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
57 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
59 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
60 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
61 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
63 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
64 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
65 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
66 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
69 int rs600_gart_init(struct radeon_device *rdev)
73 if (rdev->gart.table.vram.robj) {
74 WARN(1, "RS600 GART already initialized.\n");
77 /* Initialize common gart structure */
78 r = radeon_gart_init(rdev);
82 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
83 return radeon_gart_table_vram_alloc(rdev);
86 int rs600_gart_enable(struct radeon_device *rdev)
91 if (rdev->gart.table.vram.robj == NULL) {
92 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
95 r = radeon_gart_table_vram_pin(rdev);
98 /* Enable bus master */
99 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
100 WREG32(R_00004C_BUS_CNTL, tmp);
101 /* FIXME: setup default page */
102 WREG32_MC(R_000100_MC_PT0_CNTL,
103 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
104 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
106 for (i = 0; i < 19; i++) {
107 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
108 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
109 S_00016C_SYSTEM_ACCESS_MODE_MASK(
110 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
111 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
112 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
113 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
114 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
115 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
117 /* enable first context */
118 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
119 S_000102_ENABLE_PAGE_TABLE(1) |
120 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
122 /* disable all other contexts */
123 for (i = 1; i < 8; i++)
124 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
126 /* setup the page table */
127 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
128 rdev->gart.table_addr);
129 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
130 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
131 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
133 /* System context maps to VRAM space */
134 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
135 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
137 /* enable page tables */
138 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
139 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
140 tmp = RREG32_MC(R_000009_MC_CNTL1);
141 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
142 rs600_gart_tlb_flush(rdev);
143 rdev->gart.ready = true;
147 void rs600_gart_disable(struct radeon_device *rdev)
152 /* FIXME: disable out of gart access */
153 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
154 tmp = RREG32_MC(R_000009_MC_CNTL1);
155 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
156 if (rdev->gart.table.vram.robj) {
157 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159 radeon_bo_kunmap(rdev->gart.table.vram.robj);
160 radeon_bo_unpin(rdev->gart.table.vram.robj);
161 radeon_bo_unreserve(rdev->gart.table.vram.robj);
166 void rs600_gart_fini(struct radeon_device *rdev)
168 rs600_gart_disable(rdev);
169 radeon_gart_table_vram_free(rdev);
170 radeon_gart_fini(rdev);
173 #define R600_PTE_VALID (1 << 0)
174 #define R600_PTE_SYSTEM (1 << 1)
175 #define R600_PTE_SNOOPED (1 << 2)
176 #define R600_PTE_READABLE (1 << 5)
177 #define R600_PTE_WRITEABLE (1 << 6)
179 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
181 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
183 if (i < 0 || i > rdev->gart.num_gpu_pages) {
186 addr = addr & 0xFFFFFFFFFFFFF000ULL;
187 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
188 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
189 writeq(addr, ((void __iomem *)ptr) + (i * 8));
193 int rs600_irq_set(struct radeon_device *rdev)
196 uint32_t mode_int = 0;
198 if (rdev->irq.sw_int) {
199 tmp |= S_000040_SW_INT_EN(1);
201 if (rdev->irq.crtc_vblank_int[0]) {
202 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
204 if (rdev->irq.crtc_vblank_int[1]) {
205 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
207 WREG32(R_000040_GEN_INT_CNTL, tmp);
208 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
212 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
214 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
215 uint32_t irq_mask = ~C_000044_SW_INT;
217 if (G_000044_DISPLAY_INT_STAT(irqs)) {
218 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
219 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
220 WREG32(R_006534_D1MODE_VBLANK_STATUS,
221 S_006534_D1MODE_VBLANK_ACK(1));
223 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
224 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
225 S_006D34_D2MODE_VBLANK_ACK(1));
232 WREG32(R_000044_GEN_INT_STATUS, irqs);
234 return irqs & irq_mask;
237 void rs600_irq_disable(struct radeon_device *rdev)
241 WREG32(R_000040_GEN_INT_CNTL, 0);
242 WREG32(R_006540_DxMODE_INT_MASK, 0);
243 /* Wait and acknowledge irq */
245 rs600_irq_ack(rdev, &tmp);
248 int rs600_irq_process(struct radeon_device *rdev)
250 uint32_t status, msi_rearm;
251 uint32_t r500_disp_int;
253 status = rs600_irq_ack(rdev, &r500_disp_int);
254 if (!status && !r500_disp_int) {
257 while (status || r500_disp_int) {
259 if (G_000040_SW_INT_EN(status))
260 radeon_fence_process(rdev);
261 /* Vertical blank interrupts */
262 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
263 drm_handle_vblank(rdev->ddev, 0);
264 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
265 drm_handle_vblank(rdev->ddev, 1);
266 status = rs600_irq_ack(rdev, &r500_disp_int);
268 if (rdev->msi_enabled) {
269 switch (rdev->family) {
273 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
274 WREG32(RADEON_BUS_CNTL, msi_rearm);
275 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
278 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
279 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
280 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
287 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
290 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
292 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
295 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
299 for (i = 0; i < rdev->usec_timeout; i++) {
300 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
307 void rs600_gpu_init(struct radeon_device *rdev)
309 r100_hdp_reset(rdev);
310 r420_pipes_init(rdev);
311 /* Wait for mc idle */
312 if (rs600_mc_wait_for_idle(rdev))
313 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
316 void rs600_vram_info(struct radeon_device *rdev)
318 rdev->mc.vram_is_ddr = true;
319 rdev->mc.vram_width = 128;
321 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
322 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
324 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
325 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
327 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
328 rdev->mc.mc_vram_size = rdev->mc.aper_size;
330 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
331 rdev->mc.real_vram_size = rdev->mc.aper_size;
334 void rs600_bandwidth_update(struct radeon_device *rdev)
336 /* FIXME: implement, should this be like rs690 ? */
339 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
341 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
342 S_000070_MC_IND_CITF_ARB0(1));
343 return RREG32(R_000074_MC_IND_DATA);
346 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
348 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
349 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
350 WREG32(R_000074_MC_IND_DATA, v);
353 void rs600_debugfs(struct radeon_device *rdev)
355 if (r100_debugfs_rbbm_init(rdev))
356 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
359 void rs600_set_safe_registers(struct radeon_device *rdev)
361 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
362 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
365 static void rs600_mc_program(struct radeon_device *rdev)
367 struct rv515_mc_save save;
369 /* Stops all mc clients */
370 rv515_mc_stop(rdev, &save);
372 /* Wait for mc idle */
373 if (rs600_mc_wait_for_idle(rdev))
374 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
376 /* FIXME: What does AGP means for such chipset ? */
377 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
378 WREG32_MC(R_000006_AGP_BASE, 0);
379 WREG32_MC(R_000007_AGP_BASE_2, 0);
381 WREG32_MC(R_000004_MC_FB_LOCATION,
382 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
383 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
384 WREG32(R_000134_HDP_FB_LOCATION,
385 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
387 rv515_mc_resume(rdev, &save);
390 static int rs600_startup(struct radeon_device *rdev)
394 rs600_mc_program(rdev);
396 rv515_clock_startup(rdev);
397 /* Initialize GPU configuration (# pipes, ...) */
398 rs600_gpu_init(rdev);
399 /* Initialize GART (initialize after TTM so we can allocate
400 * memory through TTM but finalize after TTM) */
401 r = rs600_gart_enable(rdev);
407 r = r100_cp_init(rdev, 1024 * 1024);
409 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
412 r = r100_wb_init(rdev);
414 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
415 r = r100_ib_init(rdev);
417 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
423 int rs600_resume(struct radeon_device *rdev)
425 /* Make sur GART are not working */
426 rs600_gart_disable(rdev);
427 /* Resume clock before doing reset */
428 rv515_clock_startup(rdev);
429 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
430 if (radeon_gpu_reset(rdev)) {
431 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
432 RREG32(R_000E40_RBBM_STATUS),
433 RREG32(R_0007C0_CP_STAT));
436 atom_asic_init(rdev->mode_info.atom_context);
437 /* Resume clock after posting */
438 rv515_clock_startup(rdev);
439 return rs600_startup(rdev);
442 int rs600_suspend(struct radeon_device *rdev)
444 r100_cp_disable(rdev);
445 r100_wb_disable(rdev);
446 rs600_irq_disable(rdev);
447 rs600_gart_disable(rdev);
451 void rs600_fini(struct radeon_device *rdev)
457 radeon_gem_fini(rdev);
458 rs600_gart_fini(rdev);
459 radeon_irq_kms_fini(rdev);
460 radeon_fence_driver_fini(rdev);
461 radeon_bo_fini(rdev);
462 radeon_atombios_fini(rdev);
467 int rs600_init(struct radeon_device *rdev)
472 rv515_vga_render_disable(rdev);
473 /* Initialize scratch registers */
474 radeon_scratch_init(rdev);
475 /* Initialize surface registers */
476 radeon_surface_init(rdev);
478 if (!radeon_get_bios(rdev)) {
479 if (ASIC_IS_AVIVO(rdev))
482 if (rdev->is_atom_bios) {
483 r = radeon_atombios_init(rdev);
487 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
490 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
491 if (radeon_gpu_reset(rdev)) {
493 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
494 RREG32(R_000E40_RBBM_STATUS),
495 RREG32(R_0007C0_CP_STAT));
497 /* check if cards are posted or not */
498 if (radeon_boot_test_post_card(rdev) == false)
501 /* Initialize clocks */
502 radeon_get_clock_info(rdev->ddev);
503 /* Initialize power management */
504 radeon_pm_init(rdev);
505 /* Get vram informations */
506 rs600_vram_info(rdev);
507 /* Initialize memory controller (also test AGP) */
508 r = r420_mc_init(rdev);
513 r = radeon_fence_driver_init(rdev);
516 r = radeon_irq_kms_init(rdev);
520 r = radeon_bo_init(rdev);
523 r = rs600_gart_init(rdev);
526 rs600_set_safe_registers(rdev);
527 rdev->accel_working = true;
528 r = rs600_startup(rdev);
530 /* Somethings want wront with the accel init stop accel */
531 dev_err(rdev->dev, "Disabling GPU acceleration\n");
536 rs600_gart_fini(rdev);
537 radeon_irq_kms_fini(rdev);
538 rdev->accel_working = false;