SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include "drmP.h"
  39 #include "radeon.h"
  40 #include "radeon_asic.h"
  41 #include "atom.h"
  42 #include "rs600d.h"
  43
  44 #include "rs600_reg_safe.h"
  45
  46 void rs600_gpu_init(struct radeon_device *rdev);
  47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  48
  49 void rs600_pm_misc(struct radeon_device *rdev)
  50 {
  51 #if 0
  52         int requested_index = rdev->pm.requested_power_state_index;
  53         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
  54         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
  55         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
  56         u32 hdp_dyn_cntl, mc_host_dyn_cntl;
  57
  58         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
  59                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
  60                         tmp = RREG32(voltage->gpio.reg);
  61                         if (voltage->active_high)
  62                                 tmp |= voltage->gpio.mask;
  63                         else
  64                                 tmp &= ~(voltage->gpio.mask);
  65                         WREG32(voltage->gpio.reg, tmp);
  66                         if (voltage->delay)
  67                                 udelay(voltage->delay);
  68                 } else {
  69                         tmp = RREG32(voltage->gpio.reg);
  70                         if (voltage->active_high)
  71                                 tmp &= ~voltage->gpio.mask;
  72                         else
  73                                 tmp |= voltage->gpio.mask;
  74                         WREG32(voltage->gpio.reg, tmp);
  75                         if (voltage->delay)
  76                                 udelay(voltage->delay);
  77                 }
  78         }
  79
  80         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
  81         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
  82         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
  83         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
  84                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
  85                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
  86                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
  87                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
  88                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
  89                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
  90                 }
  91         } else {
  92                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
  93                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
  94         }
  95         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
  96
  97         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
  98         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
  99                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 100                 if (voltage->delay) {
 101                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 102                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 103                 } else
 104                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 105         } else
 106                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 107         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 108
 109         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 110         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 111                 hdp_dyn_cntl &= ~HDP_FORCEON;
 112         else
 113                 hdp_dyn_cntl |= HDP_FORCEON;
 114         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 115
 116         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 117         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 118                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 119         else
 120                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 121         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 122
 123         /* set pcie lanes */
 124         if ((rdev->flags & RADEON_IS_PCIE) &&
 125             !(rdev->flags & RADEON_IS_IGP) &&
 126             rdev->asic->set_pcie_lanes &&
 127             (ps->pcie_lanes !=
 128              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 129                 radeon_set_pcie_lanes(rdev,
 130                                       ps->pcie_lanes);
 131                 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
 132         }
 133 #endif
 134 }
 135
 136 void rs600_pm_prepare(struct radeon_device *rdev)
 137 {
 138         struct drm_device *ddev = rdev->ddev;
 139         struct drm_crtc *crtc;
 140         struct radeon_crtc *radeon_crtc;
 141         u32 tmp;
 142
 143         /* disable any active CRTCs */
 144         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 145                 radeon_crtc = to_radeon_crtc(crtc);
 146                 if (radeon_crtc->enabled) {
 147                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 148                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 149                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 150                 }
 151         }
 152 }
 153
 154 void rs600_pm_finish(struct radeon_device *rdev)
 155 {
 156         struct drm_device *ddev = rdev->ddev;
 157         struct drm_crtc *crtc;
 158         struct radeon_crtc *radeon_crtc;
 159         u32 tmp;
 160
 161         /* enable any active CRTCs */
 162         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 163                 radeon_crtc = to_radeon_crtc(crtc);
 164                 if (radeon_crtc->enabled) {
 165                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 166                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 167                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 168                 }
 169         }
 170 }
 171
 172 /* hpd for digital panel detect/disconnect */
 173 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 174 {
 175         u32 tmp;
 176         bool connected = false;
 177
 178         switch (hpd) {
 179         case RADEON_HPD_1:
 180                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 181                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 182                         connected = true;
 183                 break;
 184         case RADEON_HPD_2:
 185                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 186                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 187                         connected = true;
 188                 break;
 189         default:
 190                 break;
 191         }
 192         return connected;
 193 }
 194
 195 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 196                             enum radeon_hpd_id hpd)
 197 {
 198         u32 tmp;
 199         bool connected = rs600_hpd_sense(rdev, hpd);
 200
 201         switch (hpd) {
 202         case RADEON_HPD_1:
 203                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 204                 if (connected)
 205                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 206                 else
 207                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 208                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 209                 break;
 210         case RADEON_HPD_2:
 211                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 212                 if (connected)
 213                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 214                 else
 215                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 216                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 217                 break;
 218         default:
 219                 break;
 220         }
 221 }
 222
 223 void rs600_hpd_init(struct radeon_device *rdev)
 224 {
 225         struct drm_device *dev = rdev->ddev;
 226         struct drm_connector *connector;
 227
 228         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 229                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 230                 switch (radeon_connector->hpd.hpd) {
 231                 case RADEON_HPD_1:
 232                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 233                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 234                         rdev->irq.hpd[0] = true;
 235                         break;
 236                 case RADEON_HPD_2:
 237                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 238                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 239                         rdev->irq.hpd[1] = true;
 240                         break;
 241                 default:
 242                         break;
 243                 }
 244         }
 245         if (rdev->irq.installed)
 246                 rs600_irq_set(rdev);
 247 }
 248
 249 void rs600_hpd_fini(struct radeon_device *rdev)
 250 {
 251         struct drm_device *dev = rdev->ddev;
 252         struct drm_connector *connector;
 253
 254         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 255                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 256                 switch (radeon_connector->hpd.hpd) {
 257                 case RADEON_HPD_1:
 258                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 259                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 260                         rdev->irq.hpd[0] = false;
 261                         break;
 262                 case RADEON_HPD_2:
 263                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 264                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 265                         rdev->irq.hpd[1] = false;
 266                         break;
 267                 default:
 268                         break;
 269                 }
 270         }
 271 }
 272
 273 void rs600_bm_disable(struct radeon_device *rdev)
 274 {
 275         u32 tmp;
 276
 277         /* disable bus mastering */
 278         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
 279         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
 280         mdelay(1);
 281 }
 282
 283 int rs600_asic_reset(struct radeon_device *rdev)
 284 {
 285         u32 status, tmp;
 286
 287         struct rv515_mc_save save;
 288
 289         /* Stops all mc clients */
 290         rv515_mc_stop(rdev, &save);
 291         status = RREG32(R_000E40_RBBM_STATUS);
 292         if (!G_000E40_GUI_ACTIVE(status)) {
 293                 return 0;
 294         }
 295         status = RREG32(R_000E40_RBBM_STATUS);
 296         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 297         /* stop CP */
 298         WREG32(RADEON_CP_CSQ_CNTL, 0);
 299         tmp = RREG32(RADEON_CP_RB_CNTL);
 300         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 301         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 302         WREG32(RADEON_CP_RB_WPTR, 0);
 303         WREG32(RADEON_CP_RB_CNTL, tmp);
 304         pci_save_state(rdev->pdev);
 305         /* disable bus mastering */
 306         rs600_bm_disable(rdev);
 307         /* reset GA+VAP */
 308         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 309                                         S_0000F0_SOFT_RESET_GA(1));
 310         RREG32(R_0000F0_RBBM_SOFT_RESET);
 311         mdelay(500);
 312         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 313         mdelay(1);
 314         status = RREG32(R_000E40_RBBM_STATUS);
 315         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 316         /* reset CP */
 317         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 318         RREG32(R_0000F0_RBBM_SOFT_RESET);
 319         mdelay(500);
 320         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 321         mdelay(1);
 322         status = RREG32(R_000E40_RBBM_STATUS);
 323         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 324         /* reset MC */
 325         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 326         RREG32(R_0000F0_RBBM_SOFT_RESET);
 327         mdelay(500);
 328         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 329         mdelay(1);
 330         status = RREG32(R_000E40_RBBM_STATUS);
 331         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 332         /* restore PCI & busmastering */
 333         pci_restore_state(rdev->pdev);
 334         /* Check if GPU is idle */
 335         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 336                 dev_err(rdev->dev, "failed to reset GPU\n");
 337                 rdev->gpu_lockup = true;
 338                 return -1;
 339         }
 340         rv515_mc_resume(rdev, &save);
 341         dev_info(rdev->dev, "GPU reset succeed\n");
 342         return 0;
 343 }
 344
 345 /*
 346  * GART.
 347  */
 348 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 349 {
 350         uint32_t tmp;
 351
 352         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 353         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 354         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 355
 356         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 357         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 358         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 359
 360         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 361         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 362         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 363         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 364 }
 365
 366 int rs600_gart_init(struct radeon_device *rdev)
 367 {
 368         int r;
 369
 370         if (rdev->gart.table.vram.robj) {
 371                 WARN(1, "RS600 GART already initialized.\n");
 372                 return 0;
 373         }
 374         /* Initialize common gart structure */
 375         r = radeon_gart_init(rdev);
 376         if (r) {
 377                 return r;
 378         }
 379         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 380         return radeon_gart_table_vram_alloc(rdev);
 381 }
 382
 383 int rs600_gart_enable(struct radeon_device *rdev)
 384 {
 385         u32 tmp;
 386         int r, i;
 387
 388         if (rdev->gart.table.vram.robj == NULL) {
 389                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 390                 return -EINVAL;
 391         }
 392         r = radeon_gart_table_vram_pin(rdev);
 393         if (r)
 394                 return r;
 395         radeon_gart_restore(rdev);
 396         /* Enable bus master */
 397         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
 398         WREG32(R_00004C_BUS_CNTL, tmp);
 399         /* FIXME: setup default page */
 400         WREG32_MC(R_000100_MC_PT0_CNTL,
 401                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 402                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 403
 404         for (i = 0; i < 19; i++) {
 405                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 406                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 407                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 408                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 409                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 410                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 411                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 412                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 413                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 414         }
 415         /* enable first context */
 416         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 417                   S_000102_ENABLE_PAGE_TABLE(1) |
 418                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 419
 420         /* disable all other contexts */
 421         for (i = 1; i < 8; i++)
 422                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 423
 424         /* setup the page table */
 425         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 426                   rdev->gart.table_addr);
 427         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 428         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 429         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 430
 431         /* System context maps to VRAM space */
 432         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 433         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 434
 435         /* enable page tables */
 436         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 437         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 438         tmp = RREG32_MC(R_000009_MC_CNTL1);
 439         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 440         rs600_gart_tlb_flush(rdev);
 441         rdev->gart.ready = true;
 442         return 0;
 443 }
 444
 445 void rs600_gart_disable(struct radeon_device *rdev)
 446 {
 447         u32 tmp;
 448         int r;
 449
 450         /* FIXME: disable out of gart access */
 451         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 452         tmp = RREG32_MC(R_000009_MC_CNTL1);
 453         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 454         if (rdev->gart.table.vram.robj) {
 455                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 456                 if (r == 0) {
 457                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 458                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 459                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 460                 }
 461         }
 462 }
 463
 464 void rs600_gart_fini(struct radeon_device *rdev)
 465 {
 466         radeon_gart_fini(rdev);
 467         rs600_gart_disable(rdev);
 468         radeon_gart_table_vram_free(rdev);
 469 }
 470
 471 #define R600_PTE_VALID     (1 << 0)
 472 #define R600_PTE_SYSTEM    (1 << 1)
 473 #define R600_PTE_SNOOPED   (1 << 2)
 474 #define R600_PTE_READABLE  (1 << 5)
 475 #define R600_PTE_WRITEABLE (1 << 6)
 476
 477 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 478 {
 479         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 480
 481         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 482                 return -EINVAL;
 483         }
 484         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 485         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 486         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 487         writeq(addr, ((void __iomem *)ptr) + (i * 8));
 488         return 0;
 489 }
 490
 491 int rs600_irq_set(struct radeon_device *rdev)
 492 {
 493         uint32_t tmp = 0;
 494         uint32_t mode_int = 0;
 495         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 496                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 497         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 498                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 499
 500         if (!rdev->irq.installed) {
 501                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 502                 WREG32(R_000040_GEN_INT_CNTL, 0);
 503                 return -EINVAL;
 504         }
 505         if (rdev->irq.sw_int) {
 506                 tmp |= S_000040_SW_INT_EN(1);
 507         }
 508         if (rdev->irq.gui_idle) {
 509                 tmp |= S_000040_GUI_IDLE(1);
 510         }
 511         if (rdev->irq.crtc_vblank_int[0]) {
 512                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 513         }
 514         if (rdev->irq.crtc_vblank_int[1]) {
 515                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 516         }
 517         if (rdev->irq.hpd[0]) {
 518                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 519         }
 520         if (rdev->irq.hpd[1]) {
 521                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 522         }
 523         WREG32(R_000040_GEN_INT_CNTL, tmp);
 524         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 525         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 526         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 527         return 0;
 528 }
 529
 530 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
 531 {
 532         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 533         uint32_t irq_mask = S_000044_SW_INT(1);
 534         u32 tmp;
 535
 536         /* the interrupt works, but the status bit is permanently asserted */
 537         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 538                 if (!rdev->irq.gui_idle_acked)
 539                         irq_mask |= S_000044_GUI_IDLE_STAT(1);
 540         }
 541
 542         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 543                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 544                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
 545                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 546                                 S_006534_D1MODE_VBLANK_ACK(1));
 547                 }
 548                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
 549                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 550                                 S_006D34_D2MODE_VBLANK_ACK(1));
 551                 }
 552                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
 553                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 554                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 555                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 556                 }
 557                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
 558                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 559                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 560                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 561                 }
 562         } else {
 563                 *r500_disp_int = 0;
 564         }
 565
 566         if (irqs) {
 567                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 568         }
 569         return irqs & irq_mask;
 570 }
 571
 572 void rs600_irq_disable(struct radeon_device *rdev)
 573 {
 574         u32 tmp;
 575
 576         WREG32(R_000040_GEN_INT_CNTL, 0);
 577         WREG32(R_006540_DxMODE_INT_MASK, 0);
 578         /* Wait and acknowledge irq */
 579         mdelay(1);
 580         rs600_irq_ack(rdev, &tmp);
 581 }
 582
 583 int rs600_irq_process(struct radeon_device *rdev)
 584 {
 585         uint32_t status, msi_rearm;
 586         uint32_t r500_disp_int;
 587         bool queue_hotplug = false;
 588
 589         /* reset gui idle ack.  the status bit is broken */
 590         rdev->irq.gui_idle_acked = false;
 591
 592         status = rs600_irq_ack(rdev, &r500_disp_int);
 593         if (!status && !r500_disp_int) {
 594                 return IRQ_NONE;
 595         }
 596         while (status || r500_disp_int) {
 597                 /* SW interrupt */
 598                 if (G_000044_SW_INT(status))
 599                         radeon_fence_process(rdev);
 600                 /* GUI idle */
 601                 if (G_000040_GUI_IDLE(status)) {
 602                         rdev->irq.gui_idle_acked = true;
 603                         rdev->pm.gui_idle = true;
 604                         wake_up(&rdev->irq.idle_queue);
 605                 }
 606                 /* Vertical blank interrupts */
 607                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
 608                         drm_handle_vblank(rdev->ddev, 0);
 609                         rdev->pm.vblank_sync = true;
 610                         wake_up(&rdev->irq.vblank_queue);
 611                 }
 612                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
 613                         drm_handle_vblank(rdev->ddev, 1);
 614                         rdev->pm.vblank_sync = true;
 615                         wake_up(&rdev->irq.vblank_queue);
 616                 }
 617                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
 618                         queue_hotplug = true;
 619                         DRM_DEBUG("HPD1\n");
 620                 }
 621                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
 622                         queue_hotplug = true;
 623                         DRM_DEBUG("HPD2\n");
 624                 }
 625                 status = rs600_irq_ack(rdev, &r500_disp_int);
 626         }
 627         /* reset gui idle ack.  the status bit is broken */
 628         rdev->irq.gui_idle_acked = false;
 629         if (queue_hotplug)
 630                 queue_work(rdev->wq, &rdev->hotplug_work);
 631         if (rdev->msi_enabled) {
 632                 switch (rdev->family) {
 633                 case CHIP_RS600:
 634                 case CHIP_RS690:
 635                 case CHIP_RS740:
 636                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 637                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 638                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 639                         break;
 640                 default:
 641                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 642                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 643                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 644                         break;
 645                 }
 646         }
 647         return IRQ_HANDLED;
 648 }
 649
 650 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 651 {
 652         if (crtc == 0)
 653                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 654         else
 655                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 656 }
 657
 658 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 659 {
 660         unsigned i;
 661
 662         for (i = 0; i < rdev->usec_timeout; i++) {
 663                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 664                         return 0;
 665                 udelay(1);
 666         }
 667         return -1;
 668 }
 669
 670 void rs600_gpu_init(struct radeon_device *rdev)
 671 {
 672         r420_pipes_init(rdev);
 673         /* Wait for mc idle */
 674         if (rs600_mc_wait_for_idle(rdev))
 675                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 676 }
 677
 678 void rs600_mc_init(struct radeon_device *rdev)
 679 {
 680         u64 base;
 681
 682         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 683         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 684         rdev->mc.vram_is_ddr = true;
 685         rdev->mc.vram_width = 128;
 686         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 687         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 688         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 689         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 690         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 691         base = G_000004_MC_FB_START(base) << 16;
 692         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 693         radeon_vram_location(rdev, &rdev->mc, base);
 694         radeon_gtt_location(rdev, &rdev->mc);
 695         radeon_update_bandwidth_info(rdev);
 696 }
 697
 698 void rs600_bandwidth_update(struct radeon_device *rdev)
 699 {
 700         struct drm_display_mode *mode0 = NULL;
 701         struct drm_display_mode *mode1 = NULL;
 702         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 703         /* FIXME: implement full support */
 704
 705         radeon_update_display_priority(rdev);
 706
 707         if (rdev->mode_info.crtcs[0]->base.enabled)
 708                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 709         if (rdev->mode_info.crtcs[1]->base.enabled)
 710                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 711
 712         rs690_line_buffer_adjust(rdev, mode0, mode1);
 713
 714         if (rdev->disp_priority == 2) {
 715                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 716                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 717                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 718                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 719                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 720                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 721                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 722                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 723         }
 724 }
 725
 726 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 727 {
 728         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 729                 S_000070_MC_IND_CITF_ARB0(1));
 730         return RREG32(R_000074_MC_IND_DATA);
 731 }
 732
 733 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 734 {
 735         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 736                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 737         WREG32(R_000074_MC_IND_DATA, v);
 738 }
 739
 740 void rs600_debugfs(struct radeon_device *rdev)
 741 {
 742         if (r100_debugfs_rbbm_init(rdev))
 743                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 744 }
 745
 746 void rs600_set_safe_registers(struct radeon_device *rdev)
 747 {
 748         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 749         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 750 }
 751
 752 static void rs600_mc_program(struct radeon_device *rdev)
 753 {
 754         struct rv515_mc_save save;
 755
 756         /* Stops all mc clients */
 757         rv515_mc_stop(rdev, &save);
 758
 759         /* Wait for mc idle */
 760         if (rs600_mc_wait_for_idle(rdev))
 761                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 762
 763         /* FIXME: What does AGP means for such chipset ? */
 764         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 765         WREG32_MC(R_000006_AGP_BASE, 0);
 766         WREG32_MC(R_000007_AGP_BASE_2, 0);
 767         /* Program MC */
 768         WREG32_MC(R_000004_MC_FB_LOCATION,
 769                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 770                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 771         WREG32(R_000134_HDP_FB_LOCATION,
 772                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 773
 774         rv515_mc_resume(rdev, &save);
 775 }
 776
 777 static int rs600_startup(struct radeon_device *rdev)
 778 {
 779         int r;
 780
 781         rs600_mc_program(rdev);
 782         /* Resume clock */
 783         rv515_clock_startup(rdev);
 784         /* Initialize GPU configuration (# pipes, ...) */
 785         rs600_gpu_init(rdev);
 786         /* Initialize GART (initialize after TTM so we can allocate
 787          * memory through TTM but finalize after TTM) */
 788         r = rs600_gart_enable(rdev);
 789         if (r)
 790                 return r;
 791         /* Enable IRQ */
 792         rs600_irq_set(rdev);
 793         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 794         /* 1M ring buffer */
 795         r = r100_cp_init(rdev, 1024 * 1024);
 796         if (r) {
 797                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 798                 return r;
 799         }
 800         r = r100_wb_init(rdev);
 801         if (r)
 802                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 803         r = r100_ib_init(rdev);
 804         if (r) {
 805                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 806                 return r;
 807         }
 808         return 0;
 809 }
 810
 811 int rs600_resume(struct radeon_device *rdev)
 812 {
 813         /* Make sur GART are not working */
 814         rs600_gart_disable(rdev);
 815         /* Resume clock before doing reset */
 816         rv515_clock_startup(rdev);
 817         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 818         if (radeon_asic_reset(rdev)) {
 819                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 820                         RREG32(R_000E40_RBBM_STATUS),
 821                         RREG32(R_0007C0_CP_STAT));
 822         }
 823         /* post */
 824         atom_asic_init(rdev->mode_info.atom_context);
 825         /* Resume clock after posting */
 826         rv515_clock_startup(rdev);
 827         /* Initialize surface registers */
 828         radeon_surface_init(rdev);
 829         return rs600_startup(rdev);
 830 }
 831
 832 int rs600_suspend(struct radeon_device *rdev)
 833 {
 834         r100_cp_disable(rdev);
 835         r100_wb_disable(rdev);
 836         rs600_irq_disable(rdev);
 837         rs600_gart_disable(rdev);
 838         return 0;
 839 }
 840
 841 void rs600_fini(struct radeon_device *rdev)
 842 {
 843         radeon_pm_fini(rdev);
 844         r100_cp_fini(rdev);
 845         r100_wb_fini(rdev);
 846         r100_ib_fini(rdev);
 847         radeon_gem_fini(rdev);
 848         rs600_gart_fini(rdev);
 849         radeon_irq_kms_fini(rdev);
 850         radeon_fence_driver_fini(rdev);
 851         radeon_bo_fini(rdev);
 852         radeon_atombios_fini(rdev);
 853         kfree(rdev->bios);
 854         rdev->bios = NULL;
 855 }
 856
 857 int rs600_init(struct radeon_device *rdev)
 858 {
 859         int r;
 860
 861         /* Disable VGA */
 862         rv515_vga_render_disable(rdev);
 863         /* Initialize scratch registers */
 864         radeon_scratch_init(rdev);
 865         /* Initialize surface registers */
 866         radeon_surface_init(rdev);
 867         /* BIOS */
 868         if (!radeon_get_bios(rdev)) {
 869                 if (ASIC_IS_AVIVO(rdev))
 870                         return -EINVAL;
 871         }
 872         if (rdev->is_atom_bios) {
 873                 r = radeon_atombios_init(rdev);
 874                 if (r)
 875                         return r;
 876         } else {
 877                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
 878                 return -EINVAL;
 879         }
 880         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 881         if (radeon_asic_reset(rdev)) {
 882                 dev_warn(rdev->dev,
 883                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 884                         RREG32(R_000E40_RBBM_STATUS),
 885                         RREG32(R_0007C0_CP_STAT));
 886         }
 887         /* check if cards are posted or not */
 888         if (radeon_boot_test_post_card(rdev) == false)
 889                 return -EINVAL;
 890
 891         /* Initialize clocks */
 892         radeon_get_clock_info(rdev->ddev);
 893         /* Initialize power management */
 894         radeon_pm_init(rdev);
 895         /* initialize memory controller */
 896         rs600_mc_init(rdev);
 897         rs600_debugfs(rdev);
 898         /* Fence driver */
 899         r = radeon_fence_driver_init(rdev);
 900         if (r)
 901                 return r;
 902         r = radeon_irq_kms_init(rdev);
 903         if (r)
 904                 return r;
 905         /* Memory manager */
 906         r = radeon_bo_init(rdev);
 907         if (r)
 908                 return r;
 909         r = rs600_gart_init(rdev);
 910         if (r)
 911                 return r;
 912         rs600_set_safe_registers(rdev);
 913         rdev->accel_working = true;
 914         r = rs600_startup(rdev);
 915         if (r) {
 916                 /* Somethings want wront with the accel init stop accel */
 917                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 918                 r100_cp_fini(rdev);
 919                 r100_wb_fini(rdev);
 920                 r100_ib_fini(rdev);
 921                 rs600_gart_fini(rdev);
 922                 radeon_irq_kms_fini(rdev);
 923                 rdev->accel_working = false;
 924         }
 925         return 0;
 926 }