2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
33 static void radeon_overscan_setup(struct drm_crtc *crtc,
34 struct drm_display_mode *mode)
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode)
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 int xres = mode->hdisplay;
52 int yres = mode->vdisplay;
53 bool hscale = true, vscale = true;
58 u32 scale, inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65 (RADEON_VERT_STRETCH_RESERVED |
66 RADEON_VERT_AUTO_RATIO_INC);
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68 (RADEON_HORZ_FP_LOOP_STRETCH |
69 RADEON_HORZ_AUTO_RATIO_INC);
72 if ((rdev->family == CHIP_RS100) ||
73 (rdev->family == CHIP_RS200)) {
74 /* This is to workaround the asic bug for RMX, some versions
75 of BIOS dosen't have this register initialized correctly. */
76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
86 hsync_start = mode->crtc_hsync_start - 8;
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91 ? RADEON_CRTC_H_SYNC_POL
94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95 | ((mode->crtc_vdisplay - 1) << 16));
97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102 | ((vsync_wid & 0x1f) << 16)
103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104 ? RADEON_CRTC_V_SYNC_POL
107 fp_horz_vert_active = 0;
109 if (native_mode->hdisplay == 0 ||
110 native_mode->vdisplay == 0) {
114 if (xres > native_mode->hdisplay)
115 xres = native_mode->hdisplay;
116 if (yres > native_mode->vdisplay)
117 yres = native_mode->vdisplay;
119 if (xres == native_mode->hdisplay)
121 if (yres == native_mode->vdisplay)
125 switch (radeon_crtc->rmx_type) {
129 fp_horz_stretch |= ((xres/8-1) << 16);
131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133 / native_mode->hdisplay + 1;
134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135 RADEON_HORZ_STRETCH_BLEND |
136 RADEON_HORZ_STRETCH_ENABLE |
137 ((native_mode->hdisplay/8-1) << 16));
141 fp_vert_stretch |= ((yres-1) << 12);
143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145 / native_mode->vdisplay + 1;
146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147 RADEON_VERT_STRETCH_ENABLE |
148 RADEON_VERT_STRETCH_BLEND |
149 ((native_mode->vdisplay-1) << 12));
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157 RADEON_CRTC_AUTO_VERT_CENTER_EN);
159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160 if (blank_width > 110)
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171 | ((hsync_wid & 0x3f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173 ? RADEON_CRTC_H_SYNC_POL
176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177 | ((mode->crtc_vdisplay - 1) << 16));
179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184 | ((vsync_wid & 0x1f) << 16)
185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186 ? RADEON_CRTC_V_SYNC_POL
189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
209 void radeon_restore_common_regs(struct drm_device *dev)
211 /* don't need this yet */
214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
216 struct radeon_device *rdev = dev->dev_private;
219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
220 the cause yet, but this workaround will mask the problem for now.
221 Other chips usually will pass at the very first test, so the
222 workaround shouldn't have any effect on them. */
225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
229 static void radeon_pll_write_update(struct drm_device *dev)
231 struct radeon_device *rdev = dev->dev_private;
233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
235 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236 RADEON_PPLL_ATOMIC_UPDATE_W,
237 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
242 struct radeon_device *rdev = dev->dev_private;
246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
247 the cause yet, but this workaround will mask the problem for now.
248 Other chips usually will pass at the very first test, so the
249 workaround shouldn't have any effect on them. */
252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
256 static void radeon_pll2_write_update(struct drm_device *dev)
258 struct radeon_device *rdev = dev->dev_private;
260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263 RADEON_P2PLL_ATOMIC_UPDATE_W,
264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
270 unsigned int vcoFreq;
275 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
278 * This is horribly crude: the VCO frequency range is divided into
279 * 3 parts, each part having a fixed PLL gain value.
281 if (vcoFreq >= 30000)
286 else if (vcoFreq >= 18000)
298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
305 if (radeon_crtc->crtc_id)
306 mask = (RADEON_CRTC2_DISP_DIS |
307 RADEON_CRTC2_VSYNC_DIS |
308 RADEON_CRTC2_HSYNC_DIS |
309 RADEON_CRTC2_DISP_REQ_EN_B);
311 mask = (RADEON_CRTC_DISPLAY_DIS |
312 RADEON_CRTC_VSYNC_DIS |
313 RADEON_CRTC_HSYNC_DIS);
316 case DRM_MODE_DPMS_ON:
317 if (radeon_crtc->crtc_id)
318 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
320 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
321 RADEON_CRTC_DISP_REQ_EN_B));
322 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
324 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
325 radeon_crtc_load_lut(crtc);
327 case DRM_MODE_DPMS_STANDBY:
328 case DRM_MODE_DPMS_SUSPEND:
329 case DRM_MODE_DPMS_OFF:
330 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
331 if (radeon_crtc->crtc_id)
332 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
334 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
335 RADEON_CRTC_DISP_REQ_EN_B));
336 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
342 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
343 struct drm_framebuffer *old_fb)
345 struct drm_device *dev = crtc->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348 struct radeon_framebuffer *radeon_fb;
349 struct drm_gem_object *obj;
350 struct radeon_bo *rbo;
352 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
353 uint32_t crtc_pitch, pitch_pixels;
354 uint32_t tiling_flags;
356 uint32_t gen_cntl_reg, gen_cntl_val;
362 DRM_DEBUG("No FB bound\n");
366 radeon_fb = to_radeon_framebuffer(crtc->fb);
368 switch (crtc->fb->bits_per_pixel) {
388 /* Pin framebuffer & get tilling informations */
389 obj = radeon_fb->obj;
390 rbo = obj->driver_private;
391 r = radeon_bo_reserve(rbo, false);
392 if (unlikely(r != 0))
394 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
395 if (unlikely(r != 0)) {
396 radeon_bo_unreserve(rbo);
399 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
400 radeon_bo_unreserve(rbo);
401 if (tiling_flags & RADEON_TILING_MICRO)
402 DRM_ERROR("trying to scanout microtiled buffer\n");
404 /* if scanout was in GTT this really wouldn't work */
405 /* crtc offset is from display base addr not FB location */
406 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
408 base -= radeon_crtc->legacy_display_base_addr;
410 crtc_offset_cntl = 0;
412 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
413 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
414 ((crtc->fb->bits_per_pixel * 8) - 1)) /
415 (crtc->fb->bits_per_pixel * 8));
416 crtc_pitch |= crtc_pitch << 16;
419 if (tiling_flags & RADEON_TILING_MACRO) {
420 if (ASIC_IS_R300(rdev))
421 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
422 R300_CRTC_MICRO_TILE_BUFFER_DIS |
423 R300_CRTC_MACRO_TILE_EN);
425 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
427 if (ASIC_IS_R300(rdev))
428 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
429 R300_CRTC_MICRO_TILE_BUFFER_DIS |
430 R300_CRTC_MACRO_TILE_EN);
432 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
435 if (tiling_flags & RADEON_TILING_MACRO) {
436 if (ASIC_IS_R300(rdev)) {
437 crtc_tile_x0_y0 = x | (y << 16);
440 int byteshift = crtc->fb->bits_per_pixel >> 4;
441 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
442 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
443 crtc_offset_cntl |= (y % 16);
446 int offset = y * pitch_pixels + x;
447 switch (crtc->fb->bits_per_pixel) {
469 if (radeon_crtc->crtc_id == 1)
470 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
472 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
474 gen_cntl_val = RREG32(gen_cntl_reg);
475 gen_cntl_val &= ~(0xf << 8);
476 gen_cntl_val |= (format << 8);
477 WREG32(gen_cntl_reg, gen_cntl_val);
479 crtc_offset = (u32)base;
481 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
483 if (ASIC_IS_R300(rdev)) {
484 if (radeon_crtc->crtc_id)
485 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
487 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
489 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
490 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
491 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
493 if (old_fb && old_fb != crtc->fb) {
494 radeon_fb = to_radeon_framebuffer(old_fb);
495 rbo = radeon_fb->obj->driver_private;
496 r = radeon_bo_reserve(rbo, false);
497 if (unlikely(r != 0))
499 radeon_bo_unpin(rbo);
500 radeon_bo_unreserve(rbo);
503 /* Bytes per pixel may have changed */
504 radeon_bandwidth_update(rdev);
509 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
514 struct drm_encoder *encoder;
519 uint32_t crtc_h_total_disp;
520 uint32_t crtc_h_sync_strt_wid;
521 uint32_t crtc_v_total_disp;
522 uint32_t crtc_v_sync_strt_wid;
526 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
527 if (encoder->crtc == crtc) {
528 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
529 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
531 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
537 switch (crtc->fb->bits_per_pixel) {
557 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
558 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
560 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
563 hsync_start = mode->crtc_hsync_start - 8;
565 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
566 | ((hsync_wid & 0x3f) << 16)
567 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
568 ? RADEON_CRTC_H_SYNC_POL
571 /* This works for double scan mode. */
572 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
573 | ((mode->crtc_vdisplay - 1) << 16));
575 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
579 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
580 | ((vsync_wid & 0x1f) << 16)
581 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
582 ? RADEON_CRTC_V_SYNC_POL
585 if (radeon_crtc->crtc_id) {
586 uint32_t crtc2_gen_cntl;
587 uint32_t disp2_merge_cntl;
589 /* if TV DAC is enabled for another crtc and keep it enabled */
590 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
591 crtc2_gen_cntl |= ((format << 8)
592 | RADEON_CRTC2_VSYNC_DIS
593 | RADEON_CRTC2_HSYNC_DIS
594 | RADEON_CRTC2_DISP_DIS
595 | RADEON_CRTC2_DISP_REQ_EN_B
596 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
597 ? RADEON_CRTC2_DBL_SCAN_EN
599 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
600 ? RADEON_CRTC2_CSYNC_EN
602 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
603 ? RADEON_CRTC2_INTERLACE_EN
606 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
607 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
609 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
610 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
612 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
613 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
615 uint32_t crtc_gen_cntl;
616 uint32_t crtc_ext_cntl;
617 uint32_t disp_merge_cntl;
619 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
620 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
622 | RADEON_CRTC_DISP_REQ_EN_B
623 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
624 ? RADEON_CRTC_DBL_SCAN_EN
626 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
627 ? RADEON_CRTC_CSYNC_EN
629 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
630 ? RADEON_CRTC_INTERLACE_EN
633 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
634 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
635 RADEON_CRTC_VSYNC_DIS |
636 RADEON_CRTC_HSYNC_DIS |
637 RADEON_CRTC_DISPLAY_DIS);
639 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
640 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
642 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
643 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
644 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
648 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
649 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
650 &crtc_v_sync_strt_wid);
652 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
653 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
654 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
655 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
660 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
662 struct drm_device *dev = crtc->dev;
663 struct radeon_device *rdev = dev->dev_private;
664 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
665 struct drm_encoder *encoder;
666 uint32_t feedback_div = 0;
667 uint32_t frac_fb_div = 0;
668 uint32_t reference_div = 0;
669 uint32_t post_divider = 0;
672 bool use_bios_divs = false;
674 uint32_t pll_ref_div = 0;
675 uint32_t pll_fb_post_div = 0;
676 uint32_t htotal_cntl = 0;
678 struct radeon_pll *pll;
683 } *post_div, post_divs[] = {
684 /* From RAGE 128 VR/RAGE 128 GL Register
685 * Reference Manual (Technical Reference
686 * Manual P/N RRG-G04100-C Rev. 0.04), page
687 * 3-17 (PLL_DIV_[3:0]).
689 { 1, 0 }, /* VCLK_SRC */
690 { 2, 1 }, /* VCLK_SRC/2 */
691 { 4, 2 }, /* VCLK_SRC/4 */
692 { 8, 3 }, /* VCLK_SRC/8 */
693 { 3, 4 }, /* VCLK_SRC/3 */
694 { 16, 5 }, /* VCLK_SRC/16 */
695 { 6, 6 }, /* VCLK_SRC/6 */
696 { 12, 7 }, /* VCLK_SRC/12 */
700 if (radeon_crtc->crtc_id)
701 pll = &rdev->clock.p2pll;
703 pll = &rdev->clock.p1pll;
705 pll->flags = RADEON_PLL_LEGACY;
707 if (mode->clock > 200000) /* range limits??? */
708 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
710 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
712 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
713 if (encoder->crtc == crtc) {
714 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
716 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
721 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
722 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
723 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
724 if (!rdev->is_atom_bios) {
725 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
726 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
728 if (lvds->use_bios_dividers) {
729 pll_ref_div = lvds->panel_ref_divider;
730 pll_fb_post_div = (lvds->panel_fb_divider |
731 (lvds->panel_post_divider << 16));
733 use_bios_divs = true;
737 pll->flags |= RADEON_PLL_USE_REF_DIV;
744 if (!use_bios_divs) {
745 radeon_compute_pll(pll, mode->clock,
746 &freq, &feedback_div, &frac_fb_div,
747 &reference_div, &post_divider);
749 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
750 if (post_div->divider == post_divider)
754 if (!post_div->divider)
755 post_div = &post_divs[0];
757 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
763 pll_ref_div = reference_div;
764 #if defined(__powerpc__) && (0) /* TODO */
765 /* apparently programming this otherwise causes a hang??? */
766 if (info->MacModel == RADEON_MAC_IBOOK)
767 pll_fb_post_div = 0x000600ad;
770 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
772 htotal_cntl = mode->htotal & 0x7;
776 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
778 pll_fb_post_div & 0x7ff);
780 if (radeon_crtc->crtc_id) {
781 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
782 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
783 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
786 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
787 &pll_ref_div, &pll_fb_post_div,
791 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
792 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
793 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
795 WREG32_PLL_P(RADEON_P2PLL_CNTL,
797 | RADEON_P2PLL_ATOMIC_UPDATE_EN
798 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
800 | RADEON_P2PLL_ATOMIC_UPDATE_EN
801 | RADEON_P2PLL_PVG_MASK));
803 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
805 ~RADEON_P2PLL_REF_DIV_MASK);
807 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
809 ~RADEON_P2PLL_FB0_DIV_MASK);
811 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
813 ~RADEON_P2PLL_POST0_DIV_MASK);
815 radeon_pll2_write_update(dev);
816 radeon_pll2_wait_for_read_update_complete(dev);
818 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
820 WREG32_PLL_P(RADEON_P2PLL_CNTL,
824 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
826 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
827 (unsigned)pll_ref_div,
828 (unsigned)pll_fb_post_div,
829 (unsigned)htotal_cntl,
830 RREG32_PLL(RADEON_P2PLL_CNTL));
831 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
832 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
833 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
834 (unsigned)((pll_fb_post_div &
835 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
837 mdelay(50); /* Let the clock to lock */
839 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
840 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
841 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
843 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
845 uint32_t pixclks_cntl;
849 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
850 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
851 &pll_fb_post_div, &pixclks_cntl);
854 if (rdev->flags & RADEON_IS_MOBILITY) {
855 /* A temporal workaround for the occational blanking on certain laptop panels.
856 This appears to related to the PLL divider registers (fail to lock?).
857 It occurs even when all dividers are the same with their old settings.
858 In this case we really don't need to fiddle with PLL registers.
859 By doing this we can avoid the blanking problem with some panels.
861 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
862 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
863 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
864 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
866 ~(RADEON_PLL_DIV_SEL));
867 r100_pll_errata_after_index(rdev);
872 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
873 RADEON_VCLK_SRC_SEL_CPUCLK,
874 ~(RADEON_VCLK_SRC_SEL_MASK));
875 WREG32_PLL_P(RADEON_PPLL_CNTL,
877 | RADEON_PPLL_ATOMIC_UPDATE_EN
878 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
879 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
881 | RADEON_PPLL_ATOMIC_UPDATE_EN
882 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
883 | RADEON_PPLL_PVG_MASK));
885 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
887 ~(RADEON_PLL_DIV_SEL));
888 r100_pll_errata_after_index(rdev);
890 if (ASIC_IS_R300(rdev) ||
891 (rdev->family == CHIP_RS300) ||
892 (rdev->family == CHIP_RS400) ||
893 (rdev->family == CHIP_RS480)) {
894 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
895 /* When restoring console mode, use saved PPLL_REF_DIV
898 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
902 /* R300 uses ref_div_acc field as real ref divider */
903 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
904 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
905 ~R300_PPLL_REF_DIV_ACC_MASK);
908 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
910 ~RADEON_PPLL_REF_DIV_MASK);
912 WREG32_PLL_P(RADEON_PPLL_DIV_3,
914 ~RADEON_PPLL_FB3_DIV_MASK);
916 WREG32_PLL_P(RADEON_PPLL_DIV_3,
918 ~RADEON_PPLL_POST3_DIV_MASK);
920 radeon_pll_write_update(dev);
921 radeon_pll_wait_for_read_update_complete(dev);
923 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
925 WREG32_PLL_P(RADEON_PPLL_CNTL,
929 | RADEON_PPLL_ATOMIC_UPDATE_EN
930 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
932 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
935 (unsigned)htotal_cntl,
936 RREG32_PLL(RADEON_PPLL_CNTL));
937 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
938 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
939 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
940 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
942 mdelay(50); /* Let the clock to lock */
944 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
945 RADEON_VCLK_SRC_SEL_PPLLCLK,
946 ~(RADEON_VCLK_SRC_SEL_MASK));
949 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
953 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
954 struct drm_display_mode *mode,
955 struct drm_display_mode *adjusted_mode)
957 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
962 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
963 struct drm_display_mode *mode,
964 struct drm_display_mode *adjusted_mode,
965 int x, int y, struct drm_framebuffer *old_fb)
967 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
970 radeon_crtc_set_base(crtc, x, y, old_fb);
971 radeon_set_crtc_timing(crtc, adjusted_mode);
972 radeon_set_pll(crtc, adjusted_mode);
973 radeon_overscan_setup(crtc, adjusted_mode);
974 if (radeon_crtc->crtc_id == 0) {
975 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
977 if (radeon_crtc->rmx_type != RMX_OFF) {
978 /* FIXME: only first crtc has rmx what should we
981 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
987 static void radeon_crtc_prepare(struct drm_crtc *crtc)
989 struct drm_device *dev = crtc->dev;
990 struct drm_crtc *crtci;
993 * The hardware wedges sometimes if you reconfigure one CRTC
994 * whilst another is running (see fdo bug #24611).
996 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
997 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1000 static void radeon_crtc_commit(struct drm_crtc *crtc)
1002 struct drm_device *dev = crtc->dev;
1003 struct drm_crtc *crtci;
1006 * Reenable the CRTCs that should be running.
1008 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1010 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1014 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1015 .dpms = radeon_crtc_dpms,
1016 .mode_fixup = radeon_crtc_mode_fixup,
1017 .mode_set = radeon_crtc_mode_set,
1018 .mode_set_base = radeon_crtc_set_base,
1019 .prepare = radeon_crtc_prepare,
1020 .commit = radeon_crtc_commit,
1021 .load_lut = radeon_crtc_load_lut,
1025 void radeon_legacy_init_crtc(struct drm_device *dev,
1026 struct radeon_crtc *radeon_crtc)
1028 if (radeon_crtc->crtc_id == 1)
1029 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1030 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);