2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
32 void radeon_restore_common_regs(struct drm_device *dev)
34 /* don't need this yet */
37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
39 struct radeon_device *rdev = dev->dev_private;
42 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
43 the cause yet, but this workaround will mask the problem for now.
44 Other chips usually will pass at the very first test, so the
45 workaround shouldn't have any effect on them. */
48 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
52 static void radeon_pll_write_update(struct drm_device *dev)
54 struct radeon_device *rdev = dev->dev_private;
56 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
58 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
59 RADEON_PPLL_ATOMIC_UPDATE_W,
60 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
65 struct radeon_device *rdev = dev->dev_private;
69 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
70 the cause yet, but this workaround will mask the problem for now.
71 Other chips usually will pass at the very first test, so the
72 workaround shouldn't have any effect on them. */
75 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
79 static void radeon_pll2_write_update(struct drm_device *dev)
81 struct radeon_device *rdev = dev->dev_private;
83 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
85 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
86 RADEON_P2PLL_ATOMIC_UPDATE_W,
87 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
98 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
101 * This is horribly crude: the VCO frequency range is divided into
102 * 3 parts, each part having a fixed PLL gain value.
104 if (vcoFreq >= 30000)
109 else if (vcoFreq >= 18000)
121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
124 struct drm_device *dev = crtc->dev;
125 struct radeon_device *rdev = dev->dev_private;
128 if (radeon_crtc->crtc_id)
129 mask = (RADEON_CRTC2_EN |
130 RADEON_CRTC2_DISP_DIS |
131 RADEON_CRTC2_VSYNC_DIS |
132 RADEON_CRTC2_HSYNC_DIS |
133 RADEON_CRTC2_DISP_REQ_EN_B);
135 mask = (RADEON_CRTC_DISPLAY_DIS |
136 RADEON_CRTC_VSYNC_DIS |
137 RADEON_CRTC_HSYNC_DIS);
140 case DRM_MODE_DPMS_ON:
141 if (radeon_crtc->crtc_id)
142 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
144 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
145 RADEON_CRTC_DISP_REQ_EN_B));
146 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
149 case DRM_MODE_DPMS_STANDBY:
150 case DRM_MODE_DPMS_SUSPEND:
151 case DRM_MODE_DPMS_OFF:
152 if (radeon_crtc->crtc_id)
153 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
155 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
156 RADEON_CRTC_DISP_REQ_EN_B));
157 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
162 if (mode != DRM_MODE_DPMS_OFF) {
163 radeon_crtc_load_lut(crtc);
167 /* properly set crtc bpp when using atombios */
168 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
170 struct drm_device *dev = crtc->dev;
171 struct radeon_device *rdev = dev->dev_private;
172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
174 uint32_t crtc_gen_cntl;
175 uint32_t disp_merge_cntl;
178 switch (crtc->fb->bits_per_pixel) {
195 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
196 ((crtc->fb->bits_per_pixel * 8) - 1)) /
197 (crtc->fb->bits_per_pixel * 8));
198 crtc_pitch |= crtc_pitch << 16;
200 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
202 switch (radeon_crtc->crtc_id) {
204 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
205 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
206 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
208 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
209 crtc_gen_cntl |= (format << 8);
210 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
211 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
214 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
215 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
216 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
218 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
219 crtc_gen_cntl |= (format << 8);
220 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
221 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
222 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
227 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
228 struct drm_framebuffer *old_fb)
230 struct drm_device *dev = crtc->dev;
231 struct radeon_device *rdev = dev->dev_private;
232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
233 struct radeon_framebuffer *radeon_fb;
234 struct drm_gem_object *obj;
236 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
237 uint32_t crtc_pitch, pitch_pixels;
238 uint32_t tiling_flags;
242 radeon_fb = to_radeon_framebuffer(crtc->fb);
244 obj = radeon_fb->obj;
245 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
248 /* if scanout was in GTT this really wouldn't work */
249 /* crtc offset is from display base addr not FB location */
250 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
252 base -= radeon_crtc->legacy_display_base_addr;
254 crtc_offset_cntl = 0;
256 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
257 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
258 ((crtc->fb->bits_per_pixel * 8) - 1)) /
259 (crtc->fb->bits_per_pixel * 8));
260 crtc_pitch |= crtc_pitch << 16;
262 radeon_object_get_tiling_flags(obj->driver_private,
263 &tiling_flags, NULL);
264 if (tiling_flags & RADEON_TILING_MICRO)
265 DRM_ERROR("trying to scanout microtiled buffer\n");
267 if (tiling_flags & RADEON_TILING_MACRO) {
268 if (ASIC_IS_R300(rdev))
269 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
270 R300_CRTC_MICRO_TILE_BUFFER_DIS |
271 R300_CRTC_MACRO_TILE_EN);
273 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
275 if (ASIC_IS_R300(rdev))
276 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
277 R300_CRTC_MICRO_TILE_BUFFER_DIS |
278 R300_CRTC_MACRO_TILE_EN);
280 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
283 if (tiling_flags & RADEON_TILING_MACRO) {
284 if (ASIC_IS_R300(rdev)) {
285 crtc_tile_x0_y0 = x | (y << 16);
288 int byteshift = crtc->fb->bits_per_pixel >> 4;
289 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
290 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
291 crtc_offset_cntl |= (y % 16);
294 int offset = y * pitch_pixels + x;
295 switch (crtc->fb->bits_per_pixel) {
314 crtc_offset = (u32)base;
316 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
318 if (ASIC_IS_R300(rdev)) {
319 if (radeon_crtc->crtc_id)
320 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
322 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
324 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
325 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
326 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
328 if (old_fb && old_fb != crtc->fb) {
329 radeon_fb = to_radeon_framebuffer(old_fb);
330 radeon_gem_object_unpin(radeon_fb->obj);
335 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
337 struct drm_device *dev = crtc->dev;
338 struct radeon_device *rdev = dev->dev_private;
339 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
344 uint32_t crtc_h_total_disp;
345 uint32_t crtc_h_sync_strt_wid;
346 uint32_t crtc_v_total_disp;
347 uint32_t crtc_v_sync_strt_wid;
351 switch (crtc->fb->bits_per_pixel) {
368 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
369 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
371 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
374 hsync_start = mode->crtc_hsync_start - 8;
376 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
377 | ((hsync_wid & 0x3f) << 16)
378 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
379 ? RADEON_CRTC_H_SYNC_POL
382 /* This works for double scan mode. */
383 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
384 | ((mode->crtc_vdisplay - 1) << 16));
386 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
390 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
391 | ((vsync_wid & 0x1f) << 16)
392 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
393 ? RADEON_CRTC_V_SYNC_POL
396 /* TODO -> Dell Server */
398 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
399 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
400 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
401 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
403 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
404 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
406 /* For CRT on DAC2, don't turn it on if BIOS didn't
407 enable it, even it's detected.
409 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
410 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
411 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
413 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
414 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
415 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
416 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
419 if (radeon_crtc->crtc_id) {
420 uint32_t crtc2_gen_cntl;
421 uint32_t disp2_merge_cntl;
423 /* check to see if TV DAC is enabled for another crtc and keep it enabled */
424 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
425 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
429 crtc2_gen_cntl |= ((format << 8)
430 | RADEON_CRTC2_VSYNC_DIS
431 | RADEON_CRTC2_HSYNC_DIS
432 | RADEON_CRTC2_DISP_DIS
433 | RADEON_CRTC2_DISP_REQ_EN_B
434 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
435 ? RADEON_CRTC2_DBL_SCAN_EN
437 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
438 ? RADEON_CRTC2_CSYNC_EN
440 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
441 ? RADEON_CRTC2_INTERLACE_EN
444 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
445 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
447 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
448 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
450 uint32_t crtc_gen_cntl;
451 uint32_t crtc_ext_cntl;
452 uint32_t disp_merge_cntl;
454 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
456 | RADEON_CRTC_DISP_REQ_EN_B
457 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
458 ? RADEON_CRTC_DBL_SCAN_EN
460 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
461 ? RADEON_CRTC_CSYNC_EN
463 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
464 ? RADEON_CRTC_INTERLACE_EN
467 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
468 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
469 RADEON_CRTC_VSYNC_DIS |
470 RADEON_CRTC_HSYNC_DIS |
471 RADEON_CRTC_DISPLAY_DIS);
473 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
474 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
476 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
477 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
478 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
481 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
482 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
483 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
484 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
489 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
491 struct drm_device *dev = crtc->dev;
492 struct radeon_device *rdev = dev->dev_private;
493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
494 struct drm_encoder *encoder;
495 uint32_t feedback_div = 0;
496 uint32_t frac_fb_div = 0;
497 uint32_t reference_div = 0;
498 uint32_t post_divider = 0;
501 int pll_flags = RADEON_PLL_LEGACY;
502 bool use_bios_divs = false;
504 uint32_t pll_ref_div = 0;
505 uint32_t pll_fb_post_div = 0;
506 uint32_t htotal_cntl = 0;
508 struct radeon_pll *pll;
513 } *post_div, post_divs[] = {
514 /* From RAGE 128 VR/RAGE 128 GL Register
515 * Reference Manual (Technical Reference
516 * Manual P/N RRG-G04100-C Rev. 0.04), page
517 * 3-17 (PLL_DIV_[3:0]).
519 { 1, 0 }, /* VCLK_SRC */
520 { 2, 1 }, /* VCLK_SRC/2 */
521 { 4, 2 }, /* VCLK_SRC/4 */
522 { 8, 3 }, /* VCLK_SRC/8 */
523 { 3, 4 }, /* VCLK_SRC/3 */
524 { 16, 5 }, /* VCLK_SRC/16 */
525 { 6, 6 }, /* VCLK_SRC/6 */
526 { 12, 7 }, /* VCLK_SRC/12 */
530 if (radeon_crtc->crtc_id)
531 pll = &rdev->clock.p2pll;
533 pll = &rdev->clock.p1pll;
535 if (mode->clock > 200000) /* range limits??? */
536 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
538 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
541 if (encoder->crtc == crtc) {
542 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
543 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
544 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
546 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
548 if (lvds->use_bios_dividers) {
549 pll_ref_div = lvds->panel_ref_divider;
550 pll_fb_post_div = (lvds->panel_fb_divider |
551 (lvds->panel_post_divider << 16));
553 use_bios_divs = true;
556 pll_flags |= RADEON_PLL_USE_REF_DIV;
563 if (!use_bios_divs) {
564 radeon_compute_pll(pll, mode->clock,
565 &freq, &feedback_div, &frac_fb_div,
566 &reference_div, &post_divider,
569 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
570 if (post_div->divider == post_divider)
574 if (!post_div->divider)
575 post_div = &post_divs[0];
577 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
583 pll_ref_div = reference_div;
584 #if defined(__powerpc__) && (0) /* TODO */
585 /* apparently programming this otherwise causes a hang??? */
586 if (info->MacModel == RADEON_MAC_IBOOK)
587 pll_fb_post_div = 0x000600ad;
590 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
592 htotal_cntl = mode->htotal & 0x7;
596 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
598 pll_fb_post_div & 0x7ff);
600 if (radeon_crtc->crtc_id) {
601 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
602 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
603 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
605 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
606 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
607 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
609 WREG32_PLL_P(RADEON_P2PLL_CNTL,
611 | RADEON_P2PLL_ATOMIC_UPDATE_EN
612 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
614 | RADEON_P2PLL_ATOMIC_UPDATE_EN
615 | RADEON_P2PLL_PVG_MASK));
617 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
619 ~RADEON_P2PLL_REF_DIV_MASK);
621 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
623 ~RADEON_P2PLL_FB0_DIV_MASK);
625 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
627 ~RADEON_P2PLL_POST0_DIV_MASK);
629 radeon_pll2_write_update(dev);
630 radeon_pll2_wait_for_read_update_complete(dev);
632 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
634 WREG32_PLL_P(RADEON_P2PLL_CNTL,
638 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
640 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
641 (unsigned)pll_ref_div,
642 (unsigned)pll_fb_post_div,
643 (unsigned)htotal_cntl,
644 RREG32_PLL(RADEON_P2PLL_CNTL));
645 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
646 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
647 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
648 (unsigned)((pll_fb_post_div &
649 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
651 mdelay(50); /* Let the clock to lock */
653 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
654 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
655 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
657 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
659 if (rdev->flags & RADEON_IS_MOBILITY) {
660 /* A temporal workaround for the occational blanking on certain laptop panels.
661 This appears to related to the PLL divider registers (fail to lock?).
662 It occurs even when all dividers are the same with their old settings.
663 In this case we really don't need to fiddle with PLL registers.
664 By doing this we can avoid the blanking problem with some panels.
666 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
667 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
668 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
669 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
671 ~(RADEON_PLL_DIV_SEL));
672 r100_pll_errata_after_index(rdev);
677 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
678 RADEON_VCLK_SRC_SEL_CPUCLK,
679 ~(RADEON_VCLK_SRC_SEL_MASK));
680 WREG32_PLL_P(RADEON_PPLL_CNTL,
682 | RADEON_PPLL_ATOMIC_UPDATE_EN
683 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
684 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
686 | RADEON_PPLL_ATOMIC_UPDATE_EN
687 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
688 | RADEON_PPLL_PVG_MASK));
690 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
692 ~(RADEON_PLL_DIV_SEL));
693 r100_pll_errata_after_index(rdev);
695 if (ASIC_IS_R300(rdev) ||
696 (rdev->family == CHIP_RS300) ||
697 (rdev->family == CHIP_RS400) ||
698 (rdev->family == CHIP_RS480)) {
699 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
700 /* When restoring console mode, use saved PPLL_REF_DIV
703 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
707 /* R300 uses ref_div_acc field as real ref divider */
708 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
709 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
710 ~R300_PPLL_REF_DIV_ACC_MASK);
713 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
715 ~RADEON_PPLL_REF_DIV_MASK);
717 WREG32_PLL_P(RADEON_PPLL_DIV_3,
719 ~RADEON_PPLL_FB3_DIV_MASK);
721 WREG32_PLL_P(RADEON_PPLL_DIV_3,
723 ~RADEON_PPLL_POST3_DIV_MASK);
725 radeon_pll_write_update(dev);
726 radeon_pll_wait_for_read_update_complete(dev);
728 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
730 WREG32_PLL_P(RADEON_PPLL_CNTL,
734 | RADEON_PPLL_ATOMIC_UPDATE_EN
735 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
737 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
740 (unsigned)htotal_cntl,
741 RREG32_PLL(RADEON_PPLL_CNTL));
742 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
743 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
744 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
745 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
747 mdelay(50); /* Let the clock to lock */
749 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
750 RADEON_VCLK_SRC_SEL_PPLLCLK,
751 ~(RADEON_VCLK_SRC_SEL_MASK));
756 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
757 struct drm_display_mode *mode,
758 struct drm_display_mode *adjusted_mode)
763 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
764 struct drm_display_mode *mode,
765 struct drm_display_mode *adjusted_mode,
766 int x, int y, struct drm_framebuffer *old_fb)
773 radeon_crtc_set_base(crtc, x, y, old_fb);
774 radeon_set_crtc_timing(crtc, adjusted_mode);
775 radeon_set_pll(crtc, adjusted_mode);
776 radeon_init_disp_bandwidth(crtc->dev);
781 static void radeon_crtc_prepare(struct drm_crtc *crtc)
783 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
786 static void radeon_crtc_commit(struct drm_crtc *crtc)
788 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
791 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
792 .dpms = radeon_crtc_dpms,
793 .mode_fixup = radeon_crtc_mode_fixup,
794 .mode_set = radeon_crtc_mode_set,
795 .mode_set_base = radeon_crtc_set_base,
796 .prepare = radeon_crtc_prepare,
797 .commit = radeon_crtc_commit,
801 void radeon_legacy_init_crtc(struct drm_device *dev,
802 struct radeon_crtc *radeon_crtc)
804 if (radeon_crtc->crtc_id == 1)
805 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
806 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
809 void radeon_init_disp_bw_legacy(struct drm_device *dev,
810 struct drm_display_mode *mode1,
811 uint32_t pixel_bytes1,
812 struct drm_display_mode *mode2,
813 uint32_t pixel_bytes2)
815 struct radeon_device *rdev = dev->dev_private;
816 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
817 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
818 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
819 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
820 fixed20_12 memtcas_ff[8] = {
829 fixed20_12 memtcas_rs480_ff[8] = {
839 fixed20_12 memtcas2_ff[8] = {
849 fixed20_12 memtrbs[8] = {
859 fixed20_12 memtrbs_r4xx[8] = {
869 fixed20_12 min_mem_eff;
870 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
871 fixed20_12 cur_latency_mclk, cur_latency_sclk;
872 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
873 disp_drain_rate2, read_return_rate;
874 fixed20_12 time_disp1_drop_priority;
876 int cur_size = 16; /* in octawords */
877 int critical_point = 0, critical_point2;
878 /* uint32_t read_return_rate, time_disp1_drop_priority; */
879 int stop_req, max_stop_req;
881 min_mem_eff.full = rfixed_const_8(0);
883 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
884 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
885 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
886 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
887 /* check crtc enables */
889 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
891 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
892 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
896 * determine is there is enough bw for current mode
898 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
899 temp_ff.full = rfixed_const(100);
900 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
901 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
902 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
904 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
905 temp_ff.full = rfixed_const(temp);
906 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
910 peak_disp_bw.full = 0;
912 temp_ff.full = rfixed_const(1000);
913 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
914 pix_clk.full = rfixed_div(pix_clk, temp_ff);
915 temp_ff.full = rfixed_const(pixel_bytes1);
916 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
919 temp_ff.full = rfixed_const(1000);
920 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
921 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
922 temp_ff.full = rfixed_const(pixel_bytes2);
923 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
926 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
927 if (peak_disp_bw.full >= mem_bw.full) {
928 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
929 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
932 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
933 temp = RREG32(RADEON_MEM_TIMING_CNTL);
934 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
935 mem_trcd = ((temp >> 2) & 0x3) + 1;
936 mem_trp = ((temp & 0x3)) + 1;
937 mem_tras = ((temp & 0x70) >> 4) + 1;
938 } else if (rdev->family == CHIP_R300 ||
939 rdev->family == CHIP_R350) { /* r300, r350 */
940 mem_trcd = (temp & 0x7) + 1;
941 mem_trp = ((temp >> 8) & 0x7) + 1;
942 mem_tras = ((temp >> 11) & 0xf) + 4;
943 } else if (rdev->family == CHIP_RV350 ||
944 rdev->family <= CHIP_RV380) {
946 mem_trcd = (temp & 0x7) + 3;
947 mem_trp = ((temp >> 8) & 0x7) + 3;
948 mem_tras = ((temp >> 11) & 0xf) + 6;
949 } else if (rdev->family == CHIP_R420 ||
950 rdev->family == CHIP_R423 ||
951 rdev->family == CHIP_RV410) {
953 mem_trcd = (temp & 0xf) + 3;
956 mem_trp = ((temp >> 8) & 0xf) + 3;
959 mem_tras = ((temp >> 12) & 0x1f) + 6;
962 } else { /* RV200, R200 */
963 mem_trcd = (temp & 0x7) + 1;
964 mem_trp = ((temp >> 8) & 0x7) + 1;
965 mem_tras = ((temp >> 12) & 0xf) + 4;
968 trcd_ff.full = rfixed_const(mem_trcd);
969 trp_ff.full = rfixed_const(mem_trp);
970 tras_ff.full = rfixed_const(mem_tras);
972 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
973 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
974 data = (temp & (7 << 20)) >> 20;
975 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
976 if (rdev->family == CHIP_RS480) /* don't think rs400 */
977 tcas_ff = memtcas_rs480_ff[data];
979 tcas_ff = memtcas_ff[data];
981 tcas_ff = memtcas2_ff[data];
983 if (rdev->family == CHIP_RS400 ||
984 rdev->family == CHIP_RS480) {
985 /* extra cas latency stored in bits 23-25 0-4 clocks */
986 data = (temp >> 23) & 0x7;
988 tcas_ff.full += rfixed_const(data);
991 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
992 /* on the R300, Tcas is included in Trbs.
994 temp = RREG32(RADEON_MEM_CNTL);
995 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
997 if (R300_MEM_USE_CD_CH_ONLY & temp) {
998 temp = RREG32(R300_MC_IND_INDEX);
999 temp &= ~R300_MC_IND_ADDR_MASK;
1000 temp |= R300_MC_READ_CNTL_CD_mcind;
1001 WREG32(R300_MC_IND_INDEX, temp);
1002 temp = RREG32(R300_MC_IND_DATA);
1003 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
1005 temp = RREG32(R300_MC_READ_CNTL_AB);
1006 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
1009 temp = RREG32(R300_MC_READ_CNTL_AB);
1010 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
1012 if (rdev->family == CHIP_RV410 ||
1013 rdev->family == CHIP_R420 ||
1014 rdev->family == CHIP_R423)
1015 trbs_ff = memtrbs_r4xx[data];
1017 trbs_ff = memtrbs[data];
1018 tcas_ff.full += trbs_ff.full;
1021 sclk_eff_ff.full = sclk_ff.full;
1023 if (rdev->flags & RADEON_IS_AGP) {
1024 fixed20_12 agpmode_ff;
1025 agpmode_ff.full = rfixed_const(radeon_agpmode);
1026 temp_ff.full = rfixed_const_666(16);
1027 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
1029 /* TODO PCIE lanes may affect this - agpmode == 16?? */
1031 if (ASIC_IS_R300(rdev)) {
1032 sclk_delay_ff.full = rfixed_const(250);
1034 if ((rdev->family == CHIP_RV100) ||
1035 rdev->flags & RADEON_IS_IGP) {
1036 if (rdev->mc.vram_is_ddr)
1037 sclk_delay_ff.full = rfixed_const(41);
1039 sclk_delay_ff.full = rfixed_const(33);
1041 if (rdev->mc.vram_width == 128)
1042 sclk_delay_ff.full = rfixed_const(57);
1044 sclk_delay_ff.full = rfixed_const(41);
1048 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
1050 if (rdev->mc.vram_is_ddr) {
1051 if (rdev->mc.vram_width == 32) {
1052 k1.full = rfixed_const(40);
1055 k1.full = rfixed_const(20);
1059 k1.full = rfixed_const(40);
1063 temp_ff.full = rfixed_const(2);
1064 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
1065 temp_ff.full = rfixed_const(c);
1066 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
1067 temp_ff.full = rfixed_const(4);
1068 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
1069 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
1070 mc_latency_mclk.full += k1.full;
1072 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
1073 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
1076 HW cursor time assuming worst case of full size colour cursor.
1078 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1079 temp_ff.full += trcd_ff.full;
1080 if (temp_ff.full < tras_ff.full)
1081 temp_ff.full = tras_ff.full;
1082 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
1084 temp_ff.full = rfixed_const(cur_size);
1085 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
1087 Find the total latency for the display data.
1089 disp_latency_overhead.full = rfixed_const(80);
1090 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
1091 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
1092 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
1094 if (mc_latency_mclk.full > mc_latency_sclk.full)
1095 disp_latency.full = mc_latency_mclk.full;
1097 disp_latency.full = mc_latency_sclk.full;
1099 /* setup Max GRPH_STOP_REQ default value */
1100 if (ASIC_IS_RV100(rdev))
1101 max_stop_req = 0x5c;
1103 max_stop_req = 0x7c;
1107 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
1108 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
1110 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
1112 if (stop_req > max_stop_req)
1113 stop_req = max_stop_req;
1116 Find the drain rate of the display buffer.
1118 temp_ff.full = rfixed_const((16/pixel_bytes1));
1119 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
1122 Find the critical point of the display buffer.
1124 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
1125 crit_point_ff.full += rfixed_const_half(0);
1127 critical_point = rfixed_trunc(crit_point_ff);
1129 if (rdev->disp_priority == 2) {
1134 The critical point should never be above max_stop_req-4. Setting
1135 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
1137 if (max_stop_req - critical_point < 4)
1140 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
1141 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
1142 critical_point = 0x10;
1145 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
1146 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
1147 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
1148 temp &= ~(RADEON_GRPH_START_REQ_MASK);
1149 if ((rdev->family == CHIP_R350) &&
1150 (stop_req > 0x15)) {
1153 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
1154 temp |= RADEON_GRPH_BUFFER_SIZE;
1155 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
1156 RADEON_GRPH_CRITICAL_AT_SOF |
1157 RADEON_GRPH_STOP_CNTL);
1159 Write the result into the register.
1161 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
1162 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
1165 if ((rdev->family == CHIP_RS400) ||
1166 (rdev->family == CHIP_RS480)) {
1167 /* attempt to program RS400 disp regs correctly ??? */
1168 temp = RREG32(RS400_DISP1_REG_CNTL);
1169 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
1170 RS400_DISP1_STOP_REQ_LEVEL_MASK);
1171 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
1172 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
1173 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
1174 temp = RREG32(RS400_DMIF_MEM_CNTL1);
1175 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
1176 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
1177 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
1178 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
1179 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
1183 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
1184 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
1185 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
1190 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
1192 if (stop_req > max_stop_req)
1193 stop_req = max_stop_req;
1196 Find the drain rate of the display buffer.
1198 temp_ff.full = rfixed_const((16/pixel_bytes2));
1199 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
1201 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
1202 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
1203 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
1204 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
1205 if ((rdev->family == CHIP_R350) &&
1206 (stop_req > 0x15)) {
1209 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
1210 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
1211 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
1212 RADEON_GRPH_CRITICAL_AT_SOF |
1213 RADEON_GRPH_STOP_CNTL);
1215 if ((rdev->family == CHIP_RS100) ||
1216 (rdev->family == CHIP_RS200))
1217 critical_point2 = 0;
1219 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1220 temp_ff.full = rfixed_const(temp);
1221 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
1222 if (sclk_ff.full < temp_ff.full)
1223 temp_ff.full = sclk_ff.full;
1225 read_return_rate.full = temp_ff.full;
1228 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1229 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
1231 time_disp1_drop_priority.full = 0;
1233 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1234 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
1235 crit_point_ff.full += rfixed_const_half(0);
1237 critical_point2 = rfixed_trunc(crit_point_ff);
1239 if (rdev->disp_priority == 2) {
1240 critical_point2 = 0;
1243 if (max_stop_req - critical_point2 < 4)
1244 critical_point2 = 0;
1248 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
1249 /* some R300 cards have problem with this set to 0 */
1250 critical_point2 = 0x10;
1253 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
1254 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
1256 if ((rdev->family == CHIP_RS400) ||
1257 (rdev->family == CHIP_RS480)) {
1259 /* attempt to program RS400 disp2 regs correctly ??? */
1260 temp = RREG32(RS400_DISP2_REQ_CNTL1);
1261 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
1262 RS400_DISP2_STOP_REQ_LEVEL_MASK);
1263 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
1264 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
1265 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
1266 temp = RREG32(RS400_DISP2_REQ_CNTL2);
1267 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
1268 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
1269 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
1270 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
1271 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
1273 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
1274 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
1275 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
1276 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
1279 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
1280 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));