SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm_sarea.h"
  30 #include "radeon.h"
  31 #include "radeon_drm.h"
  32
  33
  34 /*
  35  * Driver load/unload
  36  */
  37 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  38 {
  39         struct radeon_device *rdev;
  40         int r;
  41
  42         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  43         if (rdev == NULL) {
  44                 return -ENOMEM;
  45         }
  46         dev->dev_private = (void *)rdev;
  47
  48         /* update BUS flag */
  49         if (drm_device_is_agp(dev)) {
  50                 flags |= RADEON_IS_AGP;
  51         } else if (drm_device_is_pcie(dev)) {
  52                 flags |= RADEON_IS_PCIE;
  53         } else {
  54                 flags |= RADEON_IS_PCI;
  55         }
  56
  57         /* radeon_device_init should report only fatal error
  58          * like memory allocation failure or iomapping failure,
  59          * or memory manager initialization failure, it must
  60          * properly initialize the GPU MC controller and permit
  61          * VRAM allocation
  62          */
  63         r = radeon_device_init(rdev, dev, dev->pdev, flags);
  64         if (r) {
  65                 DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  66                 return r;
  67         }
  68         /* Again modeset_init should fail only on fatal error
  69          * otherwise it should provide enough functionalities
  70          * for shadowfb to run
  71          */
  72         r = radeon_modeset_init(rdev);
  73         if (r) {
  74                 return r;
  75         }
  76         return 0;
  77 }
  78
  79 int radeon_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct radeon_device *rdev = dev->dev_private;
  82
  83         if (rdev == NULL)
  84                 return 0;
  85         radeon_modeset_fini(rdev);
  86         radeon_device_fini(rdev);
  87         kfree(rdev);
  88         dev->dev_private = NULL;
  89         return 0;
  90 }
  91
  92
  93 /*
  94  * Userspace get informations ioctl
  95  */
  96 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  97 {
  98         struct radeon_device *rdev = dev->dev_private;
  99         struct drm_radeon_info *info;
 100         uint32_t *value_ptr;
 101         uint32_t value;
 102
 103         info = data;
 104         value_ptr = (uint32_t *)((unsigned long)info->value);
 105         switch (info->request) {
 106         case RADEON_INFO_DEVICE_ID:
 107                 value = dev->pci_device;
 108                 break;
 109         case RADEON_INFO_NUM_GB_PIPES:
 110                 value = rdev->num_gb_pipes;
 111                 break;
 112         case RADEON_INFO_NUM_Z_PIPES:
 113                 value = rdev->num_z_pipes;
 114                 break;
 115         default:
 116                 DRM_DEBUG("Invalid request %d\n", info->request);
 117                 return -EINVAL;
 118         }
 119         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 120                 DRM_ERROR("copy_to_user\n");
 121                 return -EFAULT;
 122         }
 123         return 0;
 124 }
 125
 126
 127 /*
 128  * Outdated mess for old drm with Xorg being in charge (void function now).
 129  */
 130 int radeon_driver_firstopen_kms(struct drm_device *dev)
 131 {
 132         return 0;
 133 }
 134
 135
 136 void radeon_driver_lastclose_kms(struct drm_device *dev)
 137 {
 138 }
 139
 140 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 141 {
 142         return 0;
 143 }
 144
 145 void radeon_driver_postclose_kms(struct drm_device *dev,
 146                                  struct drm_file *file_priv)
 147 {
 148 }
 149
 150 void radeon_driver_preclose_kms(struct drm_device *dev,
 151                                 struct drm_file *file_priv)
 152 {
 153 }
 154
 155
 156 /*
 157  * VBlank related functions.
 158  */
 159 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 160 {
 161         struct radeon_device *rdev = dev->dev_private;
 162
 163         if (crtc < 0 || crtc > 1) {
 164                 DRM_ERROR("Invalid crtc %d\n", crtc);
 165                 return -EINVAL;
 166         }
 167
 168         return radeon_get_vblank_counter(rdev, crtc);
 169 }
 170
 171 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 172 {
 173         struct radeon_device *rdev = dev->dev_private;
 174
 175         if (crtc < 0 || crtc > 1) {
 176                 DRM_ERROR("Invalid crtc %d\n", crtc);
 177                 return -EINVAL;
 178         }
 179
 180         rdev->irq.crtc_vblank_int[crtc] = true;
 181
 182         return radeon_irq_set(rdev);
 183 }
 184
 185 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 186 {
 187         struct radeon_device *rdev = dev->dev_private;
 188
 189         if (crtc < 0 || crtc > 1) {
 190                 DRM_ERROR("Invalid crtc %d\n", crtc);
 191                 return;
 192         }
 193
 194         rdev->irq.crtc_vblank_int[crtc] = false;
 195
 196         radeon_irq_set(rdev);
 197 }
 198
 199
 200 /*
 201  * For multiple master (like multiple X).
 202  */
 203 struct drm_radeon_master_private {
 204         drm_local_map_t *sarea;
 205         drm_radeon_sarea_t *sarea_priv;
 206 };
 207
 208 int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master)
 209 {
 210         struct drm_radeon_master_private *master_priv;
 211         unsigned long sareapage;
 212         int ret;
 213
 214         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
 215         if (master_priv == NULL) {
 216                 return -ENOMEM;
 217         }
 218         /* prebuild the SAREA */
 219         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
 220         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM,
 221                          _DRM_CONTAINS_LOCK,
 222                          &master_priv->sarea);
 223         if (ret) {
 224                 DRM_ERROR("SAREA setup failed\n");
 225                 return ret;
 226         }
 227         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
 228         master_priv->sarea_priv->pfCurrentPage = 0;
 229         master->driver_priv = master_priv;
 230         return 0;
 231 }
 232
 233 void radeon_master_destroy_kms(struct drm_device *dev,
 234                                struct drm_master *master)
 235 {
 236         struct drm_radeon_master_private *master_priv = master->driver_priv;
 237
 238         if (master_priv == NULL) {
 239                 return;
 240         }
 241         if (master_priv->sarea) {
 242                 drm_rmmap_locked(dev, master_priv->sarea);
 243         }
 244         kfree(master_priv);
 245         master->driver_priv = NULL;
 246 }
 247
 248
 249 /*
 250  * IOCTL.
 251  */
 252 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 253                          struct drm_file *file_priv)
 254 {
 255         /* Not valid in KMS. */
 256         return -EINVAL;
 257 }
 258
 259 #define KMS_INVALID_IOCTL(name)                                         \
 260 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 261 {                                                                       \
 262         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 263         return -EINVAL;                                                 \
 264 }
 265
 266 /*
 267  * All these ioctls are invalid in kms world.
 268  */
 269 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 270 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 271 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 272 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 273 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 274 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 275 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 276 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 277 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 278 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 279 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 280 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 281 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 282 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 283 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 284 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 285 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 286 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 287 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 288 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 289 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 290 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 291 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 292 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 293 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 294 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 295 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 296
 297
 298 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 299         DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 300         DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 301         DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 302         DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 303         DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 304         DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 305         DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 306         DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 307         DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 308         DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 309         DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 310         DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 311         DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 312         DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 313         DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 314         DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 315         DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 316         DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 317         DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 318         DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 319         DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 320         DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 321         DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 322         DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 323         DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 324         DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 325         DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 326         /* KMS */
 327         DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH),
 328         DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH),
 329         DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH),
 330         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
 331         DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 332         DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 333         DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH),
 334         DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
 335         DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH),
 336         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH),
 337         DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH),
 338         DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH),
 339 };
 340 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);