SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_i2c.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29 #include "atom.h"
  30
  31 /**
  32  * radeon_ddc_probe
  33  *
  34  */
  35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
  36 {
  37         u8 out_buf[] = { 0x0, 0x0};
  38         u8 buf[2];
  39         int ret;
  40         struct i2c_msg msgs[] = {
  41                 {
  42                         .addr = 0x50,
  43                         .flags = 0,
  44                         .len = 1,
  45                         .buf = out_buf,
  46                 },
  47                 {
  48                         .addr = 0x50,
  49                         .flags = I2C_M_RD,
  50                         .len = 1,
  51                         .buf = buf,
  52                 }
  53         };
  54
  55         ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
  56         if (ret == 2)
  57                 return true;
  58
  59         return false;
  60 }
  61
  62
  63 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
  64 {
  65         struct radeon_device *rdev = i2c->dev->dev_private;
  66         struct radeon_i2c_bus_rec *rec = &i2c->rec;
  67         uint32_t temp;
  68
  69         /* RV410 appears to have a bug where the hw i2c in reset
  70          * holds the i2c port in a bad state - switch hw i2c away before
  71          * doing DDC - do this for all r200s/r300s/r400s for safety sake
  72          */
  73         if (rec->hw_capable) {
  74                 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
  75                         u32 reg;
  76
  77                         if (rdev->family >= CHIP_RV350)
  78                                 reg = RADEON_GPIO_MONID;
  79                         else if ((rdev->family == CHIP_R300) ||
  80                                  (rdev->family == CHIP_R350))
  81                                 reg = RADEON_GPIO_DVI_DDC;
  82                         else
  83                                 reg = RADEON_GPIO_CRT2_DDC;
  84
  85                         mutex_lock(&rdev->dc_hw_i2c_mutex);
  86                         if (rec->a_clk_reg == reg) {
  87                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
  88                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
  89                         } else {
  90                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
  91                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
  92                         }
  93                         mutex_unlock(&rdev->dc_hw_i2c_mutex);
  94                 }
  95         }
  96
  97         /* clear the output pin values */
  98         temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
  99         WREG32(rec->a_clk_reg, temp);
 100
 101         temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
 102         WREG32(rec->a_data_reg, temp);
 103
 104         /* set the pins to input */
 105         temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 106         WREG32(rec->en_clk_reg, temp);
 107
 108         temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 109         WREG32(rec->en_data_reg, temp);
 110
 111         /* mask the gpio pins for software use */
 112         temp = RREG32(rec->mask_clk_reg);
 113         if (lock_state)
 114                 temp |= rec->mask_clk_mask;
 115         else
 116                 temp &= ~rec->mask_clk_mask;
 117         WREG32(rec->mask_clk_reg, temp);
 118         temp = RREG32(rec->mask_clk_reg);
 119
 120         temp = RREG32(rec->mask_data_reg);
 121         if (lock_state)
 122                 temp |= rec->mask_data_mask;
 123         else
 124                 temp &= ~rec->mask_data_mask;
 125         WREG32(rec->mask_data_reg, temp);
 126         temp = RREG32(rec->mask_data_reg);
 127 }
 128
 129 static int get_clock(void *i2c_priv)
 130 {
 131         struct radeon_i2c_chan *i2c = i2c_priv;
 132         struct radeon_device *rdev = i2c->dev->dev_private;
 133         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 134         uint32_t val;
 135
 136         /* read the value off the pin */
 137         val = RREG32(rec->y_clk_reg);
 138         val &= rec->y_clk_mask;
 139
 140         return (val != 0);
 141 }
 142
 143
 144 static int get_data(void *i2c_priv)
 145 {
 146         struct radeon_i2c_chan *i2c = i2c_priv;
 147         struct radeon_device *rdev = i2c->dev->dev_private;
 148         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 149         uint32_t val;
 150
 151         /* read the value off the pin */
 152         val = RREG32(rec->y_data_reg);
 153         val &= rec->y_data_mask;
 154
 155         return (val != 0);
 156 }
 157
 158 static void set_clock(void *i2c_priv, int clock)
 159 {
 160         struct radeon_i2c_chan *i2c = i2c_priv;
 161         struct radeon_device *rdev = i2c->dev->dev_private;
 162         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 163         uint32_t val;
 164
 165         /* set pin direction */
 166         val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 167         val |= clock ? 0 : rec->en_clk_mask;
 168         WREG32(rec->en_clk_reg, val);
 169 }
 170
 171 static void set_data(void *i2c_priv, int data)
 172 {
 173         struct radeon_i2c_chan *i2c = i2c_priv;
 174         struct radeon_device *rdev = i2c->dev->dev_private;
 175         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 176         uint32_t val;
 177
 178         /* set pin direction */
 179         val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 180         val |= data ? 0 : rec->en_data_mask;
 181         WREG32(rec->en_data_reg, val);
 182 }
 183
 184 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
 185 {
 186         struct radeon_pll *spll = &rdev->clock.spll;
 187         u32 sclk = radeon_get_engine_clock(rdev);
 188         u32 prescale = 0;
 189         u32 n, m;
 190         u8 loop;
 191         int i2c_clock;
 192
 193         switch (rdev->family) {
 194         case CHIP_R100:
 195         case CHIP_RV100:
 196         case CHIP_RS100:
 197         case CHIP_RV200:
 198         case CHIP_RS200:
 199         case CHIP_R200:
 200         case CHIP_RV250:
 201         case CHIP_RS300:
 202         case CHIP_RV280:
 203         case CHIP_R300:
 204         case CHIP_R350:
 205         case CHIP_RV350:
 206                 n = (spll->reference_freq) / (4 * 6);
 207                 for (loop = 1; loop < 255; loop++) {
 208                         if ((loop * (loop - 1)) > n)
 209                                 break;
 210                 }
 211                 m = loop - 1;
 212                 prescale = m | (loop << 8);
 213                 break;
 214         case CHIP_RV380:
 215         case CHIP_RS400:
 216         case CHIP_RS480:
 217         case CHIP_R420:
 218         case CHIP_R423:
 219         case CHIP_RV410:
 220                 sclk = radeon_get_engine_clock(rdev);
 221                 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 222                 break;
 223         case CHIP_RS600:
 224         case CHIP_RS690:
 225         case CHIP_RS740:
 226                 /* todo */
 227                 break;
 228         case CHIP_RV515:
 229         case CHIP_R520:
 230         case CHIP_RV530:
 231         case CHIP_RV560:
 232         case CHIP_RV570:
 233         case CHIP_R580:
 234                 i2c_clock = 50;
 235                 sclk = radeon_get_engine_clock(rdev);
 236                 if (rdev->family == CHIP_R520)
 237                         prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
 238                 else
 239                         prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 240                 break;
 241         case CHIP_R600:
 242         case CHIP_RV610:
 243         case CHIP_RV630:
 244         case CHIP_RV670:
 245                 /* todo */
 246                 break;
 247         case CHIP_RV620:
 248         case CHIP_RV635:
 249         case CHIP_RS780:
 250         case CHIP_RS880:
 251         case CHIP_RV770:
 252         case CHIP_RV730:
 253         case CHIP_RV710:
 254         case CHIP_RV740:
 255                 /* todo */
 256                 break;
 257         default:
 258                 DRM_ERROR("i2c: unhandled radeon chip\n");
 259                 break;
 260         }
 261         return prescale;
 262 }
 263
 264
 265 /* hw i2c engine for r1xx-4xx hardware
 266  * hw can buffer up to 15 bytes
 267  */
 268 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 269                             struct i2c_msg *msgs, int num)
 270 {
 271         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 272         struct radeon_device *rdev = i2c->dev->dev_private;
 273         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 274         struct i2c_msg *p;
 275         int i, j, k, ret = num;
 276         u32 prescale;
 277         u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
 278         u32 tmp, reg;
 279
 280         mutex_lock(&rdev->dc_hw_i2c_mutex);
 281         /* take the pm lock since we need a constant sclk */
 282         mutex_lock(&rdev->pm.mutex);
 283
 284         prescale = radeon_get_i2c_prescale(rdev);
 285
 286         reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
 287                RADEON_I2C_START |
 288                RADEON_I2C_STOP |
 289                RADEON_I2C_GO);
 290
 291         if (rdev->is_atom_bios) {
 292                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 293                 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 294         }
 295
 296         if (rec->mm_i2c) {
 297                 i2c_cntl_0 = RADEON_I2C_CNTL_0;
 298                 i2c_cntl_1 = RADEON_I2C_CNTL_1;
 299                 i2c_data = RADEON_I2C_DATA;
 300         } else {
 301                 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
 302                 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
 303                 i2c_data = RADEON_DVI_I2C_DATA;
 304
 305                 switch (rdev->family) {
 306                 case CHIP_R100:
 307                 case CHIP_RV100:
 308                 case CHIP_RS100:
 309                 case CHIP_RV200:
 310                 case CHIP_RS200:
 311                 case CHIP_RS300:
 312                         switch (rec->mask_clk_reg) {
 313                         case RADEON_GPIO_DVI_DDC:
 314                                 /* no gpio select bit */
 315                                 break;
 316                         default:
 317                                 DRM_ERROR("gpio not supported with hw i2c\n");
 318                                 ret = -EINVAL;
 319                                 goto done;
 320                         }
 321                         break;
 322                 case CHIP_R200:
 323                         /* only bit 4 on r200 */
 324                         switch (rec->mask_clk_reg) {
 325                         case RADEON_GPIO_DVI_DDC:
 326                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 327                                 break;
 328                         case RADEON_GPIO_MONID:
 329                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 330                                 break;
 331                         default:
 332                                 DRM_ERROR("gpio not supported with hw i2c\n");
 333                                 ret = -EINVAL;
 334                                 goto done;
 335                         }
 336                         break;
 337                 case CHIP_RV250:
 338                 case CHIP_RV280:
 339                         /* bits 3 and 4 */
 340                         switch (rec->mask_clk_reg) {
 341                         case RADEON_GPIO_DVI_DDC:
 342                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 343                                 break;
 344                         case RADEON_GPIO_VGA_DDC:
 345                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 346                                 break;
 347                         case RADEON_GPIO_CRT2_DDC:
 348                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 349                                 break;
 350                         default:
 351                                 DRM_ERROR("gpio not supported with hw i2c\n");
 352                                 ret = -EINVAL;
 353                                 goto done;
 354                         }
 355                         break;
 356                 case CHIP_R300:
 357                 case CHIP_R350:
 358                         /* only bit 4 on r300/r350 */
 359                         switch (rec->mask_clk_reg) {
 360                         case RADEON_GPIO_VGA_DDC:
 361                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 362                                 break;
 363                         case RADEON_GPIO_DVI_DDC:
 364                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 365                                 break;
 366                         default:
 367                                 DRM_ERROR("gpio not supported with hw i2c\n");
 368                                 ret = -EINVAL;
 369                                 goto done;
 370                         }
 371                         break;
 372                 case CHIP_RV350:
 373                 case CHIP_RV380:
 374                 case CHIP_R420:
 375                 case CHIP_R423:
 376                 case CHIP_RV410:
 377                 case CHIP_RS400:
 378                 case CHIP_RS480:
 379                         /* bits 3 and 4 */
 380                         switch (rec->mask_clk_reg) {
 381                         case RADEON_GPIO_VGA_DDC:
 382                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 383                                 break;
 384                         case RADEON_GPIO_DVI_DDC:
 385                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 386                                 break;
 387                         case RADEON_GPIO_MONID:
 388                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 389                                 break;
 390                         default:
 391                                 DRM_ERROR("gpio not supported with hw i2c\n");
 392                                 ret = -EINVAL;
 393                                 goto done;
 394                         }
 395                         break;
 396                 default:
 397                         DRM_ERROR("unsupported asic\n");
 398                         ret = -EINVAL;
 399                         goto done;
 400                         break;
 401                 }
 402         }
 403
 404         /* check for bus probe */
 405         p = &msgs[0];
 406         if ((num == 1) && (p->len == 0)) {
 407                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 408                                     RADEON_I2C_NACK |
 409                                     RADEON_I2C_HALT |
 410                                     RADEON_I2C_SOFT_RST));
 411                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 412                 WREG32(i2c_data, 0);
 413                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 414                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 415                                     RADEON_I2C_EN |
 416                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 417                 WREG32(i2c_cntl_0, reg);
 418                 for (k = 0; k < 32; k++) {
 419                         udelay(10);
 420                         tmp = RREG32(i2c_cntl_0);
 421                         if (tmp & RADEON_I2C_GO)
 422                                 continue;
 423                         tmp = RREG32(i2c_cntl_0);
 424                         if (tmp & RADEON_I2C_DONE)
 425                                 break;
 426                         else {
 427                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 428                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 429                                 ret = -EIO;
 430                                 goto done;
 431                         }
 432                 }
 433                 goto done;
 434         }
 435
 436         for (i = 0; i < num; i++) {
 437                 p = &msgs[i];
 438                 for (j = 0; j < p->len; j++) {
 439                         if (p->flags & I2C_M_RD) {
 440                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 441                                                     RADEON_I2C_NACK |
 442                                                     RADEON_I2C_HALT |
 443                                                     RADEON_I2C_SOFT_RST));
 444                                 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
 445                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 446                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 447                                                     RADEON_I2C_EN |
 448                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 449                                 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
 450                                 for (k = 0; k < 32; k++) {
 451                                         udelay(10);
 452                                         tmp = RREG32(i2c_cntl_0);
 453                                         if (tmp & RADEON_I2C_GO)
 454                                                 continue;
 455                                         tmp = RREG32(i2c_cntl_0);
 456                                         if (tmp & RADEON_I2C_DONE)
 457                                                 break;
 458                                         else {
 459                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 460                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 461                                                 ret = -EIO;
 462                                                 goto done;
 463                                         }
 464                                 }
 465                                 p->buf[j] = RREG32(i2c_data) & 0xff;
 466                         } else {
 467                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 468                                                     RADEON_I2C_NACK |
 469                                                     RADEON_I2C_HALT |
 470                                                     RADEON_I2C_SOFT_RST));
 471                                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 472                                 WREG32(i2c_data, p->buf[j]);
 473                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 474                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 475                                                     RADEON_I2C_EN |
 476                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 477                                 WREG32(i2c_cntl_0, reg);
 478                                 for (k = 0; k < 32; k++) {
 479                                         udelay(10);
 480                                         tmp = RREG32(i2c_cntl_0);
 481                                         if (tmp & RADEON_I2C_GO)
 482                                                 continue;
 483                                         tmp = RREG32(i2c_cntl_0);
 484                                         if (tmp & RADEON_I2C_DONE)
 485                                                 break;
 486                                         else {
 487                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 488                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 489                                                 ret = -EIO;
 490                                                 goto done;
 491                                         }
 492                                 }
 493                         }
 494                 }
 495         }
 496
 497 done:
 498         WREG32(i2c_cntl_0, 0);
 499         WREG32(i2c_cntl_1, 0);
 500         WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 501                             RADEON_I2C_NACK |
 502                             RADEON_I2C_HALT |
 503                             RADEON_I2C_SOFT_RST));
 504
 505         if (rdev->is_atom_bios) {
 506                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 507                 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 508                 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 509         }
 510
 511         mutex_unlock(&rdev->pm.mutex);
 512         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 513
 514         return ret;
 515 }
 516
 517 /* hw i2c engine for r5xx hardware
 518  * hw can buffer up to 15 bytes
 519  */
 520 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 521                             struct i2c_msg *msgs, int num)
 522 {
 523         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 524         struct radeon_device *rdev = i2c->dev->dev_private;
 525         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 526         struct i2c_msg *p;
 527         int i, j, remaining, current_count, buffer_offset, ret = num;
 528         u32 prescale;
 529         u32 tmp, reg;
 530         u32 saved1, saved2;
 531
 532         mutex_lock(&rdev->dc_hw_i2c_mutex);
 533         /* take the pm lock since we need a constant sclk */
 534         mutex_lock(&rdev->pm.mutex);
 535
 536         prescale = radeon_get_i2c_prescale(rdev);
 537
 538         /* clear gpio mask bits */
 539         tmp = RREG32(rec->mask_clk_reg);
 540         tmp &= ~rec->mask_clk_mask;
 541         WREG32(rec->mask_clk_reg, tmp);
 542         tmp = RREG32(rec->mask_clk_reg);
 543
 544         tmp = RREG32(rec->mask_data_reg);
 545         tmp &= ~rec->mask_data_mask;
 546         WREG32(rec->mask_data_reg, tmp);
 547         tmp = RREG32(rec->mask_data_reg);
 548
 549         /* clear pin values */
 550         tmp = RREG32(rec->a_clk_reg);
 551         tmp &= ~rec->a_clk_mask;
 552         WREG32(rec->a_clk_reg, tmp);
 553         tmp = RREG32(rec->a_clk_reg);
 554
 555         tmp = RREG32(rec->a_data_reg);
 556         tmp &= ~rec->a_data_mask;
 557         WREG32(rec->a_data_reg, tmp);
 558         tmp = RREG32(rec->a_data_reg);
 559
 560         /* set the pins to input */
 561         tmp = RREG32(rec->en_clk_reg);
 562         tmp &= ~rec->en_clk_mask;
 563         WREG32(rec->en_clk_reg, tmp);
 564         tmp = RREG32(rec->en_clk_reg);
 565
 566         tmp = RREG32(rec->en_data_reg);
 567         tmp &= ~rec->en_data_mask;
 568         WREG32(rec->en_data_reg, tmp);
 569         tmp = RREG32(rec->en_data_reg);
 570
 571         /* */
 572         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 573         WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 574         saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
 575         saved2 = RREG32(0x494);
 576         WREG32(0x494, saved2 | 0x1);
 577
 578         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
 579         for (i = 0; i < 50; i++) {
 580                 udelay(1);
 581                 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
 582                         break;
 583         }
 584         if (i == 50) {
 585                 DRM_ERROR("failed to get i2c bus\n");
 586                 ret = -EBUSY;
 587                 goto done;
 588         }
 589
 590         reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
 591         switch (rec->mask_clk_reg) {
 592         case AVIVO_DC_GPIO_DDC1_MASK:
 593                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
 594                 break;
 595         case AVIVO_DC_GPIO_DDC2_MASK:
 596                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
 597                 break;
 598         case AVIVO_DC_GPIO_DDC3_MASK:
 599                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
 600                 break;
 601         default:
 602                 DRM_ERROR("gpio not supported with hw i2c\n");
 603                 ret = -EINVAL;
 604                 goto done;
 605         }
 606
 607         /* check for bus probe */
 608         p = &msgs[0];
 609         if ((num == 1) && (p->len == 0)) {
 610                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 611                                               AVIVO_DC_I2C_NACK |
 612                                               AVIVO_DC_I2C_HALT));
 613                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 614                 udelay(1);
 615                 WREG32(AVIVO_DC_I2C_RESET, 0);
 616
 617                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 618                 WREG32(AVIVO_DC_I2C_DATA, 0);
 619
 620                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 621                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 622                                                AVIVO_DC_I2C_DATA_COUNT(1) |
 623                                                (prescale << 16)));
 624                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 625                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 626                 for (j = 0; j < 200; j++) {
 627                         udelay(50);
 628                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 629                         if (tmp & AVIVO_DC_I2C_GO)
 630                                 continue;
 631                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 632                         if (tmp & AVIVO_DC_I2C_DONE)
 633                                 break;
 634                         else {
 635                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 636                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 637                                 ret = -EIO;
 638                                 goto done;
 639                         }
 640                 }
 641                 goto done;
 642         }
 643
 644         for (i = 0; i < num; i++) {
 645                 p = &msgs[i];
 646                 remaining = p->len;
 647                 buffer_offset = 0;
 648                 if (p->flags & I2C_M_RD) {
 649                         while (remaining) {
 650                                 if (remaining > 15)
 651                                         current_count = 15;
 652                                 else
 653                                         current_count = remaining;
 654                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 655                                                               AVIVO_DC_I2C_NACK |
 656                                                               AVIVO_DC_I2C_HALT));
 657                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 658                                 udelay(1);
 659                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 660
 661                                 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
 662                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 663                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 664                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 665                                                                (prescale << 16)));
 666                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
 667                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 668                                 for (j = 0; j < 200; j++) {
 669                                         udelay(50);
 670                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 671                                         if (tmp & AVIVO_DC_I2C_GO)
 672                                                 continue;
 673                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 674                                         if (tmp & AVIVO_DC_I2C_DONE)
 675                                                 break;
 676                                         else {
 677                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 678                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 679                                                 ret = -EIO;
 680                                                 goto done;
 681                                         }
 682                                 }
 683                                 for (j = 0; j < current_count; j++)
 684                                         p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
 685                                 remaining -= current_count;
 686                                 buffer_offset += current_count;
 687                         }
 688                 } else {
 689                         while (remaining) {
 690                                 if (remaining > 15)
 691                                         current_count = 15;
 692                                 else
 693                                         current_count = remaining;
 694                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 695                                                               AVIVO_DC_I2C_NACK |
 696                                                               AVIVO_DC_I2C_HALT));
 697                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 698                                 udelay(1);
 699                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 700
 701                                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 702                                 for (j = 0; j < current_count; j++)
 703                                         WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
 704
 705                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 706                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 707                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 708                                                                (prescale << 16)));
 709                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 710                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 711                                 for (j = 0; j < 200; j++) {
 712                                         udelay(50);
 713                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 714                                         if (tmp & AVIVO_DC_I2C_GO)
 715                                                 continue;
 716                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 717                                         if (tmp & AVIVO_DC_I2C_DONE)
 718                                                 break;
 719                                         else {
 720                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 721                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 722                                                 ret = -EIO;
 723                                                 goto done;
 724                                         }
 725                                 }
 726                                 remaining -= current_count;
 727                                 buffer_offset += current_count;
 728                         }
 729                 }
 730         }
 731
 732 done:
 733         WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 734                                       AVIVO_DC_I2C_NACK |
 735                                       AVIVO_DC_I2C_HALT));
 736         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 737         udelay(1);
 738         WREG32(AVIVO_DC_I2C_RESET, 0);
 739
 740         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
 741         WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
 742         WREG32(0x494, saved2);
 743         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 744         tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 745         WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 746
 747         mutex_unlock(&rdev->pm.mutex);
 748         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 749
 750         return ret;
 751 }
 752
 753 static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
 754                               struct i2c_msg *msgs, int num)
 755 {
 756         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 757         int ret;
 758
 759         radeon_i2c_do_lock(i2c, 1);
 760         ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
 761         radeon_i2c_do_lock(i2c, 0);
 762
 763         return ret;
 764 }
 765
 766 static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
 767                            struct i2c_msg *msgs, int num)
 768 {
 769         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 770         struct radeon_device *rdev = i2c->dev->dev_private;
 771         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 772         int ret;
 773
 774         switch (rdev->family) {
 775         case CHIP_R100:
 776         case CHIP_RV100:
 777         case CHIP_RS100:
 778         case CHIP_RV200:
 779         case CHIP_RS200:
 780         case CHIP_R200:
 781         case CHIP_RV250:
 782         case CHIP_RS300:
 783         case CHIP_RV280:
 784         case CHIP_R300:
 785         case CHIP_R350:
 786         case CHIP_RV350:
 787         case CHIP_RV380:
 788         case CHIP_R420:
 789         case CHIP_R423:
 790         case CHIP_RV410:
 791         case CHIP_RS400:
 792         case CHIP_RS480:
 793                 if (rec->hw_capable)
 794                         ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 795                 else
 796                         ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 797                 break;
 798         case CHIP_RS600:
 799         case CHIP_RS690:
 800         case CHIP_RS740:
 801                 /* XXX fill in hw i2c implementation */
 802                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 803                 break;
 804         case CHIP_RV515:
 805         case CHIP_R520:
 806         case CHIP_RV530:
 807         case CHIP_RV560:
 808         case CHIP_RV570:
 809         case CHIP_R580:
 810                 if (rec->hw_capable) {
 811                         if (rec->mm_i2c)
 812                                 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 813                         else
 814                                 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
 815                 } else
 816                         ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 817                 break;
 818         case CHIP_R600:
 819         case CHIP_RV610:
 820         case CHIP_RV630:
 821         case CHIP_RV670:
 822                 /* XXX fill in hw i2c implementation */
 823                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 824                 break;
 825         case CHIP_RV620:
 826         case CHIP_RV635:
 827         case CHIP_RS780:
 828         case CHIP_RS880:
 829         case CHIP_RV770:
 830         case CHIP_RV730:
 831         case CHIP_RV710:
 832         case CHIP_RV740:
 833                 /* XXX fill in hw i2c implementation */
 834                 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
 835                 break;
 836         default:
 837                 DRM_ERROR("i2c: unhandled radeon chip\n");
 838                 ret = -EIO;
 839                 break;
 840         }
 841
 842         return ret;
 843 }
 844
 845 static u32 radeon_i2c_func(struct i2c_adapter *adap)
 846 {
 847         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 848 }
 849
 850 static const struct i2c_algorithm radeon_i2c_algo = {
 851         .master_xfer = radeon_i2c_xfer,
 852         .functionality = radeon_i2c_func,
 853 };
 854
 855 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 856                                           struct radeon_i2c_bus_rec *rec,
 857                                           const char *name)
 858 {
 859         struct radeon_i2c_chan *i2c;
 860         int ret;
 861
 862         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 863         if (i2c == NULL)
 864                 return NULL;
 865
 866         /* set the internal bit adapter */
 867         i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
 868         i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
 869         sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
 870         i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
 871         i2c->algo.radeon.bit_data.setsda = set_data;
 872         i2c->algo.radeon.bit_data.setscl = set_clock;
 873         i2c->algo.radeon.bit_data.getsda = get_data;
 874         i2c->algo.radeon.bit_data.getscl = get_clock;
 875         i2c->algo.radeon.bit_data.udelay = 20;
 876         /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
 877          * make this, 2 jiffies is a lot more reliable */
 878         i2c->algo.radeon.bit_data.timeout = 2;
 879         i2c->algo.radeon.bit_data.data = i2c;
 880         ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
 881         if (ret) {
 882                 DRM_ERROR("Failed to register internal bit i2c %s\n", name);
 883                 goto out_free;
 884         }
 885         /* set the radeon i2c adapter */
 886         i2c->dev = dev;
 887         i2c->rec = *rec;
 888         i2c->adapter.owner = THIS_MODULE;
 889         i2c_set_adapdata(&i2c->adapter, i2c);
 890         sprintf(i2c->adapter.name, "Radeon i2c %s", name);
 891         i2c->adapter.algo_data = &i2c->algo.radeon;
 892         i2c->adapter.algo = &radeon_i2c_algo;
 893         ret = i2c_add_adapter(&i2c->adapter);
 894         if (ret) {
 895                 DRM_ERROR("Failed to register i2c %s\n", name);
 896                 goto out_free;
 897         }
 898
 899         return i2c;
 900 out_free:
 901         kfree(i2c);
 902         return NULL;
 903
 904 }
 905
 906 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 907                                              struct radeon_i2c_bus_rec *rec,
 908                                              const char *name)
 909 {
 910         struct radeon_i2c_chan *i2c;
 911         int ret;
 912
 913         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 914         if (i2c == NULL)
 915                 return NULL;
 916
 917         i2c->rec = *rec;
 918         i2c->adapter.owner = THIS_MODULE;
 919         i2c->dev = dev;
 920         i2c_set_adapdata(&i2c->adapter, i2c);
 921         i2c->adapter.algo_data = &i2c->algo.dp;
 922         i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
 923         i2c->algo.dp.address = 0;
 924         ret = i2c_dp_aux_add_bus(&i2c->adapter);
 925         if (ret) {
 926                 DRM_INFO("Failed to register i2c %s\n", name);
 927                 goto out_free;
 928         }
 929
 930         return i2c;
 931 out_free:
 932         kfree(i2c);
 933         return NULL;
 934
 935 }
 936
 937 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 938 {
 939         if (!i2c)
 940                 return;
 941         i2c_del_adapter(&i2c->algo.radeon.bit_adapter);
 942         i2c_del_adapter(&i2c->adapter);
 943         kfree(i2c);
 944 }
 945
 946 void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
 947 {
 948         if (!i2c)
 949                 return;
 950
 951         i2c_del_adapter(&i2c->adapter);
 952         kfree(i2c);
 953 }
 954
 955 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
 956 {
 957         return NULL;
 958 }
 959
 960 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 961                          u8 slave_addr,
 962                          u8 addr,
 963                          u8 *val)
 964 {
 965         u8 out_buf[2];
 966         u8 in_buf[2];
 967         struct i2c_msg msgs[] = {
 968                 {
 969                         .addr = slave_addr,
 970                         .flags = 0,
 971                         .len = 1,
 972                         .buf = out_buf,
 973                 },
 974                 {
 975                         .addr = slave_addr,
 976                         .flags = I2C_M_RD,
 977                         .len = 1,
 978                         .buf = in_buf,
 979                 }
 980         };
 981
 982         out_buf[0] = addr;
 983         out_buf[1] = 0;
 984
 985         if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
 986                 *val = in_buf[0];
 987                 DRM_DEBUG("val = 0x%02x\n", *val);
 988         } else {
 989                 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
 990                           addr, *val);
 991         }
 992 }
 993
 994 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
 995                          u8 slave_addr,
 996                          u8 addr,
 997                          u8 val)
 998 {
 999         uint8_t out_buf[2];
1000         struct i2c_msg msg = {
1001                 .addr = slave_addr,
1002                 .flags = 0,
1003                 .len = 2,
1004                 .buf = out_buf,
1005         };
1006
1007         out_buf[0] = addr;
1008         out_buf[1] = val;
1009
1010         if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1011                 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
1012                           addr, val);
1013 }
1014