SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 uint32_t
  39 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  40 {
  41         struct radeon_device *rdev = dev->dev_private;
  42         uint32_t ret = 0;
  43
  44         switch (supported_device) {
  45         case ATOM_DEVICE_CRT1_SUPPORT:
  46         case ATOM_DEVICE_TV1_SUPPORT:
  47         case ATOM_DEVICE_TV2_SUPPORT:
  48         case ATOM_DEVICE_CRT2_SUPPORT:
  49         case ATOM_DEVICE_CV_SUPPORT:
  50                 switch (dac) {
  51                 case 1: /* dac a */
  52                         if ((rdev->family == CHIP_RS300) ||
  53                             (rdev->family == CHIP_RS400) ||
  54                             (rdev->family == CHIP_RS480))
  55                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
  56                         else if (ASIC_IS_AVIVO(rdev))
  57                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
  58                         else
  59                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
  60                         break;
  61                 case 2: /* dac b */
  62                         if (ASIC_IS_AVIVO(rdev))
  63                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
  64                         else {
  65                                 /*if (rdev->family == CHIP_R200)
  66                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
  67                                   else*/
  68                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
  69                         }
  70                         break;
  71                 case 3: /* external dac */
  72                         if (ASIC_IS_AVIVO(rdev))
  73                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
  74                         else
  75                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
  76                         break;
  77                 }
  78                 break;
  79         case ATOM_DEVICE_LCD1_SUPPORT:
  80                 if (ASIC_IS_AVIVO(rdev))
  81                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
  82                 else
  83                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
  84                 break;
  85         case ATOM_DEVICE_DFP1_SUPPORT:
  86                 if ((rdev->family == CHIP_RS300) ||
  87                     (rdev->family == CHIP_RS400) ||
  88                     (rdev->family == CHIP_RS480))
  89                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
  90                 else if (ASIC_IS_AVIVO(rdev))
  91                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
  92                 else
  93                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
  94                 break;
  95         case ATOM_DEVICE_LCD2_SUPPORT:
  96         case ATOM_DEVICE_DFP2_SUPPORT:
  97                 if ((rdev->family == CHIP_RS600) ||
  98                     (rdev->family == CHIP_RS690) ||
  99                     (rdev->family == CHIP_RS740))
 100                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 101                 else if (ASIC_IS_AVIVO(rdev))
 102                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 103                 else
 104                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 105                 break;
 106         case ATOM_DEVICE_DFP3_SUPPORT:
 107                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 108                 break;
 109         }
 110
 111         return ret;
 112 }
 113
 114 void
 115 radeon_link_encoder_connector(struct drm_device *dev)
 116 {
 117         struct drm_connector *connector;
 118         struct radeon_connector *radeon_connector;
 119         struct drm_encoder *encoder;
 120         struct radeon_encoder *radeon_encoder;
 121
 122         /* walk the list and link encoders to connectors */
 123         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 124                 radeon_connector = to_radeon_connector(connector);
 125                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 126                         radeon_encoder = to_radeon_encoder(encoder);
 127                         if (radeon_encoder->devices & radeon_connector->devices)
 128                                 drm_mode_connector_attach_encoder(connector, encoder);
 129                 }
 130         }
 131 }
 132
 133 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 134 {
 135         struct drm_device *dev = encoder->dev;
 136         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 137         struct drm_connector *connector;
 138
 139         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 140                 if (connector->encoder == encoder) {
 141                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 142                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 143                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 144                                   radeon_encoder->active_device, radeon_encoder->devices,
 145                                   radeon_connector->devices, encoder->encoder_type);
 146                 }
 147         }
 148 }
 149
 150 static struct drm_connector *
 151 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 152 {
 153         struct drm_device *dev = encoder->dev;
 154         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 155         struct drm_connector *connector;
 156         struct radeon_connector *radeon_connector;
 157
 158         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 159                 radeon_connector = to_radeon_connector(connector);
 160                 if (radeon_encoder->devices & radeon_connector->devices)
 161                         return connector;
 162         }
 163         return NULL;
 164 }
 165
 166 /* used for both atom and legacy */
 167 void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
 168                            struct drm_display_mode *mode,
 169                            struct drm_display_mode *adjusted_mode)
 170 {
 171         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 172         struct drm_device *dev = encoder->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 175
 176         if (mode->hdisplay < native_mode->hdisplay ||
 177             mode->vdisplay < native_mode->vdisplay) {
 178                 *adjusted_mode = *native_mode;
 179                 if (!ASIC_IS_AVIVO(rdev)) {
 180                         adjusted_mode->hdisplay = mode->hdisplay;
 181                         adjusted_mode->vdisplay = mode->vdisplay;
 182                 }
 183         }
 184 }
 185
 186
 187 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 188                                    struct drm_display_mode *mode,
 189                                    struct drm_display_mode *adjusted_mode)
 190 {
 191         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 192         struct drm_device *dev = encoder->dev;
 193         struct radeon_device *rdev = dev->dev_private;
 194
 195         drm_mode_set_crtcinfo(adjusted_mode, 0);
 196
 197         if (radeon_encoder->rmx_type != RMX_OFF)
 198                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 199
 200         /* hw bug */
 201         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 202             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 203                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 204
 205         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 206                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 207                 if (tv_dac) {
 208                         if (tv_dac->tv_std == TV_STD_NTSC ||
 209                             tv_dac->tv_std == TV_STD_NTSC_J ||
 210                             tv_dac->tv_std == TV_STD_PAL_M)
 211                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 212                         else
 213                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 214                 }
 215         }
 216
 217         return true;
 218 }
 219
 220 static void
 221 atombios_dac_setup(struct drm_encoder *encoder, int action)
 222 {
 223         struct drm_device *dev = encoder->dev;
 224         struct radeon_device *rdev = dev->dev_private;
 225         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 226         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 227         int index = 0, num = 0;
 228         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 229         enum radeon_tv_std tv_std = TV_STD_NTSC;
 230
 231         if (dac_info->tv_std)
 232                 tv_std = dac_info->tv_std;
 233
 234         memset(&args, 0, sizeof(args));
 235
 236         switch (radeon_encoder->encoder_id) {
 237         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 238         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 239                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 240                 num = 1;
 241                 break;
 242         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 243         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 244                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 245                 num = 2;
 246                 break;
 247         }
 248
 249         args.ucAction = action;
 250
 251         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 252                 args.ucDacStandard = ATOM_DAC1_PS2;
 253         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 254                 args.ucDacStandard = ATOM_DAC1_CV;
 255         else {
 256                 switch (tv_std) {
 257                 case TV_STD_PAL:
 258                 case TV_STD_PAL_M:
 259                 case TV_STD_SCART_PAL:
 260                 case TV_STD_SECAM:
 261                 case TV_STD_PAL_CN:
 262                         args.ucDacStandard = ATOM_DAC1_PAL;
 263                         break;
 264                 case TV_STD_NTSC:
 265                 case TV_STD_NTSC_J:
 266                 case TV_STD_PAL_60:
 267                 default:
 268                         args.ucDacStandard = ATOM_DAC1_NTSC;
 269                         break;
 270                 }
 271         }
 272         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 273
 274         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 275
 276 }
 277
 278 static void
 279 atombios_tv_setup(struct drm_encoder *encoder, int action)
 280 {
 281         struct drm_device *dev = encoder->dev;
 282         struct radeon_device *rdev = dev->dev_private;
 283         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 284         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 285         int index = 0;
 286         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 287         enum radeon_tv_std tv_std = TV_STD_NTSC;
 288
 289         if (dac_info->tv_std)
 290                 tv_std = dac_info->tv_std;
 291
 292         memset(&args, 0, sizeof(args));
 293
 294         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 295
 296         args.sTVEncoder.ucAction = action;
 297
 298         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 299                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 300         else {
 301                 switch (tv_std) {
 302                 case TV_STD_NTSC:
 303                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 304                         break;
 305                 case TV_STD_PAL:
 306                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 307                         break;
 308                 case TV_STD_PAL_M:
 309                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 310                         break;
 311                 case TV_STD_PAL_60:
 312                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 313                         break;
 314                 case TV_STD_NTSC_J:
 315                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 316                         break;
 317                 case TV_STD_SCART_PAL:
 318                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 319                         break;
 320                 case TV_STD_SECAM:
 321                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 322                         break;
 323                 case TV_STD_PAL_CN:
 324                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 325                         break;
 326                 default:
 327                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 328                         break;
 329                 }
 330         }
 331
 332         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 333
 334         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 335
 336 }
 337
 338 void
 339 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 340 {
 341         struct drm_device *dev = encoder->dev;
 342         struct radeon_device *rdev = dev->dev_private;
 343         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 344         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 345         int index = 0;
 346
 347         memset(&args, 0, sizeof(args));
 348
 349         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 350
 351         args.sXTmdsEncoder.ucEnable = action;
 352
 353         if (radeon_encoder->pixel_clock > 165000)
 354                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 355
 356         /*if (pScrn->rgbBits == 8)*/
 357         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 358
 359         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 360
 361 }
 362
 363 static void
 364 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 365 {
 366         struct drm_device *dev = encoder->dev;
 367         struct radeon_device *rdev = dev->dev_private;
 368         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 369         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 370         int index = 0;
 371
 372         memset(&args, 0, sizeof(args));
 373
 374         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 375
 376         args.sDVOEncoder.ucAction = action;
 377         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 378
 379         if (radeon_encoder->pixel_clock > 165000)
 380                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 381
 382         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 383
 384 }
 385
 386 union lvds_encoder_control {
 387         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 388         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 389 };
 390
 391 static void
 392 atombios_digital_setup(struct drm_encoder *encoder, int action)
 393 {
 394         struct drm_device *dev = encoder->dev;
 395         struct radeon_device *rdev = dev->dev_private;
 396         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 397         union lvds_encoder_control args;
 398         int index = 0;
 399         uint8_t frev, crev;
 400         struct radeon_encoder_atom_dig *dig;
 401         struct drm_connector *connector;
 402         struct radeon_connector *radeon_connector;
 403         struct radeon_connector_atom_dig *dig_connector;
 404
 405         connector = radeon_get_connector_for_encoder(encoder);
 406         if (!connector)
 407                 return;
 408
 409         radeon_connector = to_radeon_connector(connector);
 410
 411         if (!radeon_encoder->enc_priv)
 412                 return;
 413
 414         dig = radeon_encoder->enc_priv;
 415
 416         if (!radeon_connector->con_priv)
 417                 return;
 418
 419         dig_connector = radeon_connector->con_priv;
 420
 421         memset(&args, 0, sizeof(args));
 422
 423         switch (radeon_encoder->encoder_id) {
 424         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 425                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 426                 break;
 427         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 428         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 429                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 430                 break;
 431         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 432                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 433                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 434                 else
 435                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 436                 break;
 437         }
 438
 439         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 440
 441         switch (frev) {
 442         case 1:
 443         case 2:
 444                 switch (crev) {
 445                 case 1:
 446                         args.v1.ucMisc = 0;
 447                         args.v1.ucAction = action;
 448                         if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 449                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 450                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 451                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 452                                 if (dig->lvds_misc & (1 << 0))
 453                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 454                                 if (dig->lvds_misc & (1 << 1))
 455                                         args.v1.ucMisc |= (1 << 1);
 456                         } else {
 457                                 if (dig_connector->linkb)
 458                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 459                                 if (radeon_encoder->pixel_clock > 165000)
 460                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 461                                 /*if (pScrn->rgbBits == 8) */
 462                                 args.v1.ucMisc |= (1 << 1);
 463                         }
 464                         break;
 465                 case 2:
 466                 case 3:
 467                         args.v2.ucMisc = 0;
 468                         args.v2.ucAction = action;
 469                         if (crev == 3) {
 470                                 if (dig->coherent_mode)
 471                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 472                         }
 473                         if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 474                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 475                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 476                         args.v2.ucTruncate = 0;
 477                         args.v2.ucSpatial = 0;
 478                         args.v2.ucTemporal = 0;
 479                         args.v2.ucFRC = 0;
 480                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 481                                 if (dig->lvds_misc & (1 << 0))
 482                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 483                                 if (dig->lvds_misc & (1 << 5)) {
 484                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 485                                         if (dig->lvds_misc & (1 << 1))
 486                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 487                                 }
 488                                 if (dig->lvds_misc & (1 << 6)) {
 489                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 490                                         if (dig->lvds_misc & (1 << 1))
 491                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 492                                         if (((dig->lvds_misc >> 2) & 0x3) == 2)
 493                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 494                                 }
 495                         } else {
 496                                 if (dig_connector->linkb)
 497                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 498                                 if (radeon_encoder->pixel_clock > 165000)
 499                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 500                         }
 501                         break;
 502                 default:
 503                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 504                         break;
 505                 }
 506                 break;
 507         default:
 508                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 509                 break;
 510         }
 511
 512         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 513
 514 }
 515
 516 int
 517 atombios_get_encoder_mode(struct drm_encoder *encoder)
 518 {
 519         struct drm_connector *connector;
 520         struct radeon_connector *radeon_connector;
 521
 522         connector = radeon_get_connector_for_encoder(encoder);
 523         if (!connector)
 524                 return 0;
 525
 526         radeon_connector = to_radeon_connector(connector);
 527
 528         switch (connector->connector_type) {
 529         case DRM_MODE_CONNECTOR_DVII:
 530         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 531                 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 532                         return ATOM_ENCODER_MODE_HDMI;
 533                 else if (radeon_connector->use_digital)
 534                         return ATOM_ENCODER_MODE_DVI;
 535                 else
 536                         return ATOM_ENCODER_MODE_CRT;
 537                 break;
 538         case DRM_MODE_CONNECTOR_DVID:
 539         case DRM_MODE_CONNECTOR_HDMIA:
 540         default:
 541                 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 542                         return ATOM_ENCODER_MODE_HDMI;
 543                 else
 544                         return ATOM_ENCODER_MODE_DVI;
 545                 break;
 546         case DRM_MODE_CONNECTOR_LVDS:
 547                 return ATOM_ENCODER_MODE_LVDS;
 548                 break;
 549         case DRM_MODE_CONNECTOR_DisplayPort:
 550                 /*if (radeon_output->MonType == MT_DP)
 551                   return ATOM_ENCODER_MODE_DP;
 552                   else*/
 553                 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 554                         return ATOM_ENCODER_MODE_HDMI;
 555                 else
 556                         return ATOM_ENCODER_MODE_DVI;
 557                 break;
 558         case CONNECTOR_DVI_A:
 559         case CONNECTOR_VGA:
 560                 return ATOM_ENCODER_MODE_CRT;
 561                 break;
 562         case CONNECTOR_STV:
 563         case CONNECTOR_CTV:
 564         case CONNECTOR_DIN:
 565                 /* fix me */
 566                 return ATOM_ENCODER_MODE_TV;
 567                 /*return ATOM_ENCODER_MODE_CV;*/
 568                 break;
 569         }
 570 }
 571
 572 static void
 573 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 574 {
 575         struct drm_device *dev = encoder->dev;
 576         struct radeon_device *rdev = dev->dev_private;
 577         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 578         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 579         int index = 0, num = 0;
 580         uint8_t frev, crev;
 581         struct radeon_encoder_atom_dig *dig;
 582         struct drm_connector *connector;
 583         struct radeon_connector *radeon_connector;
 584         struct radeon_connector_atom_dig *dig_connector;
 585
 586         connector = radeon_get_connector_for_encoder(encoder);
 587         if (!connector)
 588                 return;
 589
 590         radeon_connector = to_radeon_connector(connector);
 591
 592         if (!radeon_connector->con_priv)
 593                 return;
 594
 595         dig_connector = radeon_connector->con_priv;
 596
 597         if (!radeon_encoder->enc_priv)
 598                 return;
 599
 600         dig = radeon_encoder->enc_priv;
 601
 602         memset(&args, 0, sizeof(args));
 603
 604         if (ASIC_IS_DCE32(rdev)) {
 605                 if (dig->dig_block)
 606                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 607                 else
 608                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 609                 num = dig->dig_block + 1;
 610         } else {
 611                 switch (radeon_encoder->encoder_id) {
 612                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 613                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 614                         num = 1;
 615                         break;
 616                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 617                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 618                         num = 2;
 619                         break;
 620                 }
 621         }
 622
 623         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 624
 625         args.ucAction = action;
 626         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 627
 628         if (ASIC_IS_DCE32(rdev)) {
 629                 switch (radeon_encoder->encoder_id) {
 630                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 631                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 632                         break;
 633                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 634                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 635                         break;
 636                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 637                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 638                         break;
 639                 }
 640         } else {
 641                 switch (radeon_encoder->encoder_id) {
 642                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 643                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 644                         break;
 645                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 646                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 647                         break;
 648                 }
 649         }
 650
 651         if (radeon_encoder->pixel_clock > 165000) {
 652                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
 653                 args.ucLaneNum = 8;
 654         } else {
 655                 if (dig_connector->linkb)
 656                         args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 657                 else
 658                         args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 659                 args.ucLaneNum = 4;
 660         }
 661
 662         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 663
 664         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 665
 666 }
 667
 668 union dig_transmitter_control {
 669         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 670         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 671 };
 672
 673 static void
 674 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
 675 {
 676         struct drm_device *dev = encoder->dev;
 677         struct radeon_device *rdev = dev->dev_private;
 678         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 679         union dig_transmitter_control args;
 680         int index = 0, num = 0;
 681         uint8_t frev, crev;
 682         struct radeon_encoder_atom_dig *dig;
 683         struct drm_connector *connector;
 684         struct radeon_connector *radeon_connector;
 685         struct radeon_connector_atom_dig *dig_connector;
 686
 687         connector = radeon_get_connector_for_encoder(encoder);
 688         if (!connector)
 689                 return;
 690
 691         radeon_connector = to_radeon_connector(connector);
 692
 693         if (!radeon_encoder->enc_priv)
 694                 return;
 695
 696         dig = radeon_encoder->enc_priv;
 697
 698         if (!radeon_connector->con_priv)
 699                 return;
 700
 701         dig_connector = radeon_connector->con_priv;
 702
 703         memset(&args, 0, sizeof(args));
 704
 705         if (ASIC_IS_DCE32(rdev))
 706                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 707         else {
 708                 switch (radeon_encoder->encoder_id) {
 709                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 710                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 711                         break;
 712                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 713                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 714                         break;
 715                 }
 716         }
 717
 718         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 719
 720         args.v1.ucAction = action;
 721
 722         if (ASIC_IS_DCE32(rdev)) {
 723                 if (radeon_encoder->pixel_clock > 165000) {
 724                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
 725                         args.v2.acConfig.fDualLinkConnector = 1;
 726                 } else {
 727                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
 728                 }
 729                 if (dig->dig_block)
 730                         args.v2.acConfig.ucEncoderSel = 1;
 731
 732                 switch (radeon_encoder->encoder_id) {
 733                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 734                         args.v2.acConfig.ucTransmitterSel = 0;
 735                         num = 0;
 736                         break;
 737                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 738                         args.v2.acConfig.ucTransmitterSel = 1;
 739                         num = 1;
 740                         break;
 741                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 742                         args.v2.acConfig.ucTransmitterSel = 2;
 743                         num = 2;
 744                         break;
 745                 }
 746
 747                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 748                         if (dig->coherent_mode)
 749                                 args.v2.acConfig.fCoherentMode = 1;
 750                 }
 751         } else {
 752                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 753                 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
 754
 755                 switch (radeon_encoder->encoder_id) {
 756                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 757                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 758                         if (rdev->flags & RADEON_IS_IGP) {
 759                                 if (radeon_encoder->pixel_clock > 165000) {
 760                                         args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 761                                                              ATOM_TRANSMITTER_CONFIG_LINKA_B);
 762                                         if (dig_connector->igp_lane_info & 0x3)
 763                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 764                                         else if (dig_connector->igp_lane_info & 0xc)
 765                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 766                                 } else {
 767                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 768                                         if (dig_connector->igp_lane_info & 0x1)
 769                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 770                                         else if (dig_connector->igp_lane_info & 0x2)
 771                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 772                                         else if (dig_connector->igp_lane_info & 0x4)
 773                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 774                                         else if (dig_connector->igp_lane_info & 0x8)
 775                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 776                                 }
 777                         } else {
 778                                 if (radeon_encoder->pixel_clock > 165000)
 779                                         args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 780                                                              ATOM_TRANSMITTER_CONFIG_LINKA_B |
 781                                                              ATOM_TRANSMITTER_CONFIG_LANE_0_7);
 782                                 else {
 783                                         if (dig_connector->linkb)
 784                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 785                                         else
 786                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 787                                 }
 788                         }
 789                         break;
 790                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 791                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 792                         if (radeon_encoder->pixel_clock > 165000)
 793                                 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 794                                                      ATOM_TRANSMITTER_CONFIG_LINKA_B |
 795                                                      ATOM_TRANSMITTER_CONFIG_LANE_0_7);
 796                         else {
 797                                 if (dig_connector->linkb)
 798                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 799                                 else
 800                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 801                         }
 802                         break;
 803                 }
 804
 805                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 806                         if (dig->coherent_mode)
 807                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 808                 }
 809         }
 810
 811         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 812
 813 }
 814
 815 static void
 816 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 817 {
 818         struct drm_device *dev = encoder->dev;
 819         struct radeon_device *rdev = dev->dev_private;
 820         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 821         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 822         ENABLE_YUV_PS_ALLOCATION args;
 823         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 824         uint32_t temp, reg;
 825
 826         memset(&args, 0, sizeof(args));
 827
 828         if (rdev->family >= CHIP_R600)
 829                 reg = R600_BIOS_3_SCRATCH;
 830         else
 831                 reg = RADEON_BIOS_3_SCRATCH;
 832
 833         /* XXX: fix up scratch reg handling */
 834         temp = RREG32(reg);
 835         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 836                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 837                              (radeon_crtc->crtc_id << 18)));
 838         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 839                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 840         else
 841                 WREG32(reg, 0);
 842
 843         if (enable)
 844                 args.ucEnable = ATOM_ENABLE;
 845         args.ucCRTC = radeon_crtc->crtc_id;
 846
 847         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 848
 849         WREG32(reg, temp);
 850 }
 851
 852 static void
 853 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 854 {
 855         struct drm_device *dev = encoder->dev;
 856         struct radeon_device *rdev = dev->dev_private;
 857         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 858         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 859         int index = 0;
 860         bool is_dig = false;
 861         int devices;
 862
 863         memset(&args, 0, sizeof(args));
 864
 865         /* on DPMS off we have no idea if active device is meaningful */
 866         if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
 867                 devices = radeon_encoder->devices;
 868         else
 869                 devices = radeon_encoder->active_device;
 870
 871         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 872                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 873                   radeon_encoder->active_device);
 874         switch (radeon_encoder->encoder_id) {
 875         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 876         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 877                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 878                 break;
 879         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 880         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 881         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 882         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 883                 is_dig = true;
 884                 break;
 885         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 886         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 887         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 888                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 889                 break;
 890         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 891                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 892                 break;
 893         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 894                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 895                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 896                 else
 897                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 898                 break;
 899         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 900         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 901                 if (devices & (ATOM_DEVICE_TV_SUPPORT))
 902                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 903                 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
 904                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 905                 else
 906                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 907                 break;
 908         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 909         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 910                 if (devices & (ATOM_DEVICE_TV_SUPPORT))
 911                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 912                 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
 913                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 914                 else
 915                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 916                 break;
 917         }
 918
 919         if (is_dig) {
 920                 switch (mode) {
 921                 case DRM_MODE_DPMS_ON:
 922                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
 923                         break;
 924                 case DRM_MODE_DPMS_STANDBY:
 925                 case DRM_MODE_DPMS_SUSPEND:
 926                 case DRM_MODE_DPMS_OFF:
 927                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
 928                         break;
 929                 }
 930         } else {
 931                 switch (mode) {
 932                 case DRM_MODE_DPMS_ON:
 933                         args.ucAction = ATOM_ENABLE;
 934                         break;
 935                 case DRM_MODE_DPMS_STANDBY:
 936                 case DRM_MODE_DPMS_SUSPEND:
 937                 case DRM_MODE_DPMS_OFF:
 938                         args.ucAction = ATOM_DISABLE;
 939                         break;
 940                 }
 941                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 942         }
 943         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 944 }
 945
 946 union crtc_sourc_param {
 947         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
 948         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
 949 };
 950
 951 static void
 952 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
 953 {
 954         struct drm_device *dev = encoder->dev;
 955         struct radeon_device *rdev = dev->dev_private;
 956         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 957         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 958         union crtc_sourc_param args;
 959         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
 960         uint8_t frev, crev;
 961
 962         memset(&args, 0, sizeof(args));
 963
 964         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 965
 966         switch (frev) {
 967         case 1:
 968                 switch (crev) {
 969                 case 1:
 970                 default:
 971                         if (ASIC_IS_AVIVO(rdev))
 972                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
 973                         else {
 974                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
 975                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
 976                                 } else {
 977                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
 978                                 }
 979                         }
 980                         switch (radeon_encoder->encoder_id) {
 981                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 982                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 983                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
 984                                 break;
 985                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 986                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 987                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
 988                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
 989                                 else
 990                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
 991                                 break;
 992                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 993                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 994                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 995                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
 996                                 break;
 997                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 998                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 999                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1000                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1001                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1002                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1003                                 else
1004                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1005                                 break;
1006                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1007                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1008                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1009                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1010                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1011                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1012                                 else
1013                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1014                                 break;
1015                         }
1016                         break;
1017                 case 2:
1018                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1019                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1020                         switch (radeon_encoder->encoder_id) {
1021                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1022                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1023                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1024                                 if (ASIC_IS_DCE32(rdev)) {
1025                                         if (radeon_crtc->crtc_id)
1026                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1027                                         else
1028                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1029                                 } else
1030                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1031                                 break;
1032                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1033                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1034                                 break;
1035                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1036                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1037                                 break;
1038                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1039                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1040                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1041                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1042                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1043                                 else
1044                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1045                                 break;
1046                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1047                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1048                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1049                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1050                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1051                                 else
1052                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1053                                 break;
1054                         }
1055                         break;
1056                 }
1057                 break;
1058         default:
1059                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1060                 break;
1061         }
1062
1063         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1064
1065 }
1066
1067 static void
1068 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1069                               struct drm_display_mode *mode)
1070 {
1071         struct drm_device *dev = encoder->dev;
1072         struct radeon_device *rdev = dev->dev_private;
1073         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1074         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1075
1076         /* Funky macbooks */
1077         if ((dev->pdev->device == 0x71C5) &&
1078             (dev->pdev->subsystem_vendor == 0x106b) &&
1079             (dev->pdev->subsystem_device == 0x0080)) {
1080                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1081                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1082
1083                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1084                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1085
1086                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1087                 }
1088         }
1089
1090         /* set scaler clears this on some chips */
1091         if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1092                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
1093 }
1094
1095 static void
1096 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1097                              struct drm_display_mode *mode,
1098                              struct drm_display_mode *adjusted_mode)
1099 {
1100         struct drm_device *dev = encoder->dev;
1101         struct radeon_device *rdev = dev->dev_private;
1102         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1104
1105         if (radeon_encoder->enc_priv) {
1106                 struct radeon_encoder_atom_dig *dig;
1107
1108                 dig = radeon_encoder->enc_priv;
1109                 dig->dig_block = radeon_crtc->crtc_id;
1110         }
1111         radeon_encoder->pixel_clock = adjusted_mode->clock;
1112
1113         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1114         atombios_set_encoder_crtc_source(encoder);
1115
1116         if (ASIC_IS_AVIVO(rdev)) {
1117                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1118                         atombios_yuv_setup(encoder, true);
1119                 else
1120                         atombios_yuv_setup(encoder, false);
1121         }
1122
1123         switch (radeon_encoder->encoder_id) {
1124         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1125         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1126         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1127         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1128                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1129                 break;
1130         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1131         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1132         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1133         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1134                 /* disable the encoder and transmitter */
1135                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
1136                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1137
1138                 /* setup and enable the encoder and transmitter */
1139                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1140                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1141                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1142                 break;
1143         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1144                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1145                 break;
1146         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1147         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1148                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1149                 break;
1150         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1151         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1152         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1153         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1154                 atombios_dac_setup(encoder, ATOM_ENABLE);
1155                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1156                         atombios_tv_setup(encoder, ATOM_ENABLE);
1157                 break;
1158         }
1159         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1160 }
1161
1162 static bool
1163 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1164 {
1165         struct drm_device *dev = encoder->dev;
1166         struct radeon_device *rdev = dev->dev_private;
1167         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1168         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1169
1170         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1171                                        ATOM_DEVICE_CV_SUPPORT |
1172                                        ATOM_DEVICE_CRT_SUPPORT)) {
1173                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1174                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1175                 uint8_t frev, crev;
1176
1177                 memset(&args, 0, sizeof(args));
1178
1179                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1180
1181                 args.sDacload.ucMisc = 0;
1182
1183                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1184                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1185                         args.sDacload.ucDacType = ATOM_DAC_A;
1186                 else
1187                         args.sDacload.ucDacType = ATOM_DAC_B;
1188
1189                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1190                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1191                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1192                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1193                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1194                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1195                         if (crev >= 3)
1196                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1197                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1198                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1199                         if (crev >= 3)
1200                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1201                 }
1202
1203                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1204
1205                 return true;
1206         } else
1207                 return false;
1208 }
1209
1210 static enum drm_connector_status
1211 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1212 {
1213         struct drm_device *dev = encoder->dev;
1214         struct radeon_device *rdev = dev->dev_private;
1215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1216         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1217         uint32_t bios_0_scratch;
1218
1219         if (!atombios_dac_load_detect(encoder, connector)) {
1220                 DRM_DEBUG("detect returned false \n");
1221                 return connector_status_unknown;
1222         }
1223
1224         if (rdev->family >= CHIP_R600)
1225                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1226         else
1227                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1228
1229         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1230         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1231                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1232                         return connector_status_connected;
1233         }
1234         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1235                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1236                         return connector_status_connected;
1237         }
1238         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1239                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1240                         return connector_status_connected;
1241         }
1242         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1243                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1244                         return connector_status_connected; /* CTV */
1245                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1246                         return connector_status_connected; /* STV */
1247         }
1248         return connector_status_disconnected;
1249 }
1250
1251 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1252 {
1253         radeon_atom_output_lock(encoder, true);
1254         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1255
1256         radeon_encoder_set_active_device(encoder);
1257 }
1258
1259 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1260 {
1261         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1262         radeon_atom_output_lock(encoder, false);
1263 }
1264
1265 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1266 {
1267         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1268         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1269         radeon_encoder->active_device = 0;
1270 }
1271
1272 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1273         .dpms = radeon_atom_encoder_dpms,
1274         .mode_fixup = radeon_atom_mode_fixup,
1275         .prepare = radeon_atom_encoder_prepare,
1276         .mode_set = radeon_atom_encoder_mode_set,
1277         .commit = radeon_atom_encoder_commit,
1278         .disable = radeon_atom_encoder_disable,
1279         /* no detect for TMDS/LVDS yet */
1280 };
1281
1282 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1283         .dpms = radeon_atom_encoder_dpms,
1284         .mode_fixup = radeon_atom_mode_fixup,
1285         .prepare = radeon_atom_encoder_prepare,
1286         .mode_set = radeon_atom_encoder_mode_set,
1287         .commit = radeon_atom_encoder_commit,
1288         .detect = radeon_atom_dac_detect,
1289 };
1290
1291 void radeon_enc_destroy(struct drm_encoder *encoder)
1292 {
1293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1294         kfree(radeon_encoder->enc_priv);
1295         drm_encoder_cleanup(encoder);
1296         kfree(radeon_encoder);
1297 }
1298
1299 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1300         .destroy = radeon_enc_destroy,
1301 };
1302
1303 struct radeon_encoder_atom_dac *
1304 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1305 {
1306         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1307
1308         if (!dac)
1309                 return NULL;
1310
1311         dac->tv_std = TV_STD_NTSC;
1312         return dac;
1313 }
1314
1315 struct radeon_encoder_atom_dig *
1316 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1317 {
1318         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1319
1320         if (!dig)
1321                 return NULL;
1322
1323         /* coherent mode by default */
1324         dig->coherent_mode = true;
1325
1326         return dig;
1327 }
1328
1329 void
1330 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1331 {
1332         struct radeon_device *rdev = dev->dev_private;
1333         struct drm_encoder *encoder;
1334         struct radeon_encoder *radeon_encoder;
1335
1336         /* see if we already added it */
1337         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1338                 radeon_encoder = to_radeon_encoder(encoder);
1339                 if (radeon_encoder->encoder_id == encoder_id) {
1340                         radeon_encoder->devices |= supported_device;
1341                         return;
1342                 }
1343
1344         }
1345
1346         /* add a new one */
1347         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1348         if (!radeon_encoder)
1349                 return;
1350
1351         encoder = &radeon_encoder->base;
1352         if (rdev->flags & RADEON_SINGLE_CRTC)
1353                 encoder->possible_crtcs = 0x1;
1354         else
1355                 encoder->possible_crtcs = 0x3;
1356         encoder->possible_clones = 0;
1357
1358         radeon_encoder->enc_priv = NULL;
1359
1360         radeon_encoder->encoder_id = encoder_id;
1361         radeon_encoder->devices = supported_device;
1362         radeon_encoder->rmx_type = RMX_OFF;
1363
1364         switch (radeon_encoder->encoder_id) {
1365         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1366         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1367         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1368         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1369                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1370                         radeon_encoder->rmx_type = RMX_FULL;
1371                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1372                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1373                 } else {
1374                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1375                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1376                 }
1377                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1378                 break;
1379         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1380                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1381                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1382                 break;
1383         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1384         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1385         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1386                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1387                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1388                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1389                 break;
1390         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1391         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1392         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1393         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1394         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1395         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1396         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1397                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1398                         radeon_encoder->rmx_type = RMX_FULL;
1399                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1400                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1401                 } else {
1402                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1403                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1404                 }
1405                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1406                 break;
1407         }
1408 }