SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* adjust pm to upcoming mode change */
 266         radeon_pm_compute_clocks(rdev);
 267
 268         /* set the active encoder to connector routing */
 269         radeon_encoder_set_active_device(encoder);
 270         drm_mode_set_crtcinfo(adjusted_mode, 0);
 271
 272         /* hw bug */
 273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 276
 277         /* get the native mode for LVDS */
 278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 280                 int mode_id = adjusted_mode->base.id;
 281                 *adjusted_mode = *native_mode;
 282                 if (!ASIC_IS_AVIVO(rdev)) {
 283                         adjusted_mode->hdisplay = mode->hdisplay;
 284                         adjusted_mode->vdisplay = mode->vdisplay;
 285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 287                 }
 288                 adjusted_mode->base.id = mode_id;
 289         }
 290
 291         /* get the native mode for TV */
 292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 294                 if (tv_dac) {
 295                         if (tv_dac->tv_std == TV_STD_NTSC ||
 296                             tv_dac->tv_std == TV_STD_NTSC_J ||
 297                             tv_dac->tv_std == TV_STD_PAL_M)
 298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 299                         else
 300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 301                 }
 302         }
 303
 304         if (ASIC_IS_DCE3(rdev) &&
 305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 307                 radeon_dp_set_link_config(connector, mode);
 308         }
 309
 310         return true;
 311 }
 312
 313 static void
 314 atombios_dac_setup(struct drm_encoder *encoder, int action)
 315 {
 316         struct drm_device *dev = encoder->dev;
 317         struct radeon_device *rdev = dev->dev_private;
 318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 320         int index = 0, num = 0;
 321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 322         enum radeon_tv_std tv_std = TV_STD_NTSC;
 323
 324         if (dac_info->tv_std)
 325                 tv_std = dac_info->tv_std;
 326
 327         memset(&args, 0, sizeof(args));
 328
 329         switch (radeon_encoder->encoder_id) {
 330         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 332                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 333                 num = 1;
 334                 break;
 335         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 336         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 337                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 338                 num = 2;
 339                 break;
 340         }
 341
 342         args.ucAction = action;
 343
 344         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 345                 args.ucDacStandard = ATOM_DAC1_PS2;
 346         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 347                 args.ucDacStandard = ATOM_DAC1_CV;
 348         else {
 349                 switch (tv_std) {
 350                 case TV_STD_PAL:
 351                 case TV_STD_PAL_M:
 352                 case TV_STD_SCART_PAL:
 353                 case TV_STD_SECAM:
 354                 case TV_STD_PAL_CN:
 355                         args.ucDacStandard = ATOM_DAC1_PAL;
 356                         break;
 357                 case TV_STD_NTSC:
 358                 case TV_STD_NTSC_J:
 359                 case TV_STD_PAL_60:
 360                 default:
 361                         args.ucDacStandard = ATOM_DAC1_NTSC;
 362                         break;
 363                 }
 364         }
 365         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 366
 367         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 368
 369 }
 370
 371 static void
 372 atombios_tv_setup(struct drm_encoder *encoder, int action)
 373 {
 374         struct drm_device *dev = encoder->dev;
 375         struct radeon_device *rdev = dev->dev_private;
 376         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 377         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 378         int index = 0;
 379         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 380         enum radeon_tv_std tv_std = TV_STD_NTSC;
 381
 382         if (dac_info->tv_std)
 383                 tv_std = dac_info->tv_std;
 384
 385         memset(&args, 0, sizeof(args));
 386
 387         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 388
 389         args.sTVEncoder.ucAction = action;
 390
 391         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 392                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 393         else {
 394                 switch (tv_std) {
 395                 case TV_STD_NTSC:
 396                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 397                         break;
 398                 case TV_STD_PAL:
 399                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 400                         break;
 401                 case TV_STD_PAL_M:
 402                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 403                         break;
 404                 case TV_STD_PAL_60:
 405                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 406                         break;
 407                 case TV_STD_NTSC_J:
 408                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 409                         break;
 410                 case TV_STD_SCART_PAL:
 411                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 412                         break;
 413                 case TV_STD_SECAM:
 414                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 415                         break;
 416                 case TV_STD_PAL_CN:
 417                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 418                         break;
 419                 default:
 420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 421                         break;
 422                 }
 423         }
 424
 425         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 426
 427         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 428
 429 }
 430
 431 void
 432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 433 {
 434         struct drm_device *dev = encoder->dev;
 435         struct radeon_device *rdev = dev->dev_private;
 436         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 437         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 438         int index = 0;
 439
 440         memset(&args, 0, sizeof(args));
 441
 442         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 443
 444         args.sXTmdsEncoder.ucEnable = action;
 445
 446         if (radeon_encoder->pixel_clock > 165000)
 447                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 448
 449         /*if (pScrn->rgbBits == 8)*/
 450         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 451
 452         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 453
 454 }
 455
 456 static void
 457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 458 {
 459         struct drm_device *dev = encoder->dev;
 460         struct radeon_device *rdev = dev->dev_private;
 461         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 462         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 463         int index = 0;
 464
 465         memset(&args, 0, sizeof(args));
 466
 467         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 468
 469         args.sDVOEncoder.ucAction = action;
 470         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 471
 472         if (radeon_encoder->pixel_clock > 165000)
 473                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 474
 475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 476
 477 }
 478
 479 union lvds_encoder_control {
 480         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 481         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 482 };
 483
 484 void
 485 atombios_digital_setup(struct drm_encoder *encoder, int action)
 486 {
 487         struct drm_device *dev = encoder->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 490         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 491         struct radeon_connector_atom_dig *dig_connector =
 492                 radeon_get_atom_connector_priv_from_encoder(encoder);
 493         union lvds_encoder_control args;
 494         int index = 0;
 495         int hdmi_detected = 0;
 496         uint8_t frev, crev;
 497
 498         if (!dig || !dig_connector)
 499                 return;
 500
 501         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 502                 hdmi_detected = 1;
 503
 504         memset(&args, 0, sizeof(args));
 505
 506         switch (radeon_encoder->encoder_id) {
 507         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 508                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 509                 break;
 510         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 511         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 512                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 513                 break;
 514         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 515                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 516                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 517                 else
 518                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 519                 break;
 520         }
 521
 522         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 523
 524         switch (frev) {
 525         case 1:
 526         case 2:
 527                 switch (crev) {
 528                 case 1:
 529                         args.v1.ucMisc = 0;
 530                         args.v1.ucAction = action;
 531                         if (hdmi_detected)
 532                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 533                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 534                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 535                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 536                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 537                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 538                                         args.v1.ucMisc |= (1 << 1);
 539                         } else {
 540                                 if (dig_connector->linkb)
 541                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 542                                 if (radeon_encoder->pixel_clock > 165000)
 543                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 544                                 /*if (pScrn->rgbBits == 8) */
 545                                 args.v1.ucMisc |= (1 << 1);
 546                         }
 547                         break;
 548                 case 2:
 549                 case 3:
 550                         args.v2.ucMisc = 0;
 551                         args.v2.ucAction = action;
 552                         if (crev == 3) {
 553                                 if (dig->coherent_mode)
 554                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 555                         }
 556                         if (hdmi_detected)
 557                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 558                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 559                         args.v2.ucTruncate = 0;
 560                         args.v2.ucSpatial = 0;
 561                         args.v2.ucTemporal = 0;
 562                         args.v2.ucFRC = 0;
 563                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 564                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 565                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 566                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 567                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 568                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 569                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 570                                 }
 571                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 572                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 573                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 574                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 575                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 576                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 577                                 }
 578                         } else {
 579                                 if (dig_connector->linkb)
 580                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 581                                 if (radeon_encoder->pixel_clock > 165000)
 582                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 583                         }
 584                         break;
 585                 default:
 586                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 587                         break;
 588                 }
 589                 break;
 590         default:
 591                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 592                 break;
 593         }
 594
 595         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 596         r600_hdmi_enable(encoder, hdmi_detected);
 597 }
 598
 599 int
 600 atombios_get_encoder_mode(struct drm_encoder *encoder)
 601 {
 602         struct drm_connector *connector;
 603         struct radeon_connector *radeon_connector;
 604         struct radeon_connector_atom_dig *dig_connector;
 605
 606         connector = radeon_get_connector_for_encoder(encoder);
 607         if (!connector)
 608                 return 0;
 609
 610         radeon_connector = to_radeon_connector(connector);
 611
 612         switch (connector->connector_type) {
 613         case DRM_MODE_CONNECTOR_DVII:
 614         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 615                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 616                         return ATOM_ENCODER_MODE_HDMI;
 617                 else if (radeon_connector->use_digital)
 618                         return ATOM_ENCODER_MODE_DVI;
 619                 else
 620                         return ATOM_ENCODER_MODE_CRT;
 621                 break;
 622         case DRM_MODE_CONNECTOR_DVID:
 623         case DRM_MODE_CONNECTOR_HDMIA:
 624         default:
 625                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 626                         return ATOM_ENCODER_MODE_HDMI;
 627                 else
 628                         return ATOM_ENCODER_MODE_DVI;
 629                 break;
 630         case DRM_MODE_CONNECTOR_LVDS:
 631                 return ATOM_ENCODER_MODE_LVDS;
 632                 break;
 633         case DRM_MODE_CONNECTOR_DisplayPort:
 634         case DRM_MODE_CONNECTOR_eDP:
 635                 dig_connector = radeon_connector->con_priv;
 636                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 637                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 638                         return ATOM_ENCODER_MODE_DP;
 639                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 640                         return ATOM_ENCODER_MODE_HDMI;
 641                 else
 642                         return ATOM_ENCODER_MODE_DVI;
 643                 break;
 644         case DRM_MODE_CONNECTOR_DVIA:
 645         case DRM_MODE_CONNECTOR_VGA:
 646                 return ATOM_ENCODER_MODE_CRT;
 647                 break;
 648         case DRM_MODE_CONNECTOR_Composite:
 649         case DRM_MODE_CONNECTOR_SVIDEO:
 650         case DRM_MODE_CONNECTOR_9PinDIN:
 651                 /* fix me */
 652                 return ATOM_ENCODER_MODE_TV;
 653                 /*return ATOM_ENCODER_MODE_CV;*/
 654                 break;
 655         }
 656 }
 657
 658 /*
 659  * DIG Encoder/Transmitter Setup
 660  *
 661  * DCE 3.0/3.1
 662  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 663  * Supports up to 3 digital outputs
 664  * - 2 DIG encoder blocks.
 665  * DIG1 can drive UNIPHY link A or link B
 666  * DIG2 can drive UNIPHY link B or LVTMA
 667  *
 668  * DCE 3.2
 669  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 670  * Supports up to 5 digital outputs
 671  * - 2 DIG encoder blocks.
 672  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 673  *
 674  * Routing
 675  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 676  * Examples:
 677  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 678  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 679  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 680  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 681  */
 682 static void
 683 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 684 {
 685         struct drm_device *dev = encoder->dev;
 686         struct radeon_device *rdev = dev->dev_private;
 687         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 688         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 689         struct radeon_connector_atom_dig *dig_connector =
 690                 radeon_get_atom_connector_priv_from_encoder(encoder);
 691         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 692         int index = 0, num = 0;
 693         uint8_t frev, crev;
 694
 695         if (!dig || !dig_connector)
 696                 return;
 697
 698         memset(&args, 0, sizeof(args));
 699
 700         if (dig->dig_encoder)
 701                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 702         else
 703                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 704         num = dig->dig_encoder + 1;
 705
 706         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 707
 708         args.ucAction = action;
 709         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 710
 711         if (ASIC_IS_DCE32(rdev)) {
 712                 switch (radeon_encoder->encoder_id) {
 713                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 714                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 715                         break;
 716                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 717                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 718                         break;
 719                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 720                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 721                         break;
 722                 }
 723         } else {
 724                 switch (radeon_encoder->encoder_id) {
 725                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 726                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 727                         break;
 728                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 729                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 730                         break;
 731                 }
 732         }
 733
 734         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 735
 736         if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 737                 if (dig_connector->dp_clock == 270000)
 738                         args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 739                 args.ucLaneNum = dig_connector->dp_lane_count;
 740         } else if (radeon_encoder->pixel_clock > 165000)
 741                 args.ucLaneNum = 8;
 742         else
 743                 args.ucLaneNum = 4;
 744
 745         if (dig_connector->linkb)
 746                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 747         else
 748                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 749
 750         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 751
 752 }
 753
 754 union dig_transmitter_control {
 755         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 756         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 757 };
 758
 759 void
 760 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 761 {
 762         struct drm_device *dev = encoder->dev;
 763         struct radeon_device *rdev = dev->dev_private;
 764         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 765         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 766         struct radeon_connector_atom_dig *dig_connector =
 767                 radeon_get_atom_connector_priv_from_encoder(encoder);
 768         struct drm_connector *connector;
 769         struct radeon_connector *radeon_connector;
 770         union dig_transmitter_control args;
 771         int index = 0, num = 0;
 772         uint8_t frev, crev;
 773         bool is_dp = false;
 774
 775         if (!dig || !dig_connector)
 776                 return;
 777
 778         connector = radeon_get_connector_for_encoder(encoder);
 779         radeon_connector = to_radeon_connector(connector);
 780
 781         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 782                 is_dp = true;
 783
 784         memset(&args, 0, sizeof(args));
 785
 786         if (ASIC_IS_DCE32(rdev))
 787                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 788         else {
 789                 switch (radeon_encoder->encoder_id) {
 790                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 791                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 792                         break;
 793                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 794                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 795                         break;
 796                 }
 797         }
 798
 799         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 800
 801         args.v1.ucAction = action;
 802         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 803                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 804         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 805                 args.v1.asMode.ucLaneSel = lane_num;
 806                 args.v1.asMode.ucLaneSet = lane_set;
 807         } else {
 808                 if (is_dp)
 809                         args.v1.usPixelClock =
 810                                 cpu_to_le16(dig_connector->dp_clock / 10);
 811                 else if (radeon_encoder->pixel_clock > 165000)
 812                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 813                 else
 814                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 815         }
 816         if (ASIC_IS_DCE32(rdev)) {
 817                 if (dig->dig_encoder == 1)
 818                         args.v2.acConfig.ucEncoderSel = 1;
 819                 if (dig_connector->linkb)
 820                         args.v2.acConfig.ucLinkSel = 1;
 821
 822                 switch (radeon_encoder->encoder_id) {
 823                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 824                         args.v2.acConfig.ucTransmitterSel = 0;
 825                         num = 0;
 826                         break;
 827                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 828                         args.v2.acConfig.ucTransmitterSel = 1;
 829                         num = 1;
 830                         break;
 831                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 832                         args.v2.acConfig.ucTransmitterSel = 2;
 833                         num = 2;
 834                         break;
 835                 }
 836
 837                 if (is_dp)
 838                         args.v2.acConfig.fCoherentMode = 1;
 839                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 840                         if (dig->coherent_mode)
 841                                 args.v2.acConfig.fCoherentMode = 1;
 842                 }
 843         } else {
 844
 845                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 846
 847                 if (dig->dig_encoder)
 848                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 849                 else
 850                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 851
 852                 switch (radeon_encoder->encoder_id) {
 853                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 854                         if (rdev->flags & RADEON_IS_IGP) {
 855                                 if (radeon_encoder->pixel_clock > 165000) {
 856                                         if (dig_connector->igp_lane_info & 0x3)
 857                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 858                                         else if (dig_connector->igp_lane_info & 0xc)
 859                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 860                                 } else {
 861                                         if (dig_connector->igp_lane_info & 0x1)
 862                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 863                                         else if (dig_connector->igp_lane_info & 0x2)
 864                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 865                                         else if (dig_connector->igp_lane_info & 0x4)
 866                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 867                                         else if (dig_connector->igp_lane_info & 0x8)
 868                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 869                                 }
 870                         }
 871                         break;
 872                 }
 873
 874                 if (radeon_encoder->pixel_clock > 165000)
 875                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 876
 877                 if (dig_connector->linkb)
 878                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 879                 else
 880                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 881
 882                 if (is_dp)
 883                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 884                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 885                         if (dig->coherent_mode)
 886                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 887                 }
 888         }
 889
 890         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 891 }
 892
 893 static void
 894 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 895 {
 896         struct drm_device *dev = encoder->dev;
 897         struct radeon_device *rdev = dev->dev_private;
 898         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 899         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 900         ENABLE_YUV_PS_ALLOCATION args;
 901         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 902         uint32_t temp, reg;
 903
 904         memset(&args, 0, sizeof(args));
 905
 906         if (rdev->family >= CHIP_R600)
 907                 reg = R600_BIOS_3_SCRATCH;
 908         else
 909                 reg = RADEON_BIOS_3_SCRATCH;
 910
 911         /* XXX: fix up scratch reg handling */
 912         temp = RREG32(reg);
 913         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 914                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 915                              (radeon_crtc->crtc_id << 18)));
 916         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 917                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 918         else
 919                 WREG32(reg, 0);
 920
 921         if (enable)
 922                 args.ucEnable = ATOM_ENABLE;
 923         args.ucCRTC = radeon_crtc->crtc_id;
 924
 925         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 926
 927         WREG32(reg, temp);
 928 }
 929
 930 static void
 931 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 932 {
 933         struct drm_device *dev = encoder->dev;
 934         struct radeon_device *rdev = dev->dev_private;
 935         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 936         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 937         int index = 0;
 938         bool is_dig = false;
 939
 940         memset(&args, 0, sizeof(args));
 941
 942         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 943                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 944                   radeon_encoder->active_device);
 945         switch (radeon_encoder->encoder_id) {
 946         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 947         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 948                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 949                 break;
 950         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 951         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 952         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 953         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 954                 is_dig = true;
 955                 break;
 956         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 957         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 958         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 959                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 960                 break;
 961         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 962                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 963                 break;
 964         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 965                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 966                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 967                 else
 968                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 969                 break;
 970         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 971         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 972                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 973                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 974                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 975                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 976                 else
 977                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 978                 break;
 979         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 980         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 981                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 982                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 983                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 984                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 985                 else
 986                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 987                 break;
 988         }
 989
 990         if (is_dig) {
 991                 switch (mode) {
 992                 case DRM_MODE_DPMS_ON:
 993                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
 994                         {
 995                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 996                                 dp_link_train(encoder, connector);
 997                         }
 998                         break;
 999                 case DRM_MODE_DPMS_STANDBY:
1000                 case DRM_MODE_DPMS_SUSPEND:
1001                 case DRM_MODE_DPMS_OFF:
1002                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1003                         break;
1004                 }
1005         } else {
1006                 switch (mode) {
1007                 case DRM_MODE_DPMS_ON:
1008                         args.ucAction = ATOM_ENABLE;
1009                         break;
1010                 case DRM_MODE_DPMS_STANDBY:
1011                 case DRM_MODE_DPMS_SUSPEND:
1012                 case DRM_MODE_DPMS_OFF:
1013                         args.ucAction = ATOM_DISABLE;
1014                         break;
1015                 }
1016                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1017         }
1018         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1019
1020         /* adjust pm to dpms change */
1021         radeon_pm_compute_clocks(rdev);
1022 }
1023
1024 union crtc_source_param {
1025         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1026         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1027 };
1028
1029 static void
1030 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1031 {
1032         struct drm_device *dev = encoder->dev;
1033         struct radeon_device *rdev = dev->dev_private;
1034         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1035         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1036         union crtc_source_param args;
1037         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1038         uint8_t frev, crev;
1039         struct radeon_encoder_atom_dig *dig;
1040
1041         memset(&args, 0, sizeof(args));
1042
1043         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1044
1045         switch (frev) {
1046         case 1:
1047                 switch (crev) {
1048                 case 1:
1049                 default:
1050                         if (ASIC_IS_AVIVO(rdev))
1051                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1052                         else {
1053                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1054                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1055                                 } else {
1056                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1057                                 }
1058                         }
1059                         switch (radeon_encoder->encoder_id) {
1060                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1061                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1062                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1063                                 break;
1064                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1065                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1066                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1067                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1068                                 else
1069                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1070                                 break;
1071                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1072                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1073                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1074                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1075                                 break;
1076                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1077                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1078                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1079                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1080                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1081                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1082                                 else
1083                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1084                                 break;
1085                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1086                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1087                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1088                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1089                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1090                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1091                                 else
1092                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1093                                 break;
1094                         }
1095                         break;
1096                 case 2:
1097                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1098                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1099                         switch (radeon_encoder->encoder_id) {
1100                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1101                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1102                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1103                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1104                                 dig = radeon_encoder->enc_priv;
1105                                 if (dig->dig_encoder)
1106                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1107                                 else
1108                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1109                                 break;
1110                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1111                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1112                                 break;
1113                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1114                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1115                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1116                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1117                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1118                                 else
1119                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1120                                 break;
1121                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1122                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1123                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1124                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1126                                 else
1127                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1128                                 break;
1129                         }
1130                         break;
1131                 }
1132                 break;
1133         default:
1134                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1135                 break;
1136         }
1137
1138         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1139 }
1140
1141 static void
1142 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1143                               struct drm_display_mode *mode)
1144 {
1145         struct drm_device *dev = encoder->dev;
1146         struct radeon_device *rdev = dev->dev_private;
1147         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1148         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1149
1150         /* Funky macbooks */
1151         if ((dev->pdev->device == 0x71C5) &&
1152             (dev->pdev->subsystem_vendor == 0x106b) &&
1153             (dev->pdev->subsystem_device == 0x0080)) {
1154                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1155                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1156
1157                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1158                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1159
1160                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1161                 }
1162         }
1163
1164         /* set scaler clears this on some chips */
1165         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1166                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1167                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1168                                AVIVO_D1MODE_INTERLEAVE_EN);
1169         }
1170 }
1171
1172 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1173 {
1174         struct drm_device *dev = encoder->dev;
1175         struct radeon_device *rdev = dev->dev_private;
1176         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1178         struct drm_encoder *test_encoder;
1179         struct radeon_encoder_atom_dig *dig;
1180         uint32_t dig_enc_in_use = 0;
1181         /* on DCE32 and encoder can driver any block so just crtc id */
1182         if (ASIC_IS_DCE32(rdev)) {
1183                 return radeon_crtc->crtc_id;
1184         }
1185
1186         /* on DCE3 - LVTMA can only be driven by DIGB */
1187         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1188                 struct radeon_encoder *radeon_test_encoder;
1189
1190                 if (encoder == test_encoder)
1191                         continue;
1192
1193                 if (!radeon_encoder_is_digital(test_encoder))
1194                         continue;
1195
1196                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1197                 dig = radeon_test_encoder->enc_priv;
1198
1199                 if (dig->dig_encoder >= 0)
1200                         dig_enc_in_use |= (1 << dig->dig_encoder);
1201         }
1202
1203         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1204                 if (dig_enc_in_use & 0x2)
1205                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1206                 return 1;
1207         }
1208         if (!(dig_enc_in_use & 1))
1209                 return 0;
1210         return 1;
1211 }
1212
1213 static void
1214 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1215                              struct drm_display_mode *mode,
1216                              struct drm_display_mode *adjusted_mode)
1217 {
1218         struct drm_device *dev = encoder->dev;
1219         struct radeon_device *rdev = dev->dev_private;
1220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1221         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1222
1223         if (radeon_encoder->active_device &
1224             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1225                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1226                 if (dig)
1227                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1228         }
1229         radeon_encoder->pixel_clock = adjusted_mode->clock;
1230
1231         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1232         atombios_set_encoder_crtc_source(encoder);
1233
1234         if (ASIC_IS_AVIVO(rdev)) {
1235                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1236                         atombios_yuv_setup(encoder, true);
1237                 else
1238                         atombios_yuv_setup(encoder, false);
1239         }
1240
1241         switch (radeon_encoder->encoder_id) {
1242         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1243         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1244         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1245         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1246                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1247                 break;
1248         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1249         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1250         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1251         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1252                 /* disable the encoder and transmitter */
1253                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1254                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1255
1256                 /* setup and enable the encoder and transmitter */
1257                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1258                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1259                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1260                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1261                 break;
1262         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1263                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1264                 break;
1265         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1266         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1267                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1268                 break;
1269         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1270         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1271         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1272         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1273                 atombios_dac_setup(encoder, ATOM_ENABLE);
1274                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1275                         atombios_tv_setup(encoder, ATOM_ENABLE);
1276                 break;
1277         }
1278         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1279
1280         r600_hdmi_setmode(encoder, adjusted_mode);
1281 }
1282
1283 static bool
1284 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1285 {
1286         struct drm_device *dev = encoder->dev;
1287         struct radeon_device *rdev = dev->dev_private;
1288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1289         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1290
1291         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1292                                        ATOM_DEVICE_CV_SUPPORT |
1293                                        ATOM_DEVICE_CRT_SUPPORT)) {
1294                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1295                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1296                 uint8_t frev, crev;
1297
1298                 memset(&args, 0, sizeof(args));
1299
1300                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1301
1302                 args.sDacload.ucMisc = 0;
1303
1304                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1305                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1306                         args.sDacload.ucDacType = ATOM_DAC_A;
1307                 else
1308                         args.sDacload.ucDacType = ATOM_DAC_B;
1309
1310                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1311                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1312                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1313                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1314                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1315                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1316                         if (crev >= 3)
1317                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1318                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1319                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1320                         if (crev >= 3)
1321                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1322                 }
1323
1324                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1325
1326                 return true;
1327         } else
1328                 return false;
1329 }
1330
1331 static enum drm_connector_status
1332 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1333 {
1334         struct drm_device *dev = encoder->dev;
1335         struct radeon_device *rdev = dev->dev_private;
1336         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1337         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1338         uint32_t bios_0_scratch;
1339
1340         if (!atombios_dac_load_detect(encoder, connector)) {
1341                 DRM_DEBUG("detect returned false \n");
1342                 return connector_status_unknown;
1343         }
1344
1345         if (rdev->family >= CHIP_R600)
1346                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1347         else
1348                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1349
1350         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1351         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1352                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1353                         return connector_status_connected;
1354         }
1355         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1356                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1357                         return connector_status_connected;
1358         }
1359         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1360                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1361                         return connector_status_connected;
1362         }
1363         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1364                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1365                         return connector_status_connected; /* CTV */
1366                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1367                         return connector_status_connected; /* STV */
1368         }
1369         return connector_status_disconnected;
1370 }
1371
1372 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1373 {
1374         radeon_atom_output_lock(encoder, true);
1375         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1376 }
1377
1378 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1379 {
1380         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1381         radeon_atom_output_lock(encoder, false);
1382 }
1383
1384 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1385 {
1386         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1387         struct radeon_encoder_atom_dig *dig;
1388         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1389
1390         if (radeon_encoder_is_digital(encoder)) {
1391                 dig = radeon_encoder->enc_priv;
1392                 dig->dig_encoder = -1;
1393         }
1394         radeon_encoder->active_device = 0;
1395 }
1396
1397 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1398         .dpms = radeon_atom_encoder_dpms,
1399         .mode_fixup = radeon_atom_mode_fixup,
1400         .prepare = radeon_atom_encoder_prepare,
1401         .mode_set = radeon_atom_encoder_mode_set,
1402         .commit = radeon_atom_encoder_commit,
1403         .disable = radeon_atom_encoder_disable,
1404         /* no detect for TMDS/LVDS yet */
1405 };
1406
1407 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1408         .dpms = radeon_atom_encoder_dpms,
1409         .mode_fixup = radeon_atom_mode_fixup,
1410         .prepare = radeon_atom_encoder_prepare,
1411         .mode_set = radeon_atom_encoder_mode_set,
1412         .commit = radeon_atom_encoder_commit,
1413         .detect = radeon_atom_dac_detect,
1414 };
1415
1416 void radeon_enc_destroy(struct drm_encoder *encoder)
1417 {
1418         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1419         kfree(radeon_encoder->enc_priv);
1420         drm_encoder_cleanup(encoder);
1421         kfree(radeon_encoder);
1422 }
1423
1424 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1425         .destroy = radeon_enc_destroy,
1426 };
1427
1428 struct radeon_encoder_atom_dac *
1429 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1430 {
1431         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1432
1433         if (!dac)
1434                 return NULL;
1435
1436         dac->tv_std = TV_STD_NTSC;
1437         return dac;
1438 }
1439
1440 struct radeon_encoder_atom_dig *
1441 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1442 {
1443         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1444
1445         if (!dig)
1446                 return NULL;
1447
1448         /* coherent mode by default */
1449         dig->coherent_mode = true;
1450         dig->dig_encoder = -1;
1451
1452         return dig;
1453 }
1454
1455 void
1456 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1457 {
1458         struct radeon_device *rdev = dev->dev_private;
1459         struct drm_encoder *encoder;
1460         struct radeon_encoder *radeon_encoder;
1461
1462         /* see if we already added it */
1463         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1464                 radeon_encoder = to_radeon_encoder(encoder);
1465                 if (radeon_encoder->encoder_id == encoder_id) {
1466                         radeon_encoder->devices |= supported_device;
1467                         return;
1468                 }
1469
1470         }
1471
1472         /* add a new one */
1473         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1474         if (!radeon_encoder)
1475                 return;
1476
1477         encoder = &radeon_encoder->base;
1478         if (rdev->flags & RADEON_SINGLE_CRTC)
1479                 encoder->possible_crtcs = 0x1;
1480         else
1481                 encoder->possible_crtcs = 0x3;
1482
1483         radeon_encoder->enc_priv = NULL;
1484
1485         radeon_encoder->encoder_id = encoder_id;
1486         radeon_encoder->devices = supported_device;
1487         radeon_encoder->rmx_type = RMX_OFF;
1488
1489         switch (radeon_encoder->encoder_id) {
1490         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1491         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1492         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1493         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1494                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1495                         radeon_encoder->rmx_type = RMX_FULL;
1496                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1497                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1498                 } else {
1499                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1500                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1501                 }
1502                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1503                 break;
1504         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1505                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1506                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1507                 break;
1508         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1509         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1510         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1511                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1512                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1513                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1514                 break;
1515         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1516         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1517         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1518         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1519         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1520         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1521         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1522                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1523                         radeon_encoder->rmx_type = RMX_FULL;
1524                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1525                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1526                 } else {
1527                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1528                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1529                 }
1530                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1531                 break;
1532         }
1533
1534         r600_hdmi_init(encoder);
1535 }