SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* set the active encoder to connector routing */
 266         radeon_encoder_set_active_device(encoder);
 267         drm_mode_set_crtcinfo(adjusted_mode, 0);
 268
 269         /* hw bug */
 270         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 271             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 272                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 273
 274         /* get the native mode for LVDS */
 275         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 276                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 277                 int mode_id = adjusted_mode->base.id;
 278                 *adjusted_mode = *native_mode;
 279                 if (!ASIC_IS_AVIVO(rdev)) {
 280                         adjusted_mode->hdisplay = mode->hdisplay;
 281                         adjusted_mode->vdisplay = mode->vdisplay;
 282                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 283                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 284                 }
 285                 adjusted_mode->base.id = mode_id;
 286         }
 287
 288         /* get the native mode for TV */
 289         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 290                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 291                 if (tv_dac) {
 292                         if (tv_dac->tv_std == TV_STD_NTSC ||
 293                             tv_dac->tv_std == TV_STD_NTSC_J ||
 294                             tv_dac->tv_std == TV_STD_PAL_M)
 295                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 296                         else
 297                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 298                 }
 299         }
 300
 301         if (ASIC_IS_DCE3(rdev) &&
 302             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 303                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 304                 radeon_dp_set_link_config(connector, mode);
 305         }
 306
 307         return true;
 308 }
 309
 310 static void
 311 atombios_dac_setup(struct drm_encoder *encoder, int action)
 312 {
 313         struct drm_device *dev = encoder->dev;
 314         struct radeon_device *rdev = dev->dev_private;
 315         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 316         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 317         int index = 0, num = 0;
 318         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 319         enum radeon_tv_std tv_std = TV_STD_NTSC;
 320
 321         if (dac_info->tv_std)
 322                 tv_std = dac_info->tv_std;
 323
 324         memset(&args, 0, sizeof(args));
 325
 326         switch (radeon_encoder->encoder_id) {
 327         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 328         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 329                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 330                 num = 1;
 331                 break;
 332         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 333         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 334                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 335                 num = 2;
 336                 break;
 337         }
 338
 339         args.ucAction = action;
 340
 341         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 342                 args.ucDacStandard = ATOM_DAC1_PS2;
 343         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 344                 args.ucDacStandard = ATOM_DAC1_CV;
 345         else {
 346                 switch (tv_std) {
 347                 case TV_STD_PAL:
 348                 case TV_STD_PAL_M:
 349                 case TV_STD_SCART_PAL:
 350                 case TV_STD_SECAM:
 351                 case TV_STD_PAL_CN:
 352                         args.ucDacStandard = ATOM_DAC1_PAL;
 353                         break;
 354                 case TV_STD_NTSC:
 355                 case TV_STD_NTSC_J:
 356                 case TV_STD_PAL_60:
 357                 default:
 358                         args.ucDacStandard = ATOM_DAC1_NTSC;
 359                         break;
 360                 }
 361         }
 362         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 363
 364         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 365
 366 }
 367
 368 static void
 369 atombios_tv_setup(struct drm_encoder *encoder, int action)
 370 {
 371         struct drm_device *dev = encoder->dev;
 372         struct radeon_device *rdev = dev->dev_private;
 373         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 374         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 375         int index = 0;
 376         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 377         enum radeon_tv_std tv_std = TV_STD_NTSC;
 378
 379         if (dac_info->tv_std)
 380                 tv_std = dac_info->tv_std;
 381
 382         memset(&args, 0, sizeof(args));
 383
 384         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 385
 386         args.sTVEncoder.ucAction = action;
 387
 388         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 389                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 390         else {
 391                 switch (tv_std) {
 392                 case TV_STD_NTSC:
 393                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 394                         break;
 395                 case TV_STD_PAL:
 396                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 397                         break;
 398                 case TV_STD_PAL_M:
 399                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 400                         break;
 401                 case TV_STD_PAL_60:
 402                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 403                         break;
 404                 case TV_STD_NTSC_J:
 405                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 406                         break;
 407                 case TV_STD_SCART_PAL:
 408                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 409                         break;
 410                 case TV_STD_SECAM:
 411                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 412                         break;
 413                 case TV_STD_PAL_CN:
 414                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 415                         break;
 416                 default:
 417                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 418                         break;
 419                 }
 420         }
 421
 422         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 423
 424         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 425
 426 }
 427
 428 void
 429 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 430 {
 431         struct drm_device *dev = encoder->dev;
 432         struct radeon_device *rdev = dev->dev_private;
 433         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 434         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 435         int index = 0;
 436
 437         memset(&args, 0, sizeof(args));
 438
 439         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 440
 441         args.sXTmdsEncoder.ucEnable = action;
 442
 443         if (radeon_encoder->pixel_clock > 165000)
 444                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 445
 446         /*if (pScrn->rgbBits == 8)*/
 447         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 448
 449         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 450
 451 }
 452
 453 static void
 454 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 455 {
 456         struct drm_device *dev = encoder->dev;
 457         struct radeon_device *rdev = dev->dev_private;
 458         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 459         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 460         int index = 0;
 461
 462         memset(&args, 0, sizeof(args));
 463
 464         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 465
 466         args.sDVOEncoder.ucAction = action;
 467         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 468
 469         if (radeon_encoder->pixel_clock > 165000)
 470                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 471
 472         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 473
 474 }
 475
 476 union lvds_encoder_control {
 477         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 478         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 479 };
 480
 481 void
 482 atombios_digital_setup(struct drm_encoder *encoder, int action)
 483 {
 484         struct drm_device *dev = encoder->dev;
 485         struct radeon_device *rdev = dev->dev_private;
 486         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 487         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 488         struct radeon_connector_atom_dig *dig_connector =
 489                 radeon_get_atom_connector_priv_from_encoder(encoder);
 490         union lvds_encoder_control args;
 491         int index = 0;
 492         int hdmi_detected = 0;
 493         uint8_t frev, crev;
 494
 495         if (!dig || !dig_connector)
 496                 return;
 497
 498         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 499                 hdmi_detected = 1;
 500
 501         memset(&args, 0, sizeof(args));
 502
 503         switch (radeon_encoder->encoder_id) {
 504         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 505                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 506                 break;
 507         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 508         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 509                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 510                 break;
 511         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 512                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 513                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 514                 else
 515                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 516                 break;
 517         }
 518
 519         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 520
 521         switch (frev) {
 522         case 1:
 523         case 2:
 524                 switch (crev) {
 525                 case 1:
 526                         args.v1.ucMisc = 0;
 527                         args.v1.ucAction = action;
 528                         if (hdmi_detected)
 529                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 530                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 532                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 533                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 534                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 535                                         args.v1.ucMisc |= (1 << 1);
 536                         } else {
 537                                 if (dig_connector->linkb)
 538                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 539                                 if (radeon_encoder->pixel_clock > 165000)
 540                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 541                                 /*if (pScrn->rgbBits == 8) */
 542                                 args.v1.ucMisc |= (1 << 1);
 543                         }
 544                         break;
 545                 case 2:
 546                 case 3:
 547                         args.v2.ucMisc = 0;
 548                         args.v2.ucAction = action;
 549                         if (crev == 3) {
 550                                 if (dig->coherent_mode)
 551                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 552                         }
 553                         if (hdmi_detected)
 554                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 555                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 556                         args.v2.ucTruncate = 0;
 557                         args.v2.ucSpatial = 0;
 558                         args.v2.ucTemporal = 0;
 559                         args.v2.ucFRC = 0;
 560                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 561                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 562                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 563                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 564                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 565                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 566                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 567                                 }
 568                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 569                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 570                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 571                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 572                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 573                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 574                                 }
 575                         } else {
 576                                 if (dig_connector->linkb)
 577                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 578                                 if (radeon_encoder->pixel_clock > 165000)
 579                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 580                         }
 581                         break;
 582                 default:
 583                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 584                         break;
 585                 }
 586                 break;
 587         default:
 588                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 589                 break;
 590         }
 591
 592         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 593         r600_hdmi_enable(encoder, hdmi_detected);
 594 }
 595
 596 int
 597 atombios_get_encoder_mode(struct drm_encoder *encoder)
 598 {
 599         struct drm_connector *connector;
 600         struct radeon_connector *radeon_connector;
 601         struct radeon_connector_atom_dig *dig_connector;
 602
 603         connector = radeon_get_connector_for_encoder(encoder);
 604         if (!connector)
 605                 return 0;
 606
 607         radeon_connector = to_radeon_connector(connector);
 608
 609         switch (connector->connector_type) {
 610         case DRM_MODE_CONNECTOR_DVII:
 611         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 612                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 613                         return ATOM_ENCODER_MODE_HDMI;
 614                 else if (radeon_connector->use_digital)
 615                         return ATOM_ENCODER_MODE_DVI;
 616                 else
 617                         return ATOM_ENCODER_MODE_CRT;
 618                 break;
 619         case DRM_MODE_CONNECTOR_DVID:
 620         case DRM_MODE_CONNECTOR_HDMIA:
 621         default:
 622                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 623                         return ATOM_ENCODER_MODE_HDMI;
 624                 else
 625                         return ATOM_ENCODER_MODE_DVI;
 626                 break;
 627         case DRM_MODE_CONNECTOR_LVDS:
 628                 return ATOM_ENCODER_MODE_LVDS;
 629                 break;
 630         case DRM_MODE_CONNECTOR_DisplayPort:
 631         case DRM_MODE_CONNECTOR_eDP:
 632                 dig_connector = radeon_connector->con_priv;
 633                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 634                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 635                         return ATOM_ENCODER_MODE_DP;
 636                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 637                         return ATOM_ENCODER_MODE_HDMI;
 638                 else
 639                         return ATOM_ENCODER_MODE_DVI;
 640                 break;
 641         case DRM_MODE_CONNECTOR_DVIA:
 642         case DRM_MODE_CONNECTOR_VGA:
 643                 return ATOM_ENCODER_MODE_CRT;
 644                 break;
 645         case DRM_MODE_CONNECTOR_Composite:
 646         case DRM_MODE_CONNECTOR_SVIDEO:
 647         case DRM_MODE_CONNECTOR_9PinDIN:
 648                 /* fix me */
 649                 return ATOM_ENCODER_MODE_TV;
 650                 /*return ATOM_ENCODER_MODE_CV;*/
 651                 break;
 652         }
 653 }
 654
 655 /*
 656  * DIG Encoder/Transmitter Setup
 657  *
 658  * DCE 3.0/3.1
 659  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 660  * Supports up to 3 digital outputs
 661  * - 2 DIG encoder blocks.
 662  * DIG1 can drive UNIPHY link A or link B
 663  * DIG2 can drive UNIPHY link B or LVTMA
 664  *
 665  * DCE 3.2
 666  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 667  * Supports up to 5 digital outputs
 668  * - 2 DIG encoder blocks.
 669  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 670  *
 671  * Routing
 672  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 673  * Examples:
 674  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 675  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 676  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 677  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 678  */
 679 static void
 680 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 681 {
 682         struct drm_device *dev = encoder->dev;
 683         struct radeon_device *rdev = dev->dev_private;
 684         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 685         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 686         struct radeon_connector_atom_dig *dig_connector =
 687                 radeon_get_atom_connector_priv_from_encoder(encoder);
 688         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 689         int index = 0, num = 0;
 690         uint8_t frev, crev;
 691
 692         if (!dig || !dig_connector)
 693                 return;
 694
 695         memset(&args, 0, sizeof(args));
 696
 697         if (dig->dig_encoder)
 698                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 699         else
 700                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 701         num = dig->dig_encoder + 1;
 702
 703         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 704
 705         args.ucAction = action;
 706         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 707
 708         if (ASIC_IS_DCE32(rdev)) {
 709                 switch (radeon_encoder->encoder_id) {
 710                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 711                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 712                         break;
 713                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 714                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 715                         break;
 716                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 717                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 718                         break;
 719                 }
 720         } else {
 721                 switch (radeon_encoder->encoder_id) {
 722                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 723                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 724                         break;
 725                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 726                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 727                         break;
 728                 }
 729         }
 730
 731         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 732
 733         if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 734                 if (dig_connector->dp_clock == 270000)
 735                         args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 736                 args.ucLaneNum = dig_connector->dp_lane_count;
 737         } else if (radeon_encoder->pixel_clock > 165000)
 738                 args.ucLaneNum = 8;
 739         else
 740                 args.ucLaneNum = 4;
 741
 742         if (dig_connector->linkb)
 743                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 744         else
 745                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 746
 747         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 748
 749 }
 750
 751 union dig_transmitter_control {
 752         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 753         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 754 };
 755
 756 void
 757 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 758 {
 759         struct drm_device *dev = encoder->dev;
 760         struct radeon_device *rdev = dev->dev_private;
 761         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 762         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 763         struct radeon_connector_atom_dig *dig_connector =
 764                 radeon_get_atom_connector_priv_from_encoder(encoder);
 765         struct drm_connector *connector;
 766         struct radeon_connector *radeon_connector;
 767         union dig_transmitter_control args;
 768         int index = 0, num = 0;
 769         uint8_t frev, crev;
 770         bool is_dp = false;
 771
 772         if (!dig || !dig_connector)
 773                 return;
 774
 775         connector = radeon_get_connector_for_encoder(encoder);
 776         radeon_connector = to_radeon_connector(connector);
 777
 778         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 779                 is_dp = true;
 780
 781         memset(&args, 0, sizeof(args));
 782
 783         if (ASIC_IS_DCE32(rdev))
 784                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 785         else {
 786                 switch (radeon_encoder->encoder_id) {
 787                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 788                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 789                         break;
 790                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 791                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 792                         break;
 793                 }
 794         }
 795
 796         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 797
 798         args.v1.ucAction = action;
 799         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 800                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 801         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 802                 args.v1.asMode.ucLaneSel = lane_num;
 803                 args.v1.asMode.ucLaneSet = lane_set;
 804         } else {
 805                 if (is_dp)
 806                         args.v1.usPixelClock =
 807                                 cpu_to_le16(dig_connector->dp_clock / 10);
 808                 else if (radeon_encoder->pixel_clock > 165000)
 809                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 810                 else
 811                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 812         }
 813         if (ASIC_IS_DCE32(rdev)) {
 814                 if (dig->dig_encoder == 1)
 815                         args.v2.acConfig.ucEncoderSel = 1;
 816                 if (dig_connector->linkb)
 817                         args.v2.acConfig.ucLinkSel = 1;
 818
 819                 switch (radeon_encoder->encoder_id) {
 820                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 821                         args.v2.acConfig.ucTransmitterSel = 0;
 822                         num = 0;
 823                         break;
 824                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 825                         args.v2.acConfig.ucTransmitterSel = 1;
 826                         num = 1;
 827                         break;
 828                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 829                         args.v2.acConfig.ucTransmitterSel = 2;
 830                         num = 2;
 831                         break;
 832                 }
 833
 834                 if (is_dp)
 835                         args.v2.acConfig.fCoherentMode = 1;
 836                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 837                         if (dig->coherent_mode)
 838                                 args.v2.acConfig.fCoherentMode = 1;
 839                 }
 840         } else {
 841
 842                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 843
 844                 if (dig->dig_encoder)
 845                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 846                 else
 847                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 848
 849                 switch (radeon_encoder->encoder_id) {
 850                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 851                         if (rdev->flags & RADEON_IS_IGP) {
 852                                 if (radeon_encoder->pixel_clock > 165000) {
 853                                         if (dig_connector->igp_lane_info & 0x3)
 854                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 855                                         else if (dig_connector->igp_lane_info & 0xc)
 856                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 857                                 } else {
 858                                         if (dig_connector->igp_lane_info & 0x1)
 859                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 860                                         else if (dig_connector->igp_lane_info & 0x2)
 861                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 862                                         else if (dig_connector->igp_lane_info & 0x4)
 863                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 864                                         else if (dig_connector->igp_lane_info & 0x8)
 865                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 866                                 }
 867                         }
 868                         break;
 869                 }
 870
 871                 if (radeon_encoder->pixel_clock > 165000)
 872                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 873
 874                 if (dig_connector->linkb)
 875                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 876                 else
 877                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 878
 879                 if (is_dp)
 880                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 881                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 882                         if (dig->coherent_mode)
 883                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 884                 }
 885         }
 886
 887         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 888 }
 889
 890 static void
 891 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 892 {
 893         struct drm_device *dev = encoder->dev;
 894         struct radeon_device *rdev = dev->dev_private;
 895         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 896         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 897         ENABLE_YUV_PS_ALLOCATION args;
 898         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 899         uint32_t temp, reg;
 900
 901         memset(&args, 0, sizeof(args));
 902
 903         if (rdev->family >= CHIP_R600)
 904                 reg = R600_BIOS_3_SCRATCH;
 905         else
 906                 reg = RADEON_BIOS_3_SCRATCH;
 907
 908         /* XXX: fix up scratch reg handling */
 909         temp = RREG32(reg);
 910         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 911                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 912                              (radeon_crtc->crtc_id << 18)));
 913         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 914                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 915         else
 916                 WREG32(reg, 0);
 917
 918         if (enable)
 919                 args.ucEnable = ATOM_ENABLE;
 920         args.ucCRTC = radeon_crtc->crtc_id;
 921
 922         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 923
 924         WREG32(reg, temp);
 925 }
 926
 927 static void
 928 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 929 {
 930         struct drm_device *dev = encoder->dev;
 931         struct radeon_device *rdev = dev->dev_private;
 932         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 933         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 934         int index = 0;
 935         bool is_dig = false;
 936
 937         memset(&args, 0, sizeof(args));
 938
 939         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 940                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 941                   radeon_encoder->active_device);
 942         switch (radeon_encoder->encoder_id) {
 943         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 944         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 945                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 946                 break;
 947         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 948         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 949         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 950         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 951                 is_dig = true;
 952                 break;
 953         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 954         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 955         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 956                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 957                 break;
 958         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 959                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 960                 break;
 961         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 962                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 963                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 964                 else
 965                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 966                 break;
 967         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 968         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 969                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 970                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 971                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 972                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 973                 else
 974                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 975                 break;
 976         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 977         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 978                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 979                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 980                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 981                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 982                 else
 983                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 984                 break;
 985         }
 986
 987         if (is_dig) {
 988                 switch (mode) {
 989                 case DRM_MODE_DPMS_ON:
 990                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
 991                         {
 992                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 993                                 dp_link_train(encoder, connector);
 994                         }
 995                         break;
 996                 case DRM_MODE_DPMS_STANDBY:
 997                 case DRM_MODE_DPMS_SUSPEND:
 998                 case DRM_MODE_DPMS_OFF:
 999                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1000                         break;
1001                 }
1002         } else {
1003                 switch (mode) {
1004                 case DRM_MODE_DPMS_ON:
1005                         args.ucAction = ATOM_ENABLE;
1006                         break;
1007                 case DRM_MODE_DPMS_STANDBY:
1008                 case DRM_MODE_DPMS_SUSPEND:
1009                 case DRM_MODE_DPMS_OFF:
1010                         args.ucAction = ATOM_DISABLE;
1011                         break;
1012                 }
1013                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1014         }
1015         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1016 }
1017
1018 union crtc_source_param {
1019         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1020         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1021 };
1022
1023 static void
1024 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1025 {
1026         struct drm_device *dev = encoder->dev;
1027         struct radeon_device *rdev = dev->dev_private;
1028         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1029         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1030         union crtc_source_param args;
1031         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1032         uint8_t frev, crev;
1033         struct radeon_encoder_atom_dig *dig;
1034
1035         memset(&args, 0, sizeof(args));
1036
1037         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1038
1039         switch (frev) {
1040         case 1:
1041                 switch (crev) {
1042                 case 1:
1043                 default:
1044                         if (ASIC_IS_AVIVO(rdev))
1045                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1046                         else {
1047                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1048                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1049                                 } else {
1050                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1051                                 }
1052                         }
1053                         switch (radeon_encoder->encoder_id) {
1054                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1055                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1056                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1057                                 break;
1058                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1059                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1060                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1061                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1062                                 else
1063                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1064                                 break;
1065                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1066                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1067                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1068                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1069                                 break;
1070                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1071                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1072                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1073                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1074                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1075                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1076                                 else
1077                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1078                                 break;
1079                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1080                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1081                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1082                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1083                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1084                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1085                                 else
1086                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1087                                 break;
1088                         }
1089                         break;
1090                 case 2:
1091                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1092                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1093                         switch (radeon_encoder->encoder_id) {
1094                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1095                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1096                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1097                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1098                                 dig = radeon_encoder->enc_priv;
1099                                 if (dig->dig_encoder)
1100                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1101                                 else
1102                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1103                                 break;
1104                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1105                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1106                                 break;
1107                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1108                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1109                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1110                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1111                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1112                                 else
1113                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1114                                 break;
1115                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1116                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1117                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1118                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1119                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1120                                 else
1121                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1122                                 break;
1123                         }
1124                         break;
1125                 }
1126                 break;
1127         default:
1128                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1129                 break;
1130         }
1131
1132         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1133 }
1134
1135 static void
1136 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1137                               struct drm_display_mode *mode)
1138 {
1139         struct drm_device *dev = encoder->dev;
1140         struct radeon_device *rdev = dev->dev_private;
1141         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1142         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1143
1144         /* Funky macbooks */
1145         if ((dev->pdev->device == 0x71C5) &&
1146             (dev->pdev->subsystem_vendor == 0x106b) &&
1147             (dev->pdev->subsystem_device == 0x0080)) {
1148                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1149                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1150
1151                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1152                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1153
1154                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1155                 }
1156         }
1157
1158         /* set scaler clears this on some chips */
1159         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1160                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1161                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1162                                AVIVO_D1MODE_INTERLEAVE_EN);
1163         }
1164 }
1165
1166 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1167 {
1168         struct drm_device *dev = encoder->dev;
1169         struct radeon_device *rdev = dev->dev_private;
1170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1171         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1172         struct drm_encoder *test_encoder;
1173         struct radeon_encoder_atom_dig *dig;
1174         uint32_t dig_enc_in_use = 0;
1175         /* on DCE32 and encoder can driver any block so just crtc id */
1176         if (ASIC_IS_DCE32(rdev)) {
1177                 return radeon_crtc->crtc_id;
1178         }
1179
1180         /* on DCE3 - LVTMA can only be driven by DIGB */
1181         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1182                 struct radeon_encoder *radeon_test_encoder;
1183
1184                 if (encoder == test_encoder)
1185                         continue;
1186
1187                 if (!radeon_encoder_is_digital(test_encoder))
1188                         continue;
1189
1190                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1191                 dig = radeon_test_encoder->enc_priv;
1192
1193                 if (dig->dig_encoder >= 0)
1194                         dig_enc_in_use |= (1 << dig->dig_encoder);
1195         }
1196
1197         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1198                 if (dig_enc_in_use & 0x2)
1199                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1200                 return 1;
1201         }
1202         if (!(dig_enc_in_use & 1))
1203                 return 0;
1204         return 1;
1205 }
1206
1207 static void
1208 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1209                              struct drm_display_mode *mode,
1210                              struct drm_display_mode *adjusted_mode)
1211 {
1212         struct drm_device *dev = encoder->dev;
1213         struct radeon_device *rdev = dev->dev_private;
1214         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1215         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1216
1217         if (radeon_encoder->active_device &
1218             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1219                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1220                 if (dig)
1221                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1222         }
1223         radeon_encoder->pixel_clock = adjusted_mode->clock;
1224
1225         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1226         atombios_set_encoder_crtc_source(encoder);
1227
1228         if (ASIC_IS_AVIVO(rdev)) {
1229                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1230                         atombios_yuv_setup(encoder, true);
1231                 else
1232                         atombios_yuv_setup(encoder, false);
1233         }
1234
1235         switch (radeon_encoder->encoder_id) {
1236         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1237         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1238         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1239         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1240                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1241                 break;
1242         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1243         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1244         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1245         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1246                 /* disable the encoder and transmitter */
1247                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1248                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1249
1250                 /* setup and enable the encoder and transmitter */
1251                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1252                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1253                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1254                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1255                 break;
1256         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1257                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1258                 break;
1259         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1260         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1261                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1262                 break;
1263         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1264         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1265         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1266         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1267                 atombios_dac_setup(encoder, ATOM_ENABLE);
1268                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1269                         atombios_tv_setup(encoder, ATOM_ENABLE);
1270                 break;
1271         }
1272         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1273
1274         r600_hdmi_setmode(encoder, adjusted_mode);
1275 }
1276
1277 static bool
1278 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1279 {
1280         struct drm_device *dev = encoder->dev;
1281         struct radeon_device *rdev = dev->dev_private;
1282         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1283         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1284
1285         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1286                                        ATOM_DEVICE_CV_SUPPORT |
1287                                        ATOM_DEVICE_CRT_SUPPORT)) {
1288                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1289                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1290                 uint8_t frev, crev;
1291
1292                 memset(&args, 0, sizeof(args));
1293
1294                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1295
1296                 args.sDacload.ucMisc = 0;
1297
1298                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1299                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1300                         args.sDacload.ucDacType = ATOM_DAC_A;
1301                 else
1302                         args.sDacload.ucDacType = ATOM_DAC_B;
1303
1304                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1305                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1306                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1307                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1308                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1309                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1310                         if (crev >= 3)
1311                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1312                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1313                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1314                         if (crev >= 3)
1315                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1316                 }
1317
1318                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1319
1320                 return true;
1321         } else
1322                 return false;
1323 }
1324
1325 static enum drm_connector_status
1326 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1327 {
1328         struct drm_device *dev = encoder->dev;
1329         struct radeon_device *rdev = dev->dev_private;
1330         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1331         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1332         uint32_t bios_0_scratch;
1333
1334         if (!atombios_dac_load_detect(encoder, connector)) {
1335                 DRM_DEBUG("detect returned false \n");
1336                 return connector_status_unknown;
1337         }
1338
1339         if (rdev->family >= CHIP_R600)
1340                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1341         else
1342                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1343
1344         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1345         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1346                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1347                         return connector_status_connected;
1348         }
1349         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1350                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1351                         return connector_status_connected;
1352         }
1353         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1354                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1355                         return connector_status_connected;
1356         }
1357         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1358                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1359                         return connector_status_connected; /* CTV */
1360                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1361                         return connector_status_connected; /* STV */
1362         }
1363         return connector_status_disconnected;
1364 }
1365
1366 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1367 {
1368         radeon_atom_output_lock(encoder, true);
1369         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1370 }
1371
1372 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1373 {
1374         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1375         radeon_atom_output_lock(encoder, false);
1376 }
1377
1378 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1379 {
1380         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1381         struct radeon_encoder_atom_dig *dig;
1382         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1383
1384         if (radeon_encoder_is_digital(encoder)) {
1385                 dig = radeon_encoder->enc_priv;
1386                 dig->dig_encoder = -1;
1387         }
1388         radeon_encoder->active_device = 0;
1389 }
1390
1391 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1392         .dpms = radeon_atom_encoder_dpms,
1393         .mode_fixup = radeon_atom_mode_fixup,
1394         .prepare = radeon_atom_encoder_prepare,
1395         .mode_set = radeon_atom_encoder_mode_set,
1396         .commit = radeon_atom_encoder_commit,
1397         .disable = radeon_atom_encoder_disable,
1398         /* no detect for TMDS/LVDS yet */
1399 };
1400
1401 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1402         .dpms = radeon_atom_encoder_dpms,
1403         .mode_fixup = radeon_atom_mode_fixup,
1404         .prepare = radeon_atom_encoder_prepare,
1405         .mode_set = radeon_atom_encoder_mode_set,
1406         .commit = radeon_atom_encoder_commit,
1407         .detect = radeon_atom_dac_detect,
1408 };
1409
1410 void radeon_enc_destroy(struct drm_encoder *encoder)
1411 {
1412         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1413         kfree(radeon_encoder->enc_priv);
1414         drm_encoder_cleanup(encoder);
1415         kfree(radeon_encoder);
1416 }
1417
1418 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1419         .destroy = radeon_enc_destroy,
1420 };
1421
1422 struct radeon_encoder_atom_dac *
1423 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1424 {
1425         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1426
1427         if (!dac)
1428                 return NULL;
1429
1430         dac->tv_std = TV_STD_NTSC;
1431         return dac;
1432 }
1433
1434 struct radeon_encoder_atom_dig *
1435 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1436 {
1437         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1438
1439         if (!dig)
1440                 return NULL;
1441
1442         /* coherent mode by default */
1443         dig->coherent_mode = true;
1444         dig->dig_encoder = -1;
1445
1446         return dig;
1447 }
1448
1449 void
1450 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1451 {
1452         struct radeon_device *rdev = dev->dev_private;
1453         struct drm_encoder *encoder;
1454         struct radeon_encoder *radeon_encoder;
1455
1456         /* see if we already added it */
1457         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1458                 radeon_encoder = to_radeon_encoder(encoder);
1459                 if (radeon_encoder->encoder_id == encoder_id) {
1460                         radeon_encoder->devices |= supported_device;
1461                         return;
1462                 }
1463
1464         }
1465
1466         /* add a new one */
1467         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1468         if (!radeon_encoder)
1469                 return;
1470
1471         encoder = &radeon_encoder->base;
1472         if (rdev->flags & RADEON_SINGLE_CRTC)
1473                 encoder->possible_crtcs = 0x1;
1474         else
1475                 encoder->possible_crtcs = 0x3;
1476
1477         radeon_encoder->enc_priv = NULL;
1478
1479         radeon_encoder->encoder_id = encoder_id;
1480         radeon_encoder->devices = supported_device;
1481         radeon_encoder->rmx_type = RMX_OFF;
1482
1483         switch (radeon_encoder->encoder_id) {
1484         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1485         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1486         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1487         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1488                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1489                         radeon_encoder->rmx_type = RMX_FULL;
1490                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1491                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1492                 } else {
1493                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1494                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1495                 }
1496                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1497                 break;
1498         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1499                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1500                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1501                 break;
1502         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1503         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1504         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1505                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1506                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1507                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1508                 break;
1509         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1510         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1511         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1512         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1513         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1514         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1515         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1516                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1517                         radeon_encoder->rmx_type = RMX_FULL;
1518                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1519                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1520                 } else {
1521                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1522                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1523                 }
1524                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1525                 break;
1526         }
1527
1528         r600_hdmi_init(encoder);
1529 }