SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 void
 160 radeon_link_encoder_connector(struct drm_device *dev)
 161 {
 162         struct drm_connector *connector;
 163         struct radeon_connector *radeon_connector;
 164         struct drm_encoder *encoder;
 165         struct radeon_encoder *radeon_encoder;
 166
 167         /* walk the list and link encoders to connectors */
 168         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 169                 radeon_connector = to_radeon_connector(connector);
 170                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 171                         radeon_encoder = to_radeon_encoder(encoder);
 172                         if (radeon_encoder->devices & radeon_connector->devices)
 173                                 drm_mode_connector_attach_encoder(connector, encoder);
 174                 }
 175         }
 176 }
 177
 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 179 {
 180         struct drm_device *dev = encoder->dev;
 181         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 182         struct drm_connector *connector;
 183
 184         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 185                 if (connector->encoder == encoder) {
 186                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 187                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 188                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 189                                   radeon_encoder->active_device, radeon_encoder->devices,
 190                                   radeon_connector->devices, encoder->encoder_type);
 191                 }
 192         }
 193 }
 194
 195 static struct drm_connector *
 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 197 {
 198         struct drm_device *dev = encoder->dev;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct drm_connector *connector;
 201         struct radeon_connector *radeon_connector;
 202
 203         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 204                 radeon_connector = to_radeon_connector(connector);
 205                 if (radeon_encoder->devices & radeon_connector->devices)
 206                         return connector;
 207         }
 208         return NULL;
 209 }
 210
 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 212                                    struct drm_display_mode *mode,
 213                                    struct drm_display_mode *adjusted_mode)
 214 {
 215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 216         struct drm_device *dev = encoder->dev;
 217         struct radeon_device *rdev = dev->dev_private;
 218
 219         /* set the active encoder to connector routing */
 220         radeon_encoder_set_active_device(encoder);
 221         drm_mode_set_crtcinfo(adjusted_mode, 0);
 222
 223         /* hw bug */
 224         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 225             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 226                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 227
 228         /* get the native mode for LVDS */
 229         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 230                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 231                 int mode_id = adjusted_mode->base.id;
 232                 *adjusted_mode = *native_mode;
 233                 if (!ASIC_IS_AVIVO(rdev)) {
 234                         adjusted_mode->hdisplay = mode->hdisplay;
 235                         adjusted_mode->vdisplay = mode->vdisplay;
 236                 }
 237                 adjusted_mode->base.id = mode_id;
 238         }
 239
 240         /* get the native mode for TV */
 241         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 242                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 243                 if (tv_dac) {
 244                         if (tv_dac->tv_std == TV_STD_NTSC ||
 245                             tv_dac->tv_std == TV_STD_NTSC_J ||
 246                             tv_dac->tv_std == TV_STD_PAL_M)
 247                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 248                         else
 249                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 250                 }
 251         }
 252
 253         return true;
 254 }
 255
 256 static void
 257 atombios_dac_setup(struct drm_encoder *encoder, int action)
 258 {
 259         struct drm_device *dev = encoder->dev;
 260         struct radeon_device *rdev = dev->dev_private;
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 263         int index = 0, num = 0;
 264         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 265         enum radeon_tv_std tv_std = TV_STD_NTSC;
 266
 267         if (dac_info->tv_std)
 268                 tv_std = dac_info->tv_std;
 269
 270         memset(&args, 0, sizeof(args));
 271
 272         switch (radeon_encoder->encoder_id) {
 273         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 274         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 275                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 276                 num = 1;
 277                 break;
 278         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 279         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 280                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 281                 num = 2;
 282                 break;
 283         }
 284
 285         args.ucAction = action;
 286
 287         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 288                 args.ucDacStandard = ATOM_DAC1_PS2;
 289         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 290                 args.ucDacStandard = ATOM_DAC1_CV;
 291         else {
 292                 switch (tv_std) {
 293                 case TV_STD_PAL:
 294                 case TV_STD_PAL_M:
 295                 case TV_STD_SCART_PAL:
 296                 case TV_STD_SECAM:
 297                 case TV_STD_PAL_CN:
 298                         args.ucDacStandard = ATOM_DAC1_PAL;
 299                         break;
 300                 case TV_STD_NTSC:
 301                 case TV_STD_NTSC_J:
 302                 case TV_STD_PAL_60:
 303                 default:
 304                         args.ucDacStandard = ATOM_DAC1_NTSC;
 305                         break;
 306                 }
 307         }
 308         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 309
 310         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 311
 312 }
 313
 314 static void
 315 atombios_tv_setup(struct drm_encoder *encoder, int action)
 316 {
 317         struct drm_device *dev = encoder->dev;
 318         struct radeon_device *rdev = dev->dev_private;
 319         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 320         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 321         int index = 0;
 322         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 323         enum radeon_tv_std tv_std = TV_STD_NTSC;
 324
 325         if (dac_info->tv_std)
 326                 tv_std = dac_info->tv_std;
 327
 328         memset(&args, 0, sizeof(args));
 329
 330         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 331
 332         args.sTVEncoder.ucAction = action;
 333
 334         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 335                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 336         else {
 337                 switch (tv_std) {
 338                 case TV_STD_NTSC:
 339                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 340                         break;
 341                 case TV_STD_PAL:
 342                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 343                         break;
 344                 case TV_STD_PAL_M:
 345                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 346                         break;
 347                 case TV_STD_PAL_60:
 348                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 349                         break;
 350                 case TV_STD_NTSC_J:
 351                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 352                         break;
 353                 case TV_STD_SCART_PAL:
 354                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 355                         break;
 356                 case TV_STD_SECAM:
 357                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 358                         break;
 359                 case TV_STD_PAL_CN:
 360                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 361                         break;
 362                 default:
 363                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 364                         break;
 365                 }
 366         }
 367
 368         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 369
 370         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 371
 372 }
 373
 374 void
 375 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 376 {
 377         struct drm_device *dev = encoder->dev;
 378         struct radeon_device *rdev = dev->dev_private;
 379         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 380         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 381         int index = 0;
 382
 383         memset(&args, 0, sizeof(args));
 384
 385         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 386
 387         args.sXTmdsEncoder.ucEnable = action;
 388
 389         if (radeon_encoder->pixel_clock > 165000)
 390                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 391
 392         /*if (pScrn->rgbBits == 8)*/
 393         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 394
 395         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 396
 397 }
 398
 399 static void
 400 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 401 {
 402         struct drm_device *dev = encoder->dev;
 403         struct radeon_device *rdev = dev->dev_private;
 404         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 405         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 406         int index = 0;
 407
 408         memset(&args, 0, sizeof(args));
 409
 410         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 411
 412         args.sDVOEncoder.ucAction = action;
 413         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 414
 415         if (radeon_encoder->pixel_clock > 165000)
 416                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 417
 418         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 419
 420 }
 421
 422 union lvds_encoder_control {
 423         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 424         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 425 };
 426
 427 void
 428 atombios_digital_setup(struct drm_encoder *encoder, int action)
 429 {
 430         struct drm_device *dev = encoder->dev;
 431         struct radeon_device *rdev = dev->dev_private;
 432         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 433         union lvds_encoder_control args;
 434         int index = 0;
 435         uint8_t frev, crev;
 436         struct radeon_encoder_atom_dig *dig;
 437         struct drm_connector *connector;
 438         struct radeon_connector *radeon_connector;
 439         struct radeon_connector_atom_dig *dig_connector;
 440
 441         connector = radeon_get_connector_for_encoder(encoder);
 442         if (!connector)
 443                 return;
 444
 445         radeon_connector = to_radeon_connector(connector);
 446
 447         if (!radeon_encoder->enc_priv)
 448                 return;
 449
 450         dig = radeon_encoder->enc_priv;
 451
 452         if (!radeon_connector->con_priv)
 453                 return;
 454
 455         dig_connector = radeon_connector->con_priv;
 456
 457         memset(&args, 0, sizeof(args));
 458
 459         switch (radeon_encoder->encoder_id) {
 460         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 461                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 462                 break;
 463         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 464         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 465                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 466                 break;
 467         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 468                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 469                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 470                 else
 471                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 472                 break;
 473         }
 474
 475         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 476
 477         switch (frev) {
 478         case 1:
 479         case 2:
 480                 switch (crev) {
 481                 case 1:
 482                         args.v1.ucMisc = 0;
 483                         args.v1.ucAction = action;
 484                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 485                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 486                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 487                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 488                                 if (dig->lvds_misc & (1 << 0))
 489                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 490                                 if (dig->lvds_misc & (1 << 1))
 491                                         args.v1.ucMisc |= (1 << 1);
 492                         } else {
 493                                 if (dig_connector->linkb)
 494                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 495                                 if (radeon_encoder->pixel_clock > 165000)
 496                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 497                                 /*if (pScrn->rgbBits == 8) */
 498                                 args.v1.ucMisc |= (1 << 1);
 499                         }
 500                         break;
 501                 case 2:
 502                 case 3:
 503                         args.v2.ucMisc = 0;
 504                         args.v2.ucAction = action;
 505                         if (crev == 3) {
 506                                 if (dig->coherent_mode)
 507                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 508                         }
 509                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 510                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 511                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 512                         args.v2.ucTruncate = 0;
 513                         args.v2.ucSpatial = 0;
 514                         args.v2.ucTemporal = 0;
 515                         args.v2.ucFRC = 0;
 516                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 517                                 if (dig->lvds_misc & (1 << 0))
 518                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 519                                 if (dig->lvds_misc & (1 << 5)) {
 520                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 521                                         if (dig->lvds_misc & (1 << 1))
 522                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 523                                 }
 524                                 if (dig->lvds_misc & (1 << 6)) {
 525                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 526                                         if (dig->lvds_misc & (1 << 1))
 527                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 528                                         if (((dig->lvds_misc >> 2) & 0x3) == 2)
 529                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 530                                 }
 531                         } else {
 532                                 if (dig_connector->linkb)
 533                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 534                                 if (radeon_encoder->pixel_clock > 165000)
 535                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 536                         }
 537                         break;
 538                 default:
 539                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 540                         break;
 541                 }
 542                 break;
 543         default:
 544                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 545                 break;
 546         }
 547
 548         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 549
 550 }
 551
 552 int
 553 atombios_get_encoder_mode(struct drm_encoder *encoder)
 554 {
 555         struct drm_connector *connector;
 556         struct radeon_connector *radeon_connector;
 557
 558         connector = radeon_get_connector_for_encoder(encoder);
 559         if (!connector)
 560                 return 0;
 561
 562         radeon_connector = to_radeon_connector(connector);
 563
 564         switch (connector->connector_type) {
 565         case DRM_MODE_CONNECTOR_DVII:
 566         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 567                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 568                         return ATOM_ENCODER_MODE_HDMI;
 569                 else if (radeon_connector->use_digital)
 570                         return ATOM_ENCODER_MODE_DVI;
 571                 else
 572                         return ATOM_ENCODER_MODE_CRT;
 573                 break;
 574         case DRM_MODE_CONNECTOR_DVID:
 575         case DRM_MODE_CONNECTOR_HDMIA:
 576         default:
 577                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 578                         return ATOM_ENCODER_MODE_HDMI;
 579                 else
 580                         return ATOM_ENCODER_MODE_DVI;
 581                 break;
 582         case DRM_MODE_CONNECTOR_LVDS:
 583                 return ATOM_ENCODER_MODE_LVDS;
 584                 break;
 585         case DRM_MODE_CONNECTOR_DisplayPort:
 586                 /*if (radeon_output->MonType == MT_DP)
 587                   return ATOM_ENCODER_MODE_DP;
 588                   else*/
 589                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 590                         return ATOM_ENCODER_MODE_HDMI;
 591                 else
 592                         return ATOM_ENCODER_MODE_DVI;
 593                 break;
 594         case CONNECTOR_DVI_A:
 595         case CONNECTOR_VGA:
 596                 return ATOM_ENCODER_MODE_CRT;
 597                 break;
 598         case CONNECTOR_STV:
 599         case CONNECTOR_CTV:
 600         case CONNECTOR_DIN:
 601                 /* fix me */
 602                 return ATOM_ENCODER_MODE_TV;
 603                 /*return ATOM_ENCODER_MODE_CV;*/
 604                 break;
 605         }
 606 }
 607
 608 static void
 609 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 610 {
 611         struct drm_device *dev = encoder->dev;
 612         struct radeon_device *rdev = dev->dev_private;
 613         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 614         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 615         int index = 0, num = 0;
 616         uint8_t frev, crev;
 617         struct radeon_encoder_atom_dig *dig;
 618         struct drm_connector *connector;
 619         struct radeon_connector *radeon_connector;
 620         struct radeon_connector_atom_dig *dig_connector;
 621
 622         connector = radeon_get_connector_for_encoder(encoder);
 623         if (!connector)
 624                 return;
 625
 626         radeon_connector = to_radeon_connector(connector);
 627
 628         if (!radeon_connector->con_priv)
 629                 return;
 630
 631         dig_connector = radeon_connector->con_priv;
 632
 633         if (!radeon_encoder->enc_priv)
 634                 return;
 635
 636         dig = radeon_encoder->enc_priv;
 637
 638         memset(&args, 0, sizeof(args));
 639
 640         if (ASIC_IS_DCE32(rdev)) {
 641                 if (dig->dig_block)
 642                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 643                 else
 644                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 645                 num = dig->dig_block + 1;
 646         } else {
 647                 switch (radeon_encoder->encoder_id) {
 648                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 649                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 650                         num = 1;
 651                         break;
 652                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 653                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 654                         num = 2;
 655                         break;
 656                 }
 657         }
 658
 659         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 660
 661         args.ucAction = action;
 662         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 663
 664         if (ASIC_IS_DCE32(rdev)) {
 665                 switch (radeon_encoder->encoder_id) {
 666                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 667                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 668                         break;
 669                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 670                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 671                         break;
 672                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 673                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 674                         break;
 675                 }
 676         } else {
 677                 switch (radeon_encoder->encoder_id) {
 678                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 679                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 680                         break;
 681                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 682                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 683                         break;
 684                 }
 685         }
 686
 687         if (radeon_encoder->pixel_clock > 165000) {
 688                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
 689                 args.ucLaneNum = 8;
 690         } else {
 691                 if (dig_connector->linkb)
 692                         args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 693                 else
 694                         args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 695                 args.ucLaneNum = 4;
 696         }
 697
 698         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 699
 700         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 701
 702 }
 703
 704 union dig_transmitter_control {
 705         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 706         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 707 };
 708
 709 static void
 710 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
 711 {
 712         struct drm_device *dev = encoder->dev;
 713         struct radeon_device *rdev = dev->dev_private;
 714         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 715         union dig_transmitter_control args;
 716         int index = 0, num = 0;
 717         uint8_t frev, crev;
 718         struct radeon_encoder_atom_dig *dig;
 719         struct drm_connector *connector;
 720         struct radeon_connector *radeon_connector;
 721         struct radeon_connector_atom_dig *dig_connector;
 722
 723         connector = radeon_get_connector_for_encoder(encoder);
 724         if (!connector)
 725                 return;
 726
 727         radeon_connector = to_radeon_connector(connector);
 728
 729         if (!radeon_encoder->enc_priv)
 730                 return;
 731
 732         dig = radeon_encoder->enc_priv;
 733
 734         if (!radeon_connector->con_priv)
 735                 return;
 736
 737         dig_connector = radeon_connector->con_priv;
 738
 739         memset(&args, 0, sizeof(args));
 740
 741         if (ASIC_IS_DCE32(rdev))
 742                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 743         else {
 744                 switch (radeon_encoder->encoder_id) {
 745                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 746                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 747                         break;
 748                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 749                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 750                         break;
 751                 }
 752         }
 753
 754         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 755
 756         args.v1.ucAction = action;
 757         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 758                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 759         } else {
 760                 if (radeon_encoder->pixel_clock > 165000)
 761                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 762                 else
 763                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 764         }
 765         if (ASIC_IS_DCE32(rdev)) {
 766                 if (radeon_encoder->pixel_clock > 165000)
 767                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 768                 if (dig->dig_block)
 769                         args.v2.acConfig.ucEncoderSel = 1;
 770
 771                 switch (radeon_encoder->encoder_id) {
 772                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 773                         args.v2.acConfig.ucTransmitterSel = 0;
 774                         num = 0;
 775                         break;
 776                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 777                         args.v2.acConfig.ucTransmitterSel = 1;
 778                         num = 1;
 779                         break;
 780                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 781                         args.v2.acConfig.ucTransmitterSel = 2;
 782                         num = 2;
 783                         break;
 784                 }
 785
 786                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 787                         if (dig->coherent_mode)
 788                                 args.v2.acConfig.fCoherentMode = 1;
 789                 }
 790         } else {
 791                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 792
 793                 switch (radeon_encoder->encoder_id) {
 794                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 795                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 796                         if (rdev->flags & RADEON_IS_IGP) {
 797                                 if (radeon_encoder->pixel_clock > 165000) {
 798                                         args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 799                                                              ATOM_TRANSMITTER_CONFIG_LINKA_B);
 800                                         if (dig_connector->igp_lane_info & 0x3)
 801                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 802                                         else if (dig_connector->igp_lane_info & 0xc)
 803                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 804                                 } else {
 805                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 806                                         if (dig_connector->igp_lane_info & 0x1)
 807                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 808                                         else if (dig_connector->igp_lane_info & 0x2)
 809                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 810                                         else if (dig_connector->igp_lane_info & 0x4)
 811                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 812                                         else if (dig_connector->igp_lane_info & 0x8)
 813                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 814                                 }
 815                         } else {
 816                                 if (radeon_encoder->pixel_clock > 165000)
 817                                         args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 818                                                              ATOM_TRANSMITTER_CONFIG_LINKA_B |
 819                                                              ATOM_TRANSMITTER_CONFIG_LANE_0_7);
 820                                 else {
 821                                         if (dig_connector->linkb)
 822                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 823                                         else
 824                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 825                                 }
 826                         }
 827                         break;
 828                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 829                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 830                         if (radeon_encoder->pixel_clock > 165000)
 831                                 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 832                                                      ATOM_TRANSMITTER_CONFIG_LINKA_B |
 833                                                      ATOM_TRANSMITTER_CONFIG_LANE_0_7);
 834                         else {
 835                                 if (dig_connector->linkb)
 836                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 837                                 else
 838                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 839                         }
 840                         break;
 841                 }
 842
 843                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 844                         if (dig->coherent_mode)
 845                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 846                 }
 847         }
 848
 849         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 850
 851 }
 852
 853 static void
 854 atombios_dig_transmitter_setup_vsemph(struct drm_encoder *encoder, u8 lane_num,
 855                                       u8 lane_set)
 856 {
 857         struct drm_device *dev = encoder->dev;
 858         struct radeon_device *rdev = dev->dev_private;
 859         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 860         union dig_transmitter_control args;
 861         int index = 0, num = 0;
 862         uint8_t frev, crev;
 863         struct radeon_encoder_atom_dig *dig;
 864         struct drm_connector *connector;
 865         struct radeon_connector *radeon_connector;
 866         struct radeon_connector_atom_dig *dig_connector;
 867
 868         connector = radeon_get_connector_for_encoder(encoder);
 869         if (!connector)
 870                 return;
 871
 872         radeon_connector = to_radeon_connector(connector);
 873
 874         if (!radeon_encoder->enc_priv)
 875                 return;
 876
 877         dig = radeon_encoder->enc_priv;
 878
 879         if (!radeon_connector->con_priv)
 880                 return;
 881
 882         dig_connector = radeon_connector->con_priv;
 883
 884         memset(&args, 0, sizeof(args));
 885
 886         if (ASIC_IS_DCE32(rdev))
 887                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 888         else {
 889                 switch (radeon_encoder->encoder_id) {
 890                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 891                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 892                         break;
 893                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 894                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 895                         break;
 896                 }
 897         }
 898
 899         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 900
 901         args.v1.ucAction = ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH;
 902         args.v1.asMode.ucLaneSel = lane_num;
 903         args.v1.asMode.ucLaneSet = lane_set;
 904
 905         if (ASIC_IS_DCE32(rdev)) {
 906                 args.v2.acConfig.fDPConnector = 1;
 907
 908                 if (dig->dig_block)
 909                         args.v2.acConfig.ucEncoderSel = 1;
 910
 911                 switch (radeon_encoder->encoder_id) {
 912                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 913                         args.v2.acConfig.ucTransmitterSel = 0;
 914                         num = 0;
 915                         break;
 916                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 917                         args.v2.acConfig.ucTransmitterSel = 1;
 918                         num = 1;
 919                         break;
 920                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 921                         args.v2.acConfig.ucTransmitterSel = 2;
 922                         num = 2;
 923                         break;
 924                 }
 925         } else {
 926                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 927
 928                 switch (radeon_encoder->encoder_id) {
 929                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 930                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 931                         if (dig_connector->linkb)
 932                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 933                         else
 934                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 935                 }
 936         }
 937
 938         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 939
 940         if (ASIC_IS_DCE32(rdev))
 941                 DRM_INFO("Output UNIPHY%d transmitter VSEMPH setup success\n", num);
 942         else
 943                 DRM_INFO("Output DIG%d transmitter VSEMPH setup success\n", num);
 944 }
 945
 946 static void
 947 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 948 {
 949         struct drm_device *dev = encoder->dev;
 950         struct radeon_device *rdev = dev->dev_private;
 951         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 952         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 953         ENABLE_YUV_PS_ALLOCATION args;
 954         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 955         uint32_t temp, reg;
 956
 957         memset(&args, 0, sizeof(args));
 958
 959         if (rdev->family >= CHIP_R600)
 960                 reg = R600_BIOS_3_SCRATCH;
 961         else
 962                 reg = RADEON_BIOS_3_SCRATCH;
 963
 964         /* XXX: fix up scratch reg handling */
 965         temp = RREG32(reg);
 966         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 967                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 968                              (radeon_crtc->crtc_id << 18)));
 969         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 970                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 971         else
 972                 WREG32(reg, 0);
 973
 974         if (enable)
 975                 args.ucEnable = ATOM_ENABLE;
 976         args.ucCRTC = radeon_crtc->crtc_id;
 977
 978         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 979
 980         WREG32(reg, temp);
 981 }
 982
 983 static void
 984 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 985 {
 986         struct drm_device *dev = encoder->dev;
 987         struct radeon_device *rdev = dev->dev_private;
 988         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 989         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 990         int index = 0;
 991         bool is_dig = false;
 992
 993         memset(&args, 0, sizeof(args));
 994
 995         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 996                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 997                   radeon_encoder->active_device);
 998         switch (radeon_encoder->encoder_id) {
 999         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1000         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1001                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1002                 break;
1003         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1004         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1005         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1006         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1007                 is_dig = true;
1008                 break;
1009         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1010         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1011         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1012                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1013                 break;
1014         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1015                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1016                 break;
1017         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1018                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1019                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1020                 else
1021                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1022                 break;
1023         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1024         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1025                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1026                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1027                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1028                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1029                 else
1030                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1031                 break;
1032         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1033         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1034                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1035                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1036                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1037                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1038                 else
1039                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1040                 break;
1041         }
1042
1043         if (is_dig) {
1044                 switch (mode) {
1045                 case DRM_MODE_DPMS_ON:
1046                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
1047                         break;
1048                 case DRM_MODE_DPMS_STANDBY:
1049                 case DRM_MODE_DPMS_SUSPEND:
1050                 case DRM_MODE_DPMS_OFF:
1051                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT);
1052                         break;
1053                 }
1054         } else {
1055                 switch (mode) {
1056                 case DRM_MODE_DPMS_ON:
1057                         args.ucAction = ATOM_ENABLE;
1058                         break;
1059                 case DRM_MODE_DPMS_STANDBY:
1060                 case DRM_MODE_DPMS_SUSPEND:
1061                 case DRM_MODE_DPMS_OFF:
1062                         args.ucAction = ATOM_DISABLE;
1063                         break;
1064                 }
1065                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1066         }
1067         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1068 }
1069
1070 union crtc_sourc_param {
1071         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1072         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1073 };
1074
1075 static void
1076 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1077 {
1078         struct drm_device *dev = encoder->dev;
1079         struct radeon_device *rdev = dev->dev_private;
1080         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1081         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1082         union crtc_sourc_param args;
1083         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1084         uint8_t frev, crev;
1085
1086         memset(&args, 0, sizeof(args));
1087
1088         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1089
1090         switch (frev) {
1091         case 1:
1092                 switch (crev) {
1093                 case 1:
1094                 default:
1095                         if (ASIC_IS_AVIVO(rdev))
1096                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1097                         else {
1098                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1099                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1100                                 } else {
1101                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1102                                 }
1103                         }
1104                         switch (radeon_encoder->encoder_id) {
1105                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1106                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1107                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1108                                 break;
1109                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1110                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1111                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1112                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1113                                 else
1114                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1115                                 break;
1116                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1117                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1118                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1119                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1120                                 break;
1121                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1122                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1123                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1124                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1125                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1126                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1127                                 else
1128                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1129                                 break;
1130                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1131                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1132                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1133                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1134                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1135                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1136                                 else
1137                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1138                                 break;
1139                         }
1140                         break;
1141                 case 2:
1142                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1143                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1144                         switch (radeon_encoder->encoder_id) {
1145                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1146                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1147                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1148                                 if (ASIC_IS_DCE32(rdev)) {
1149                                         if (radeon_crtc->crtc_id)
1150                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1151                                         else
1152                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1153                                 } else
1154                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1155                                 break;
1156                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1157                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1158                                 break;
1159                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1160                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1161                                 break;
1162                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1163                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1164                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1165                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1166                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1167                                 else
1168                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1169                                 break;
1170                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1171                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1172                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1173                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1174                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1175                                 else
1176                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1177                                 break;
1178                         }
1179                         break;
1180                 }
1181                 break;
1182         default:
1183                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1184                 break;
1185         }
1186
1187         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1188
1189 }
1190
1191 static void
1192 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1193                               struct drm_display_mode *mode)
1194 {
1195         struct drm_device *dev = encoder->dev;
1196         struct radeon_device *rdev = dev->dev_private;
1197         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1199
1200         /* Funky macbooks */
1201         if ((dev->pdev->device == 0x71C5) &&
1202             (dev->pdev->subsystem_vendor == 0x106b) &&
1203             (dev->pdev->subsystem_device == 0x0080)) {
1204                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1205                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1206
1207                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1208                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1209
1210                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1211                 }
1212         }
1213
1214         /* set scaler clears this on some chips */
1215         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1216                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1217                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1218                                AVIVO_D1MODE_INTERLEAVE_EN);
1219         }
1220 }
1221
1222 static void
1223 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1224                              struct drm_display_mode *mode,
1225                              struct drm_display_mode *adjusted_mode)
1226 {
1227         struct drm_device *dev = encoder->dev;
1228         struct radeon_device *rdev = dev->dev_private;
1229         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1230         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1231
1232         if (radeon_encoder->enc_priv) {
1233                 struct radeon_encoder_atom_dig *dig;
1234
1235                 dig = radeon_encoder->enc_priv;
1236                 dig->dig_block = radeon_crtc->crtc_id;
1237         }
1238         radeon_encoder->pixel_clock = adjusted_mode->clock;
1239
1240         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1241         atombios_set_encoder_crtc_source(encoder);
1242
1243         if (ASIC_IS_AVIVO(rdev)) {
1244                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1245                         atombios_yuv_setup(encoder, true);
1246                 else
1247                         atombios_yuv_setup(encoder, false);
1248         }
1249
1250         switch (radeon_encoder->encoder_id) {
1251         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1252         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1253         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1254         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1255                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1256                 break;
1257         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1258         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1259         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1260         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1261                 /* disable the encoder and transmitter */
1262                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
1263                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1264
1265                 /* setup and enable the encoder and transmitter */
1266                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1267                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT);
1268                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1269                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1270                 break;
1271         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1272                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1273                 break;
1274         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1275         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1276                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1277                 break;
1278         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1279         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1280         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1281         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1282                 atombios_dac_setup(encoder, ATOM_ENABLE);
1283                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1284                         atombios_tv_setup(encoder, ATOM_ENABLE);
1285                 break;
1286         }
1287         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1288 }
1289
1290 static bool
1291 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1292 {
1293         struct drm_device *dev = encoder->dev;
1294         struct radeon_device *rdev = dev->dev_private;
1295         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1296         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1297
1298         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1299                                        ATOM_DEVICE_CV_SUPPORT |
1300                                        ATOM_DEVICE_CRT_SUPPORT)) {
1301                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1302                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1303                 uint8_t frev, crev;
1304
1305                 memset(&args, 0, sizeof(args));
1306
1307                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1308
1309                 args.sDacload.ucMisc = 0;
1310
1311                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1312                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1313                         args.sDacload.ucDacType = ATOM_DAC_A;
1314                 else
1315                         args.sDacload.ucDacType = ATOM_DAC_B;
1316
1317                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1318                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1319                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1320                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1321                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1322                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1323                         if (crev >= 3)
1324                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1325                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1326                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1327                         if (crev >= 3)
1328                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1329                 }
1330
1331                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1332
1333                 return true;
1334         } else
1335                 return false;
1336 }
1337
1338 static enum drm_connector_status
1339 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1340 {
1341         struct drm_device *dev = encoder->dev;
1342         struct radeon_device *rdev = dev->dev_private;
1343         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1344         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1345         uint32_t bios_0_scratch;
1346
1347         if (!atombios_dac_load_detect(encoder, connector)) {
1348                 DRM_DEBUG("detect returned false \n");
1349                 return connector_status_unknown;
1350         }
1351
1352         if (rdev->family >= CHIP_R600)
1353                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1354         else
1355                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1356
1357         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1358         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1359                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1360                         return connector_status_connected;
1361         }
1362         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1363                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1364                         return connector_status_connected;
1365         }
1366         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1367                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1368                         return connector_status_connected;
1369         }
1370         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1371                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1372                         return connector_status_connected; /* CTV */
1373                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1374                         return connector_status_connected; /* STV */
1375         }
1376         return connector_status_disconnected;
1377 }
1378
1379 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1380 {
1381         radeon_atom_output_lock(encoder, true);
1382         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1383 }
1384
1385 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1386 {
1387         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1388         radeon_atom_output_lock(encoder, false);
1389 }
1390
1391 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1392 {
1393         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1394         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1395         radeon_encoder->active_device = 0;
1396 }
1397
1398 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1399         .dpms = radeon_atom_encoder_dpms,
1400         .mode_fixup = radeon_atom_mode_fixup,
1401         .prepare = radeon_atom_encoder_prepare,
1402         .mode_set = radeon_atom_encoder_mode_set,
1403         .commit = radeon_atom_encoder_commit,
1404         .disable = radeon_atom_encoder_disable,
1405         /* no detect for TMDS/LVDS yet */
1406 };
1407
1408 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1409         .dpms = radeon_atom_encoder_dpms,
1410         .mode_fixup = radeon_atom_mode_fixup,
1411         .prepare = radeon_atom_encoder_prepare,
1412         .mode_set = radeon_atom_encoder_mode_set,
1413         .commit = radeon_atom_encoder_commit,
1414         .detect = radeon_atom_dac_detect,
1415 };
1416
1417 void radeon_enc_destroy(struct drm_encoder *encoder)
1418 {
1419         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1420         kfree(radeon_encoder->enc_priv);
1421         drm_encoder_cleanup(encoder);
1422         kfree(radeon_encoder);
1423 }
1424
1425 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1426         .destroy = radeon_enc_destroy,
1427 };
1428
1429 struct radeon_encoder_atom_dac *
1430 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1431 {
1432         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1433
1434         if (!dac)
1435                 return NULL;
1436
1437         dac->tv_std = TV_STD_NTSC;
1438         return dac;
1439 }
1440
1441 struct radeon_encoder_atom_dig *
1442 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1443 {
1444         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1445
1446         if (!dig)
1447                 return NULL;
1448
1449         /* coherent mode by default */
1450         dig->coherent_mode = true;
1451
1452         return dig;
1453 }
1454
1455 void
1456 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1457 {
1458         struct radeon_device *rdev = dev->dev_private;
1459         struct drm_encoder *encoder;
1460         struct radeon_encoder *radeon_encoder;
1461
1462         /* see if we already added it */
1463         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1464                 radeon_encoder = to_radeon_encoder(encoder);
1465                 if (radeon_encoder->encoder_id == encoder_id) {
1466                         radeon_encoder->devices |= supported_device;
1467                         return;
1468                 }
1469
1470         }
1471
1472         /* add a new one */
1473         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1474         if (!radeon_encoder)
1475                 return;
1476
1477         encoder = &radeon_encoder->base;
1478         if (rdev->flags & RADEON_SINGLE_CRTC)
1479                 encoder->possible_crtcs = 0x1;
1480         else
1481                 encoder->possible_crtcs = 0x3;
1482
1483         radeon_encoder->enc_priv = NULL;
1484
1485         radeon_encoder->encoder_id = encoder_id;
1486         radeon_encoder->devices = supported_device;
1487         radeon_encoder->rmx_type = RMX_OFF;
1488
1489         switch (radeon_encoder->encoder_id) {
1490         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1491         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1492         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1493         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1494                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1495                         radeon_encoder->rmx_type = RMX_FULL;
1496                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1497                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1498                 } else {
1499                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1500                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1501                 }
1502                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1503                 break;
1504         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1505                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1506                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1507                 break;
1508         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1509         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1510         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1511                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1512                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1513                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1514                 break;
1515         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1516         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1517         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1518         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1519         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1520         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1521         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1522                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1523                         radeon_encoder->rmx_type = RMX_FULL;
1524                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1525                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1526                 } else {
1527                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1528                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1529                 }
1530                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1531                 break;
1532         }
1533 }