SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 void
 160 radeon_link_encoder_connector(struct drm_device *dev)
 161 {
 162         struct drm_connector *connector;
 163         struct radeon_connector *radeon_connector;
 164         struct drm_encoder *encoder;
 165         struct radeon_encoder *radeon_encoder;
 166
 167         /* walk the list and link encoders to connectors */
 168         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 169                 radeon_connector = to_radeon_connector(connector);
 170                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 171                         radeon_encoder = to_radeon_encoder(encoder);
 172                         if (radeon_encoder->devices & radeon_connector->devices)
 173                                 drm_mode_connector_attach_encoder(connector, encoder);
 174                 }
 175         }
 176 }
 177
 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 179 {
 180         struct drm_device *dev = encoder->dev;
 181         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 182         struct drm_connector *connector;
 183
 184         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 185                 if (connector->encoder == encoder) {
 186                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 187                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 188                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 189                                   radeon_encoder->active_device, radeon_encoder->devices,
 190                                   radeon_connector->devices, encoder->encoder_type);
 191                 }
 192         }
 193 }
 194
 195 static struct drm_connector *
 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 197 {
 198         struct drm_device *dev = encoder->dev;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct drm_connector *connector;
 201         struct radeon_connector *radeon_connector;
 202
 203         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 204                 radeon_connector = to_radeon_connector(connector);
 205                 if (radeon_encoder->devices & radeon_connector->devices)
 206                         return connector;
 207         }
 208         return NULL;
 209 }
 210
 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 212                                    struct drm_display_mode *mode,
 213                                    struct drm_display_mode *adjusted_mode)
 214 {
 215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 216         struct drm_device *dev = encoder->dev;
 217         struct radeon_device *rdev = dev->dev_private;
 218
 219         /* set the active encoder to connector routing */
 220         radeon_encoder_set_active_device(encoder);
 221         drm_mode_set_crtcinfo(adjusted_mode, 0);
 222
 223         /* hw bug */
 224         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 225             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 226                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 227
 228         /* get the native mode for LVDS */
 229         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 230                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 231                 int mode_id = adjusted_mode->base.id;
 232                 *adjusted_mode = *native_mode;
 233                 if (!ASIC_IS_AVIVO(rdev)) {
 234                         adjusted_mode->hdisplay = mode->hdisplay;
 235                         adjusted_mode->vdisplay = mode->vdisplay;
 236                 }
 237                 adjusted_mode->base.id = mode_id;
 238         }
 239
 240         /* get the native mode for TV */
 241         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 242                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 243                 if (tv_dac) {
 244                         if (tv_dac->tv_std == TV_STD_NTSC ||
 245                             tv_dac->tv_std == TV_STD_NTSC_J ||
 246                             tv_dac->tv_std == TV_STD_PAL_M)
 247                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 248                         else
 249                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 250                 }
 251         }
 252
 253         if (ASIC_IS_DCE3(rdev) &&
 254             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 255                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 256                 radeon_dp_set_link_config(connector, mode);
 257         }
 258
 259         return true;
 260 }
 261
 262 static void
 263 atombios_dac_setup(struct drm_encoder *encoder, int action)
 264 {
 265         struct drm_device *dev = encoder->dev;
 266         struct radeon_device *rdev = dev->dev_private;
 267         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 268         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 269         int index = 0, num = 0;
 270         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 271         enum radeon_tv_std tv_std = TV_STD_NTSC;
 272
 273         if (dac_info->tv_std)
 274                 tv_std = dac_info->tv_std;
 275
 276         memset(&args, 0, sizeof(args));
 277
 278         switch (radeon_encoder->encoder_id) {
 279         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 280         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 281                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 282                 num = 1;
 283                 break;
 284         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 285         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 286                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 287                 num = 2;
 288                 break;
 289         }
 290
 291         args.ucAction = action;
 292
 293         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 294                 args.ucDacStandard = ATOM_DAC1_PS2;
 295         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 296                 args.ucDacStandard = ATOM_DAC1_CV;
 297         else {
 298                 switch (tv_std) {
 299                 case TV_STD_PAL:
 300                 case TV_STD_PAL_M:
 301                 case TV_STD_SCART_PAL:
 302                 case TV_STD_SECAM:
 303                 case TV_STD_PAL_CN:
 304                         args.ucDacStandard = ATOM_DAC1_PAL;
 305                         break;
 306                 case TV_STD_NTSC:
 307                 case TV_STD_NTSC_J:
 308                 case TV_STD_PAL_60:
 309                 default:
 310                         args.ucDacStandard = ATOM_DAC1_NTSC;
 311                         break;
 312                 }
 313         }
 314         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 315
 316         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 317
 318 }
 319
 320 static void
 321 atombios_tv_setup(struct drm_encoder *encoder, int action)
 322 {
 323         struct drm_device *dev = encoder->dev;
 324         struct radeon_device *rdev = dev->dev_private;
 325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 326         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 327         int index = 0;
 328         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 329         enum radeon_tv_std tv_std = TV_STD_NTSC;
 330
 331         if (dac_info->tv_std)
 332                 tv_std = dac_info->tv_std;
 333
 334         memset(&args, 0, sizeof(args));
 335
 336         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 337
 338         args.sTVEncoder.ucAction = action;
 339
 340         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 341                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 342         else {
 343                 switch (tv_std) {
 344                 case TV_STD_NTSC:
 345                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 346                         break;
 347                 case TV_STD_PAL:
 348                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 349                         break;
 350                 case TV_STD_PAL_M:
 351                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 352                         break;
 353                 case TV_STD_PAL_60:
 354                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 355                         break;
 356                 case TV_STD_NTSC_J:
 357                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 358                         break;
 359                 case TV_STD_SCART_PAL:
 360                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 361                         break;
 362                 case TV_STD_SECAM:
 363                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 364                         break;
 365                 case TV_STD_PAL_CN:
 366                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 367                         break;
 368                 default:
 369                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 370                         break;
 371                 }
 372         }
 373
 374         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 375
 376         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 377
 378 }
 379
 380 void
 381 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 382 {
 383         struct drm_device *dev = encoder->dev;
 384         struct radeon_device *rdev = dev->dev_private;
 385         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 386         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 387         int index = 0;
 388
 389         memset(&args, 0, sizeof(args));
 390
 391         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 392
 393         args.sXTmdsEncoder.ucEnable = action;
 394
 395         if (radeon_encoder->pixel_clock > 165000)
 396                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 397
 398         /*if (pScrn->rgbBits == 8)*/
 399         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 400
 401         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 402
 403 }
 404
 405 static void
 406 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 407 {
 408         struct drm_device *dev = encoder->dev;
 409         struct radeon_device *rdev = dev->dev_private;
 410         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 411         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 412         int index = 0;
 413
 414         memset(&args, 0, sizeof(args));
 415
 416         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 417
 418         args.sDVOEncoder.ucAction = action;
 419         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 420
 421         if (radeon_encoder->pixel_clock > 165000)
 422                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 423
 424         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 425
 426 }
 427
 428 union lvds_encoder_control {
 429         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 430         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 431 };
 432
 433 void
 434 atombios_digital_setup(struct drm_encoder *encoder, int action)
 435 {
 436         struct drm_device *dev = encoder->dev;
 437         struct radeon_device *rdev = dev->dev_private;
 438         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 439         union lvds_encoder_control args;
 440         int index = 0;
 441         uint8_t frev, crev;
 442         struct radeon_encoder_atom_dig *dig;
 443         struct drm_connector *connector;
 444         struct radeon_connector *radeon_connector;
 445         struct radeon_connector_atom_dig *dig_connector;
 446
 447         connector = radeon_get_connector_for_encoder(encoder);
 448         if (!connector)
 449                 return;
 450
 451         radeon_connector = to_radeon_connector(connector);
 452
 453         if (!radeon_encoder->enc_priv)
 454                 return;
 455
 456         dig = radeon_encoder->enc_priv;
 457
 458         if (!radeon_connector->con_priv)
 459                 return;
 460
 461         dig_connector = radeon_connector->con_priv;
 462
 463         memset(&args, 0, sizeof(args));
 464
 465         switch (radeon_encoder->encoder_id) {
 466         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 467                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 468                 break;
 469         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 470         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 471                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 472                 break;
 473         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 474                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 475                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 476                 else
 477                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 478                 break;
 479         }
 480
 481         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 482
 483         switch (frev) {
 484         case 1:
 485         case 2:
 486                 switch (crev) {
 487                 case 1:
 488                         args.v1.ucMisc = 0;
 489                         args.v1.ucAction = action;
 490                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 491                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 492                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 493                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 494                                 if (dig->lvds_misc & (1 << 0))
 495                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 496                                 if (dig->lvds_misc & (1 << 1))
 497                                         args.v1.ucMisc |= (1 << 1);
 498                         } else {
 499                                 if (dig_connector->linkb)
 500                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 501                                 if (radeon_encoder->pixel_clock > 165000)
 502                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 503                                 /*if (pScrn->rgbBits == 8) */
 504                                 args.v1.ucMisc |= (1 << 1);
 505                         }
 506                         break;
 507                 case 2:
 508                 case 3:
 509                         args.v2.ucMisc = 0;
 510                         args.v2.ucAction = action;
 511                         if (crev == 3) {
 512                                 if (dig->coherent_mode)
 513                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 514                         }
 515                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 516                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 517                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 518                         args.v2.ucTruncate = 0;
 519                         args.v2.ucSpatial = 0;
 520                         args.v2.ucTemporal = 0;
 521                         args.v2.ucFRC = 0;
 522                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 523                                 if (dig->lvds_misc & (1 << 0))
 524                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 525                                 if (dig->lvds_misc & (1 << 5)) {
 526                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 527                                         if (dig->lvds_misc & (1 << 1))
 528                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 529                                 }
 530                                 if (dig->lvds_misc & (1 << 6)) {
 531                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 532                                         if (dig->lvds_misc & (1 << 1))
 533                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 534                                         if (((dig->lvds_misc >> 2) & 0x3) == 2)
 535                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 536                                 }
 537                         } else {
 538                                 if (dig_connector->linkb)
 539                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 540                                 if (radeon_encoder->pixel_clock > 165000)
 541                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 542                         }
 543                         break;
 544                 default:
 545                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 546                         break;
 547                 }
 548                 break;
 549         default:
 550                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 551                 break;
 552         }
 553
 554         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 555
 556 }
 557
 558 int
 559 atombios_get_encoder_mode(struct drm_encoder *encoder)
 560 {
 561         struct drm_connector *connector;
 562         struct radeon_connector *radeon_connector;
 563         struct radeon_connector_atom_dig *radeon_dig_connector;
 564
 565         connector = radeon_get_connector_for_encoder(encoder);
 566         if (!connector)
 567                 return 0;
 568
 569         radeon_connector = to_radeon_connector(connector);
 570
 571         switch (connector->connector_type) {
 572         case DRM_MODE_CONNECTOR_DVII:
 573         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 574                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 575                         return ATOM_ENCODER_MODE_HDMI;
 576                 else if (radeon_connector->use_digital)
 577                         return ATOM_ENCODER_MODE_DVI;
 578                 else
 579                         return ATOM_ENCODER_MODE_CRT;
 580                 break;
 581         case DRM_MODE_CONNECTOR_DVID:
 582         case DRM_MODE_CONNECTOR_HDMIA:
 583         default:
 584                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 585                         return ATOM_ENCODER_MODE_HDMI;
 586                 else
 587                         return ATOM_ENCODER_MODE_DVI;
 588                 break;
 589         case DRM_MODE_CONNECTOR_LVDS:
 590                 return ATOM_ENCODER_MODE_LVDS;
 591                 break;
 592         case DRM_MODE_CONNECTOR_DisplayPort:
 593                 radeon_dig_connector = radeon_connector->con_priv;
 594                 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
 595                         return ATOM_ENCODER_MODE_DP;
 596                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 597                         return ATOM_ENCODER_MODE_HDMI;
 598                 else
 599                         return ATOM_ENCODER_MODE_DVI;
 600                 break;
 601         case CONNECTOR_DVI_A:
 602         case CONNECTOR_VGA:
 603                 return ATOM_ENCODER_MODE_CRT;
 604                 break;
 605         case CONNECTOR_STV:
 606         case CONNECTOR_CTV:
 607         case CONNECTOR_DIN:
 608                 /* fix me */
 609                 return ATOM_ENCODER_MODE_TV;
 610                 /*return ATOM_ENCODER_MODE_CV;*/
 611                 break;
 612         }
 613 }
 614
 615 /*
 616  * DIG Encoder/Transmitter Setup
 617  *
 618  * DCE 3.0/3.1
 619  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 620  * Supports up to 3 digital outputs
 621  * - 2 DIG encoder blocks.
 622  * DIG1 can drive UNIPHY link A or link B
 623  * DIG2 can drive UNIPHY link B or LVTMA
 624  *
 625  * DCE 3.2
 626  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 627  * Supports up to 5 digital outputs
 628  * - 2 DIG encoder blocks.
 629  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 630  *
 631  * Routing
 632  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 633  * Examples:
 634  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 635  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 636  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 637  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 638  */
 639 static void
 640 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 641 {
 642         struct drm_device *dev = encoder->dev;
 643         struct radeon_device *rdev = dev->dev_private;
 644         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 645         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 646         int index = 0, num = 0;
 647         uint8_t frev, crev;
 648         struct radeon_encoder_atom_dig *dig;
 649         struct drm_connector *connector;
 650         struct radeon_connector *radeon_connector;
 651         struct radeon_connector_atom_dig *dig_connector;
 652
 653         connector = radeon_get_connector_for_encoder(encoder);
 654         if (!connector)
 655                 return;
 656
 657         radeon_connector = to_radeon_connector(connector);
 658
 659         if (!radeon_connector->con_priv)
 660                 return;
 661
 662         dig_connector = radeon_connector->con_priv;
 663
 664         if (!radeon_encoder->enc_priv)
 665                 return;
 666
 667         dig = radeon_encoder->enc_priv;
 668
 669         memset(&args, 0, sizeof(args));
 670
 671         if (ASIC_IS_DCE32(rdev)) {
 672                 if (dig->dig_block)
 673                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 674                 else
 675                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 676                 num = dig->dig_block + 1;
 677         } else {
 678                 switch (radeon_encoder->encoder_id) {
 679                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 680                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 681                          * not already in use
 682                          */
 683                         if (dig_connector->linkb)
 684                                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 685                         else
 686                                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 687                         num = 1;
 688                         break;
 689                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 690                         /* Only dig2 encoder can drive LVTMA */
 691                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 692                         num = 2;
 693                         break;
 694                 }
 695         }
 696
 697         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 698
 699         args.ucAction = action;
 700         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 701
 702         if (ASIC_IS_DCE32(rdev)) {
 703                 switch (radeon_encoder->encoder_id) {
 704                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 705                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 706                         break;
 707                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 708                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 709                         break;
 710                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 711                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 712                         break;
 713                 }
 714         } else {
 715                 switch (radeon_encoder->encoder_id) {
 716                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 717                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 718                         break;
 719                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 720                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 721                         break;
 722                 }
 723         }
 724
 725         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 726
 727         if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 728                 if (dig_connector->dp_clock == 270000)
 729                         args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 730                 args.ucLaneNum = dig_connector->dp_lane_count;
 731         } else if (radeon_encoder->pixel_clock > 165000)
 732                 args.ucLaneNum = 8;
 733         else
 734                 args.ucLaneNum = 4;
 735
 736         if (dig_connector->linkb)
 737                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 738         else
 739                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 740
 741         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 742
 743 }
 744
 745 union dig_transmitter_control {
 746         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 747         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 748 };
 749
 750 void
 751 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 752 {
 753         struct drm_device *dev = encoder->dev;
 754         struct radeon_device *rdev = dev->dev_private;
 755         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 756         union dig_transmitter_control args;
 757         int index = 0, num = 0;
 758         uint8_t frev, crev;
 759         struct radeon_encoder_atom_dig *dig;
 760         struct drm_connector *connector;
 761         struct radeon_connector *radeon_connector;
 762         struct radeon_connector_atom_dig *dig_connector;
 763         bool is_dp = false;
 764
 765         connector = radeon_get_connector_for_encoder(encoder);
 766         if (!connector)
 767                 return;
 768
 769         radeon_connector = to_radeon_connector(connector);
 770
 771         if (!radeon_encoder->enc_priv)
 772                 return;
 773
 774         dig = radeon_encoder->enc_priv;
 775
 776         if (!radeon_connector->con_priv)
 777                 return;
 778
 779         dig_connector = radeon_connector->con_priv;
 780
 781         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 782                 is_dp = true;
 783
 784         memset(&args, 0, sizeof(args));
 785
 786         if (ASIC_IS_DCE32(rdev))
 787                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 788         else {
 789                 switch (radeon_encoder->encoder_id) {
 790                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 791                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 792                         break;
 793                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 794                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 795                         break;
 796                 }
 797         }
 798
 799         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 800
 801         args.v1.ucAction = action;
 802         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 803                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 804         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 805                 args.v1.asMode.ucLaneSel = lane_num;
 806                 args.v1.asMode.ucLaneSet = lane_set;
 807         } else {
 808                 if (is_dp)
 809                         args.v1.usPixelClock =
 810                                 cpu_to_le16(dig_connector->dp_clock / 10);
 811                 else if (radeon_encoder->pixel_clock > 165000)
 812                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 813                 else
 814                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 815         }
 816         if (ASIC_IS_DCE32(rdev)) {
 817                 if (dig->dig_block)
 818                         args.v2.acConfig.ucEncoderSel = 1;
 819                 if (dig_connector->linkb)
 820                         args.v2.acConfig.ucLinkSel = 1;
 821
 822                 switch (radeon_encoder->encoder_id) {
 823                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 824                         args.v2.acConfig.ucTransmitterSel = 0;
 825                         num = 0;
 826                         break;
 827                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 828                         args.v2.acConfig.ucTransmitterSel = 1;
 829                         num = 1;
 830                         break;
 831                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 832                         args.v2.acConfig.ucTransmitterSel = 2;
 833                         num = 2;
 834                         break;
 835                 }
 836
 837                 if (is_dp)
 838                         args.v2.acConfig.fCoherentMode = 1;
 839                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 840                         if (dig->coherent_mode)
 841                                 args.v2.acConfig.fCoherentMode = 1;
 842                 }
 843         } else {
 844                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 845
 846                 switch (radeon_encoder->encoder_id) {
 847                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 848                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 849                          * not already in use
 850                          */
 851                         if (dig_connector->linkb)
 852                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 853                         else
 854                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 855                         if (rdev->flags & RADEON_IS_IGP) {
 856                                 if (radeon_encoder->pixel_clock > 165000) {
 857                                         if (dig_connector->igp_lane_info & 0x3)
 858                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 859                                         else if (dig_connector->igp_lane_info & 0xc)
 860                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 861                                 } else {
 862                                         if (dig_connector->igp_lane_info & 0x1)
 863                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 864                                         else if (dig_connector->igp_lane_info & 0x2)
 865                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 866                                         else if (dig_connector->igp_lane_info & 0x4)
 867                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 868                                         else if (dig_connector->igp_lane_info & 0x8)
 869                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 870                                 }
 871                         }
 872                         break;
 873                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 874                         /* Only dig2 encoder can drive LVTMA */
 875                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 876                         break;
 877                 }
 878
 879                 if (radeon_encoder->pixel_clock > 165000)
 880                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 881
 882                 if (dig_connector->linkb)
 883                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 884                 else
 885                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 886
 887                 if (is_dp)
 888                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 889                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 890                         if (dig->coherent_mode)
 891                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 892                 }
 893         }
 894
 895         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 896
 897 }
 898
 899 static void
 900 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 901 {
 902         struct drm_device *dev = encoder->dev;
 903         struct radeon_device *rdev = dev->dev_private;
 904         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 905         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 906         ENABLE_YUV_PS_ALLOCATION args;
 907         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 908         uint32_t temp, reg;
 909
 910         memset(&args, 0, sizeof(args));
 911
 912         if (rdev->family >= CHIP_R600)
 913                 reg = R600_BIOS_3_SCRATCH;
 914         else
 915                 reg = RADEON_BIOS_3_SCRATCH;
 916
 917         /* XXX: fix up scratch reg handling */
 918         temp = RREG32(reg);
 919         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 920                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 921                              (radeon_crtc->crtc_id << 18)));
 922         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 923                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 924         else
 925                 WREG32(reg, 0);
 926
 927         if (enable)
 928                 args.ucEnable = ATOM_ENABLE;
 929         args.ucCRTC = radeon_crtc->crtc_id;
 930
 931         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 932
 933         WREG32(reg, temp);
 934 }
 935
 936 static void
 937 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 938 {
 939         struct drm_device *dev = encoder->dev;
 940         struct radeon_device *rdev = dev->dev_private;
 941         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 942         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 943         int index = 0;
 944         bool is_dig = false;
 945
 946         memset(&args, 0, sizeof(args));
 947
 948         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 949                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 950                   radeon_encoder->active_device);
 951         switch (radeon_encoder->encoder_id) {
 952         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 953         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 954                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 955                 break;
 956         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 957         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 958         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 959         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 960                 is_dig = true;
 961                 break;
 962         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 963         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 964         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 965                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 966                 break;
 967         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 968                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 969                 break;
 970         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 971                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 972                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 973                 else
 974                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 975                 break;
 976         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 977         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 978                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 979                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 980                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 981                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 982                 else
 983                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 984                 break;
 985         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 986         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 987                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 988                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 989                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 990                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 991                 else
 992                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 993                 break;
 994         }
 995
 996         if (is_dig) {
 997                 switch (mode) {
 998                 case DRM_MODE_DPMS_ON:
 999                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1000                         {
1001                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1002                                 dp_link_train(encoder, connector);
1003                         }
1004                         break;
1005                 case DRM_MODE_DPMS_STANDBY:
1006                 case DRM_MODE_DPMS_SUSPEND:
1007                 case DRM_MODE_DPMS_OFF:
1008                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1009                         break;
1010                 }
1011         } else {
1012                 switch (mode) {
1013                 case DRM_MODE_DPMS_ON:
1014                         args.ucAction = ATOM_ENABLE;
1015                         break;
1016                 case DRM_MODE_DPMS_STANDBY:
1017                 case DRM_MODE_DPMS_SUSPEND:
1018                 case DRM_MODE_DPMS_OFF:
1019                         args.ucAction = ATOM_DISABLE;
1020                         break;
1021                 }
1022                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1023         }
1024         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1025 }
1026
1027 union crtc_sourc_param {
1028         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1029         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1030 };
1031
1032 static void
1033 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1034 {
1035         struct drm_device *dev = encoder->dev;
1036         struct radeon_device *rdev = dev->dev_private;
1037         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1038         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1039         union crtc_sourc_param args;
1040         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1041         uint8_t frev, crev;
1042
1043         memset(&args, 0, sizeof(args));
1044
1045         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1046
1047         switch (frev) {
1048         case 1:
1049                 switch (crev) {
1050                 case 1:
1051                 default:
1052                         if (ASIC_IS_AVIVO(rdev))
1053                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1054                         else {
1055                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1056                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1057                                 } else {
1058                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1059                                 }
1060                         }
1061                         switch (radeon_encoder->encoder_id) {
1062                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1063                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1064                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1065                                 break;
1066                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1067                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1068                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1069                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1070                                 else
1071                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1072                                 break;
1073                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1074                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1075                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1076                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1077                                 break;
1078                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1079                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1080                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1081                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1082                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1083                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1084                                 else
1085                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1086                                 break;
1087                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1088                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1089                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1090                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1091                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1092                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1093                                 else
1094                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1095                                 break;
1096                         }
1097                         break;
1098                 case 2:
1099                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1100                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1101                         switch (radeon_encoder->encoder_id) {
1102                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1103                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1104                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1105                                 if (ASIC_IS_DCE32(rdev)) {
1106                                         if (radeon_crtc->crtc_id)
1107                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1108                                         else
1109                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1110                                 } else {
1111                                         struct drm_connector *connector;
1112                                         struct radeon_connector *radeon_connector;
1113                                         struct radeon_connector_atom_dig *dig_connector;
1114
1115                                         connector = radeon_get_connector_for_encoder(encoder);
1116                                         if (!connector)
1117                                                 return;
1118                                         radeon_connector = to_radeon_connector(connector);
1119                                         if (!radeon_connector->con_priv)
1120                                                 return;
1121                                         dig_connector = radeon_connector->con_priv;
1122
1123                                         /* XXX doesn't really matter which dig encoder we pick as long as it's
1124                                          * not already in use
1125                                          */
1126                                         if (dig_connector->linkb)
1127                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1128                                         else
1129                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1130                                 }
1131                                 break;
1132                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1133                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1134                                 break;
1135                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1136                                 /* Only dig2 encoder can drive LVTMA */
1137                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1138                                 break;
1139                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1140                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1141                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1142                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1143                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1144                                 else
1145                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1146                                 break;
1147                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1148                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1149                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1150                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1151                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1152                                 else
1153                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1154                                 break;
1155                         }
1156                         break;
1157                 }
1158                 break;
1159         default:
1160                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1161                 break;
1162         }
1163
1164         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1165
1166 }
1167
1168 static void
1169 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1170                               struct drm_display_mode *mode)
1171 {
1172         struct drm_device *dev = encoder->dev;
1173         struct radeon_device *rdev = dev->dev_private;
1174         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1175         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1176
1177         /* Funky macbooks */
1178         if ((dev->pdev->device == 0x71C5) &&
1179             (dev->pdev->subsystem_vendor == 0x106b) &&
1180             (dev->pdev->subsystem_device == 0x0080)) {
1181                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1182                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1183
1184                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1185                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1186
1187                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1188                 }
1189         }
1190
1191         /* set scaler clears this on some chips */
1192         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1193                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1194                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1195                                AVIVO_D1MODE_INTERLEAVE_EN);
1196         }
1197 }
1198
1199 static void
1200 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1201                              struct drm_display_mode *mode,
1202                              struct drm_display_mode *adjusted_mode)
1203 {
1204         struct drm_device *dev = encoder->dev;
1205         struct radeon_device *rdev = dev->dev_private;
1206         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1207         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1208
1209         if (radeon_encoder->active_device &
1210             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1211                 if (radeon_encoder->enc_priv) {
1212                         struct radeon_encoder_atom_dig *dig;
1213
1214                         dig = radeon_encoder->enc_priv;
1215                         dig->dig_block = radeon_crtc->crtc_id;
1216                 }
1217         }
1218         radeon_encoder->pixel_clock = adjusted_mode->clock;
1219
1220         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1221         atombios_set_encoder_crtc_source(encoder);
1222
1223         if (ASIC_IS_AVIVO(rdev)) {
1224                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1225                         atombios_yuv_setup(encoder, true);
1226                 else
1227                         atombios_yuv_setup(encoder, false);
1228         }
1229
1230         switch (radeon_encoder->encoder_id) {
1231         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1232         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1233         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1234         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1235                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1236                 break;
1237         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1238         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1239         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1240         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1241                 /* disable the encoder and transmitter */
1242                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1243                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1244
1245                 /* setup and enable the encoder and transmitter */
1246                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1247                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1248                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1249                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1250                 break;
1251         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1252                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1253                 break;
1254         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1255         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1256                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1257                 break;
1258         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1259         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1260         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1261         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1262                 atombios_dac_setup(encoder, ATOM_ENABLE);
1263                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1264                         atombios_tv_setup(encoder, ATOM_ENABLE);
1265                 break;
1266         }
1267         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1268 }
1269
1270 static bool
1271 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1272 {
1273         struct drm_device *dev = encoder->dev;
1274         struct radeon_device *rdev = dev->dev_private;
1275         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1276         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1277
1278         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1279                                        ATOM_DEVICE_CV_SUPPORT |
1280                                        ATOM_DEVICE_CRT_SUPPORT)) {
1281                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1282                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1283                 uint8_t frev, crev;
1284
1285                 memset(&args, 0, sizeof(args));
1286
1287                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1288
1289                 args.sDacload.ucMisc = 0;
1290
1291                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1292                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1293                         args.sDacload.ucDacType = ATOM_DAC_A;
1294                 else
1295                         args.sDacload.ucDacType = ATOM_DAC_B;
1296
1297                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1298                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1299                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1300                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1301                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1302                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1303                         if (crev >= 3)
1304                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1305                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1306                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1307                         if (crev >= 3)
1308                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1309                 }
1310
1311                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1312
1313                 return true;
1314         } else
1315                 return false;
1316 }
1317
1318 static enum drm_connector_status
1319 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1320 {
1321         struct drm_device *dev = encoder->dev;
1322         struct radeon_device *rdev = dev->dev_private;
1323         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1324         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1325         uint32_t bios_0_scratch;
1326
1327         if (!atombios_dac_load_detect(encoder, connector)) {
1328                 DRM_DEBUG("detect returned false \n");
1329                 return connector_status_unknown;
1330         }
1331
1332         if (rdev->family >= CHIP_R600)
1333                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1334         else
1335                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1336
1337         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1338         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1339                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1340                         return connector_status_connected;
1341         }
1342         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1343                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1344                         return connector_status_connected;
1345         }
1346         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1347                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1348                         return connector_status_connected;
1349         }
1350         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1351                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1352                         return connector_status_connected; /* CTV */
1353                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1354                         return connector_status_connected; /* STV */
1355         }
1356         return connector_status_disconnected;
1357 }
1358
1359 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1360 {
1361         radeon_atom_output_lock(encoder, true);
1362         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1363 }
1364
1365 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1366 {
1367         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1368         radeon_atom_output_lock(encoder, false);
1369 }
1370
1371 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1372 {
1373         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1374         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1375         radeon_encoder->active_device = 0;
1376 }
1377
1378 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1379         .dpms = radeon_atom_encoder_dpms,
1380         .mode_fixup = radeon_atom_mode_fixup,
1381         .prepare = radeon_atom_encoder_prepare,
1382         .mode_set = radeon_atom_encoder_mode_set,
1383         .commit = radeon_atom_encoder_commit,
1384         .disable = radeon_atom_encoder_disable,
1385         /* no detect for TMDS/LVDS yet */
1386 };
1387
1388 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1389         .dpms = radeon_atom_encoder_dpms,
1390         .mode_fixup = radeon_atom_mode_fixup,
1391         .prepare = radeon_atom_encoder_prepare,
1392         .mode_set = radeon_atom_encoder_mode_set,
1393         .commit = radeon_atom_encoder_commit,
1394         .detect = radeon_atom_dac_detect,
1395 };
1396
1397 void radeon_enc_destroy(struct drm_encoder *encoder)
1398 {
1399         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1400         kfree(radeon_encoder->enc_priv);
1401         drm_encoder_cleanup(encoder);
1402         kfree(radeon_encoder);
1403 }
1404
1405 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1406         .destroy = radeon_enc_destroy,
1407 };
1408
1409 struct radeon_encoder_atom_dac *
1410 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1411 {
1412         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1413
1414         if (!dac)
1415                 return NULL;
1416
1417         dac->tv_std = TV_STD_NTSC;
1418         return dac;
1419 }
1420
1421 struct radeon_encoder_atom_dig *
1422 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1423 {
1424         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1425
1426         if (!dig)
1427                 return NULL;
1428
1429         /* coherent mode by default */
1430         dig->coherent_mode = true;
1431
1432         return dig;
1433 }
1434
1435 void
1436 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1437 {
1438         struct radeon_device *rdev = dev->dev_private;
1439         struct drm_encoder *encoder;
1440         struct radeon_encoder *radeon_encoder;
1441
1442         /* see if we already added it */
1443         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1444                 radeon_encoder = to_radeon_encoder(encoder);
1445                 if (radeon_encoder->encoder_id == encoder_id) {
1446                         radeon_encoder->devices |= supported_device;
1447                         return;
1448                 }
1449
1450         }
1451
1452         /* add a new one */
1453         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1454         if (!radeon_encoder)
1455                 return;
1456
1457         encoder = &radeon_encoder->base;
1458         if (rdev->flags & RADEON_SINGLE_CRTC)
1459                 encoder->possible_crtcs = 0x1;
1460         else
1461                 encoder->possible_crtcs = 0x3;
1462
1463         radeon_encoder->enc_priv = NULL;
1464
1465         radeon_encoder->encoder_id = encoder_id;
1466         radeon_encoder->devices = supported_device;
1467         radeon_encoder->rmx_type = RMX_OFF;
1468
1469         switch (radeon_encoder->encoder_id) {
1470         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1471         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1472         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1473         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1474                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1475                         radeon_encoder->rmx_type = RMX_FULL;
1476                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1477                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1478                 } else {
1479                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1480                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1481                 }
1482                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1483                 break;
1484         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1485                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1486                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1487                 break;
1488         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1489         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1490         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1491                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1492                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1493                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1494                 break;
1495         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1496         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1497         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1498         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1499         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1500         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1501         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1502                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1503                         radeon_encoder->rmx_type = RMX_FULL;
1504                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1505                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1506                 } else {
1507                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1508                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1509                 }
1510                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1511                 break;
1512         }
1513 }