SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 void
 160 radeon_link_encoder_connector(struct drm_device *dev)
 161 {
 162         struct drm_connector *connector;
 163         struct radeon_connector *radeon_connector;
 164         struct drm_encoder *encoder;
 165         struct radeon_encoder *radeon_encoder;
 166
 167         /* walk the list and link encoders to connectors */
 168         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 169                 radeon_connector = to_radeon_connector(connector);
 170                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 171                         radeon_encoder = to_radeon_encoder(encoder);
 172                         if (radeon_encoder->devices & radeon_connector->devices)
 173                                 drm_mode_connector_attach_encoder(connector, encoder);
 174                 }
 175         }
 176 }
 177
 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 179 {
 180         struct drm_device *dev = encoder->dev;
 181         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 182         struct drm_connector *connector;
 183
 184         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 185                 if (connector->encoder == encoder) {
 186                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 187                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 188                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 189                                   radeon_encoder->active_device, radeon_encoder->devices,
 190                                   radeon_connector->devices, encoder->encoder_type);
 191                 }
 192         }
 193 }
 194
 195 static struct drm_connector *
 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 197 {
 198         struct drm_device *dev = encoder->dev;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct drm_connector *connector;
 201         struct radeon_connector *radeon_connector;
 202
 203         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 204                 radeon_connector = to_radeon_connector(connector);
 205                 if (radeon_encoder->devices & radeon_connector->devices)
 206                         return connector;
 207         }
 208         return NULL;
 209 }
 210
 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 212                                    struct drm_display_mode *mode,
 213                                    struct drm_display_mode *adjusted_mode)
 214 {
 215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 216         struct drm_device *dev = encoder->dev;
 217         struct radeon_device *rdev = dev->dev_private;
 218
 219         /* set the active encoder to connector routing */
 220         radeon_encoder_set_active_device(encoder);
 221         drm_mode_set_crtcinfo(adjusted_mode, 0);
 222
 223         /* hw bug */
 224         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 225             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 226                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 227
 228         /* get the native mode for LVDS */
 229         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 230                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 231                 int mode_id = adjusted_mode->base.id;
 232                 *adjusted_mode = *native_mode;
 233                 if (!ASIC_IS_AVIVO(rdev)) {
 234                         adjusted_mode->hdisplay = mode->hdisplay;
 235                         adjusted_mode->vdisplay = mode->vdisplay;
 236                 }
 237                 adjusted_mode->base.id = mode_id;
 238         }
 239
 240         /* get the native mode for TV */
 241         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 242                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 243                 if (tv_dac) {
 244                         if (tv_dac->tv_std == TV_STD_NTSC ||
 245                             tv_dac->tv_std == TV_STD_NTSC_J ||
 246                             tv_dac->tv_std == TV_STD_PAL_M)
 247                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 248                         else
 249                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 250                 }
 251         }
 252
 253         return true;
 254 }
 255
 256 static void
 257 atombios_dac_setup(struct drm_encoder *encoder, int action)
 258 {
 259         struct drm_device *dev = encoder->dev;
 260         struct radeon_device *rdev = dev->dev_private;
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 263         int index = 0, num = 0;
 264         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 265         enum radeon_tv_std tv_std = TV_STD_NTSC;
 266
 267         if (dac_info->tv_std)
 268                 tv_std = dac_info->tv_std;
 269
 270         memset(&args, 0, sizeof(args));
 271
 272         switch (radeon_encoder->encoder_id) {
 273         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 274         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 275                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 276                 num = 1;
 277                 break;
 278         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 279         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 280                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 281                 num = 2;
 282                 break;
 283         }
 284
 285         args.ucAction = action;
 286
 287         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 288                 args.ucDacStandard = ATOM_DAC1_PS2;
 289         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 290                 args.ucDacStandard = ATOM_DAC1_CV;
 291         else {
 292                 switch (tv_std) {
 293                 case TV_STD_PAL:
 294                 case TV_STD_PAL_M:
 295                 case TV_STD_SCART_PAL:
 296                 case TV_STD_SECAM:
 297                 case TV_STD_PAL_CN:
 298                         args.ucDacStandard = ATOM_DAC1_PAL;
 299                         break;
 300                 case TV_STD_NTSC:
 301                 case TV_STD_NTSC_J:
 302                 case TV_STD_PAL_60:
 303                 default:
 304                         args.ucDacStandard = ATOM_DAC1_NTSC;
 305                         break;
 306                 }
 307         }
 308         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 309
 310         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 311
 312 }
 313
 314 static void
 315 atombios_tv_setup(struct drm_encoder *encoder, int action)
 316 {
 317         struct drm_device *dev = encoder->dev;
 318         struct radeon_device *rdev = dev->dev_private;
 319         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 320         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 321         int index = 0;
 322         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 323         enum radeon_tv_std tv_std = TV_STD_NTSC;
 324
 325         if (dac_info->tv_std)
 326                 tv_std = dac_info->tv_std;
 327
 328         memset(&args, 0, sizeof(args));
 329
 330         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 331
 332         args.sTVEncoder.ucAction = action;
 333
 334         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 335                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 336         else {
 337                 switch (tv_std) {
 338                 case TV_STD_NTSC:
 339                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 340                         break;
 341                 case TV_STD_PAL:
 342                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 343                         break;
 344                 case TV_STD_PAL_M:
 345                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 346                         break;
 347                 case TV_STD_PAL_60:
 348                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 349                         break;
 350                 case TV_STD_NTSC_J:
 351                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 352                         break;
 353                 case TV_STD_SCART_PAL:
 354                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 355                         break;
 356                 case TV_STD_SECAM:
 357                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 358                         break;
 359                 case TV_STD_PAL_CN:
 360                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 361                         break;
 362                 default:
 363                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 364                         break;
 365                 }
 366         }
 367
 368         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 369
 370         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 371
 372 }
 373
 374 void
 375 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 376 {
 377         struct drm_device *dev = encoder->dev;
 378         struct radeon_device *rdev = dev->dev_private;
 379         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 380         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 381         int index = 0;
 382
 383         memset(&args, 0, sizeof(args));
 384
 385         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 386
 387         args.sXTmdsEncoder.ucEnable = action;
 388
 389         if (radeon_encoder->pixel_clock > 165000)
 390                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 391
 392         /*if (pScrn->rgbBits == 8)*/
 393         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 394
 395         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 396
 397 }
 398
 399 static void
 400 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 401 {
 402         struct drm_device *dev = encoder->dev;
 403         struct radeon_device *rdev = dev->dev_private;
 404         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 405         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 406         int index = 0;
 407
 408         memset(&args, 0, sizeof(args));
 409
 410         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 411
 412         args.sDVOEncoder.ucAction = action;
 413         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 414
 415         if (radeon_encoder->pixel_clock > 165000)
 416                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 417
 418         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 419
 420 }
 421
 422 union lvds_encoder_control {
 423         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 424         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 425 };
 426
 427 void
 428 atombios_digital_setup(struct drm_encoder *encoder, int action)
 429 {
 430         struct drm_device *dev = encoder->dev;
 431         struct radeon_device *rdev = dev->dev_private;
 432         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 433         union lvds_encoder_control args;
 434         int index = 0;
 435         uint8_t frev, crev;
 436         struct radeon_encoder_atom_dig *dig;
 437         struct drm_connector *connector;
 438         struct radeon_connector *radeon_connector;
 439         struct radeon_connector_atom_dig *dig_connector;
 440
 441         connector = radeon_get_connector_for_encoder(encoder);
 442         if (!connector)
 443                 return;
 444
 445         radeon_connector = to_radeon_connector(connector);
 446
 447         if (!radeon_encoder->enc_priv)
 448                 return;
 449
 450         dig = radeon_encoder->enc_priv;
 451
 452         if (!radeon_connector->con_priv)
 453                 return;
 454
 455         dig_connector = radeon_connector->con_priv;
 456
 457         memset(&args, 0, sizeof(args));
 458
 459         switch (radeon_encoder->encoder_id) {
 460         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 461                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 462                 break;
 463         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 464         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 465                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 466                 break;
 467         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 468                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 469                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 470                 else
 471                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 472                 break;
 473         }
 474
 475         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 476
 477         switch (frev) {
 478         case 1:
 479         case 2:
 480                 switch (crev) {
 481                 case 1:
 482                         args.v1.ucMisc = 0;
 483                         args.v1.ucAction = action;
 484                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 485                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 486                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 487                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 488                                 if (dig->lvds_misc & (1 << 0))
 489                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 490                                 if (dig->lvds_misc & (1 << 1))
 491                                         args.v1.ucMisc |= (1 << 1);
 492                         } else {
 493                                 if (dig_connector->linkb)
 494                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 495                                 if (radeon_encoder->pixel_clock > 165000)
 496                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 497                                 /*if (pScrn->rgbBits == 8) */
 498                                 args.v1.ucMisc |= (1 << 1);
 499                         }
 500                         break;
 501                 case 2:
 502                 case 3:
 503                         args.v2.ucMisc = 0;
 504                         args.v2.ucAction = action;
 505                         if (crev == 3) {
 506                                 if (dig->coherent_mode)
 507                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 508                         }
 509                         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 510                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 511                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 512                         args.v2.ucTruncate = 0;
 513                         args.v2.ucSpatial = 0;
 514                         args.v2.ucTemporal = 0;
 515                         args.v2.ucFRC = 0;
 516                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 517                                 if (dig->lvds_misc & (1 << 0))
 518                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 519                                 if (dig->lvds_misc & (1 << 5)) {
 520                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 521                                         if (dig->lvds_misc & (1 << 1))
 522                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 523                                 }
 524                                 if (dig->lvds_misc & (1 << 6)) {
 525                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 526                                         if (dig->lvds_misc & (1 << 1))
 527                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 528                                         if (((dig->lvds_misc >> 2) & 0x3) == 2)
 529                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 530                                 }
 531                         } else {
 532                                 if (dig_connector->linkb)
 533                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 534                                 if (radeon_encoder->pixel_clock > 165000)
 535                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 536                         }
 537                         break;
 538                 default:
 539                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 540                         break;
 541                 }
 542                 break;
 543         default:
 544                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 545                 break;
 546         }
 547
 548         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 549
 550 }
 551
 552 int
 553 atombios_get_encoder_mode(struct drm_encoder *encoder)
 554 {
 555         struct drm_connector *connector;
 556         struct radeon_connector *radeon_connector;
 557
 558         connector = radeon_get_connector_for_encoder(encoder);
 559         if (!connector)
 560                 return 0;
 561
 562         radeon_connector = to_radeon_connector(connector);
 563
 564         switch (connector->connector_type) {
 565         case DRM_MODE_CONNECTOR_DVII:
 566         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 567                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 568                         return ATOM_ENCODER_MODE_HDMI;
 569                 else if (radeon_connector->use_digital)
 570                         return ATOM_ENCODER_MODE_DVI;
 571                 else
 572                         return ATOM_ENCODER_MODE_CRT;
 573                 break;
 574         case DRM_MODE_CONNECTOR_DVID:
 575         case DRM_MODE_CONNECTOR_HDMIA:
 576         default:
 577                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 578                         return ATOM_ENCODER_MODE_HDMI;
 579                 else
 580                         return ATOM_ENCODER_MODE_DVI;
 581                 break;
 582         case DRM_MODE_CONNECTOR_LVDS:
 583                 return ATOM_ENCODER_MODE_LVDS;
 584                 break;
 585         case DRM_MODE_CONNECTOR_DisplayPort:
 586                 /*if (radeon_output->MonType == MT_DP)
 587                   return ATOM_ENCODER_MODE_DP;
 588                   else*/
 589                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 590                         return ATOM_ENCODER_MODE_HDMI;
 591                 else
 592                         return ATOM_ENCODER_MODE_DVI;
 593                 break;
 594         case CONNECTOR_DVI_A:
 595         case CONNECTOR_VGA:
 596                 return ATOM_ENCODER_MODE_CRT;
 597                 break;
 598         case CONNECTOR_STV:
 599         case CONNECTOR_CTV:
 600         case CONNECTOR_DIN:
 601                 /* fix me */
 602                 return ATOM_ENCODER_MODE_TV;
 603                 /*return ATOM_ENCODER_MODE_CV;*/
 604                 break;
 605         }
 606 }
 607
 608 /*
 609  * DIG Encoder/Transmitter Setup
 610  *
 611  * DCE 3.0/3.1
 612  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 613  * Supports up to 3 digital outputs
 614  * - 2 DIG encoder blocks.
 615  * DIG1 can drive UNIPHY link A or link B
 616  * DIG2 can drive UNIPHY link B or LVTMA
 617  *
 618  * DCE 3.2
 619  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 620  * Supports up to 5 digital outputs
 621  * - 2 DIG encoder blocks.
 622  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 623  *
 624  * Routing
 625  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 626  * Examples:
 627  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 628  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 629  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 630  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 631  */
 632 static void
 633 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 634 {
 635         struct drm_device *dev = encoder->dev;
 636         struct radeon_device *rdev = dev->dev_private;
 637         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 638         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 639         int index = 0, num = 0;
 640         uint8_t frev, crev;
 641         struct radeon_encoder_atom_dig *dig;
 642         struct drm_connector *connector;
 643         struct radeon_connector *radeon_connector;
 644         struct radeon_connector_atom_dig *dig_connector;
 645
 646         connector = radeon_get_connector_for_encoder(encoder);
 647         if (!connector)
 648                 return;
 649
 650         radeon_connector = to_radeon_connector(connector);
 651
 652         if (!radeon_connector->con_priv)
 653                 return;
 654
 655         dig_connector = radeon_connector->con_priv;
 656
 657         if (!radeon_encoder->enc_priv)
 658                 return;
 659
 660         dig = radeon_encoder->enc_priv;
 661
 662         memset(&args, 0, sizeof(args));
 663
 664         if (ASIC_IS_DCE32(rdev)) {
 665                 if (dig->dig_block)
 666                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 667                 else
 668                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 669                 num = dig->dig_block + 1;
 670         } else {
 671                 switch (radeon_encoder->encoder_id) {
 672                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 673                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 674                          * not already in use
 675                          */
 676                         if (dig_connector->linkb)
 677                                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 678                         else
 679                                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 680                         num = 1;
 681                         break;
 682                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 683                         /* Only dig2 encoder can drive LVTMA */
 684                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 685                         num = 2;
 686                         break;
 687                 }
 688         }
 689
 690         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 691
 692         args.ucAction = action;
 693         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 694
 695         if (ASIC_IS_DCE32(rdev)) {
 696                 switch (radeon_encoder->encoder_id) {
 697                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 698                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 699                         break;
 700                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 701                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 702                         break;
 703                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 704                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 705                         break;
 706                 }
 707         } else {
 708                 switch (radeon_encoder->encoder_id) {
 709                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 710                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 711                         break;
 712                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 713                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 714                         break;
 715                 }
 716         }
 717
 718         if (radeon_encoder->pixel_clock > 165000)
 719                 args.ucLaneNum = 8;
 720         else
 721                 args.ucLaneNum = 4;
 722
 723         if (dig_connector->linkb)
 724                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 725         else
 726                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 727
 728         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 729
 730         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 731
 732 }
 733
 734 union dig_transmitter_control {
 735         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 736         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 737 };
 738
 739 static void
 740 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 741 {
 742         struct drm_device *dev = encoder->dev;
 743         struct radeon_device *rdev = dev->dev_private;
 744         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 745         union dig_transmitter_control args;
 746         int index = 0, num = 0;
 747         uint8_t frev, crev;
 748         struct radeon_encoder_atom_dig *dig;
 749         struct drm_connector *connector;
 750         struct radeon_connector *radeon_connector;
 751         struct radeon_connector_atom_dig *dig_connector;
 752
 753         connector = radeon_get_connector_for_encoder(encoder);
 754         if (!connector)
 755                 return;
 756
 757         radeon_connector = to_radeon_connector(connector);
 758
 759         if (!radeon_encoder->enc_priv)
 760                 return;
 761
 762         dig = radeon_encoder->enc_priv;
 763
 764         if (!radeon_connector->con_priv)
 765                 return;
 766
 767         dig_connector = radeon_connector->con_priv;
 768
 769         memset(&args, 0, sizeof(args));
 770
 771         if (ASIC_IS_DCE32(rdev))
 772                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 773         else {
 774                 switch (radeon_encoder->encoder_id) {
 775                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 776                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 777                         break;
 778                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 779                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 780                         break;
 781                 }
 782         }
 783
 784         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 785
 786         args.v1.ucAction = action;
 787         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 788                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 789         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 790                 args.v1.asMode.ucLaneSel = lane_num;
 791                 args.v1.asMode.ucLaneSet = lane_set;
 792         } else {
 793                 if (radeon_encoder->pixel_clock > 165000)
 794                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 795                 else
 796                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 797         }
 798         if (ASIC_IS_DCE32(rdev)) {
 799                 if (radeon_encoder->pixel_clock > 165000)
 800                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 801                 if (dig->dig_block)
 802                         args.v2.acConfig.ucEncoderSel = 1;
 803                 if (dig_connector->linkb)
 804                         args.v2.acConfig.ucLinkSel = 1;
 805
 806                 switch (radeon_encoder->encoder_id) {
 807                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 808                         args.v2.acConfig.ucTransmitterSel = 0;
 809                         num = 0;
 810                         break;
 811                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 812                         args.v2.acConfig.ucTransmitterSel = 1;
 813                         num = 1;
 814                         break;
 815                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 816                         args.v2.acConfig.ucTransmitterSel = 2;
 817                         num = 2;
 818                         break;
 819                 }
 820
 821                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 822                         if (dig->coherent_mode)
 823                                 args.v2.acConfig.fCoherentMode = 1;
 824                 }
 825         } else {
 826                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 827
 828                 switch (radeon_encoder->encoder_id) {
 829                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 830                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 831                          * not already in use
 832                          */
 833                         if (dig_connector->linkb)
 834                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 835                         else
 836                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 837                         if (rdev->flags & RADEON_IS_IGP) {
 838                                 if (radeon_encoder->pixel_clock > 165000) {
 839                                         if (dig_connector->igp_lane_info & 0x3)
 840                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 841                                         else if (dig_connector->igp_lane_info & 0xc)
 842                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 843                                 } else {
 844                                         if (dig_connector->igp_lane_info & 0x1)
 845                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 846                                         else if (dig_connector->igp_lane_info & 0x2)
 847                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 848                                         else if (dig_connector->igp_lane_info & 0x4)
 849                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 850                                         else if (dig_connector->igp_lane_info & 0x8)
 851                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 852                                 }
 853                         }
 854                         break;
 855                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 856                         /* Only dig2 encoder can drive LVTMA */
 857                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 858                         break;
 859                 }
 860
 861                 if (radeon_encoder->pixel_clock > 165000)
 862                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 863
 864                 if (dig_connector->linkb)
 865                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 866                 else
 867                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 868
 869                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 870                         if (dig->coherent_mode)
 871                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 872                 }
 873         }
 874
 875         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 876
 877 }
 878
 879 static void
 880 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 881 {
 882         struct drm_device *dev = encoder->dev;
 883         struct radeon_device *rdev = dev->dev_private;
 884         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 885         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 886         ENABLE_YUV_PS_ALLOCATION args;
 887         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 888         uint32_t temp, reg;
 889
 890         memset(&args, 0, sizeof(args));
 891
 892         if (rdev->family >= CHIP_R600)
 893                 reg = R600_BIOS_3_SCRATCH;
 894         else
 895                 reg = RADEON_BIOS_3_SCRATCH;
 896
 897         /* XXX: fix up scratch reg handling */
 898         temp = RREG32(reg);
 899         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 900                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 901                              (radeon_crtc->crtc_id << 18)));
 902         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 903                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 904         else
 905                 WREG32(reg, 0);
 906
 907         if (enable)
 908                 args.ucEnable = ATOM_ENABLE;
 909         args.ucCRTC = radeon_crtc->crtc_id;
 910
 911         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 912
 913         WREG32(reg, temp);
 914 }
 915
 916 static void
 917 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 918 {
 919         struct drm_device *dev = encoder->dev;
 920         struct radeon_device *rdev = dev->dev_private;
 921         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 922         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 923         int index = 0;
 924         bool is_dig = false;
 925
 926         memset(&args, 0, sizeof(args));
 927
 928         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 929                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 930                   radeon_encoder->active_device);
 931         switch (radeon_encoder->encoder_id) {
 932         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 933         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 934                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 935                 break;
 936         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 937         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 938         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 939         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 940                 is_dig = true;
 941                 break;
 942         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 943         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 944         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 945                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 946                 break;
 947         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 948                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 949                 break;
 950         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 951                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 952                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 953                 else
 954                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 955                 break;
 956         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 957         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 958                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 959                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 960                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 961                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 962                 else
 963                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 964                 break;
 965         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 966         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 967                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 968                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 969                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 970                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 971                 else
 972                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 973                 break;
 974         }
 975
 976         if (is_dig) {
 977                 switch (mode) {
 978                 case DRM_MODE_DPMS_ON:
 979                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
 980                         break;
 981                 case DRM_MODE_DPMS_STANDBY:
 982                 case DRM_MODE_DPMS_SUSPEND:
 983                 case DRM_MODE_DPMS_OFF:
 984                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT);
 985                         break;
 986                 }
 987         } else {
 988                 switch (mode) {
 989                 case DRM_MODE_DPMS_ON:
 990                         args.ucAction = ATOM_ENABLE;
 991                         break;
 992                 case DRM_MODE_DPMS_STANDBY:
 993                 case DRM_MODE_DPMS_SUSPEND:
 994                 case DRM_MODE_DPMS_OFF:
 995                         args.ucAction = ATOM_DISABLE;
 996                         break;
 997                 }
 998                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 999         }
1000         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1001 }
1002
1003 union crtc_sourc_param {
1004         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1005         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1006 };
1007
1008 static void
1009 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1010 {
1011         struct drm_device *dev = encoder->dev;
1012         struct radeon_device *rdev = dev->dev_private;
1013         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1014         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1015         union crtc_sourc_param args;
1016         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1017         uint8_t frev, crev;
1018
1019         memset(&args, 0, sizeof(args));
1020
1021         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1022
1023         switch (frev) {
1024         case 1:
1025                 switch (crev) {
1026                 case 1:
1027                 default:
1028                         if (ASIC_IS_AVIVO(rdev))
1029                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1030                         else {
1031                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1032                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1033                                 } else {
1034                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1035                                 }
1036                         }
1037                         switch (radeon_encoder->encoder_id) {
1038                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1039                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1040                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1041                                 break;
1042                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1043                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1044                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1045                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1046                                 else
1047                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1048                                 break;
1049                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1050                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1051                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1052                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1053                                 break;
1054                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1055                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1056                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1057                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1058                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1059                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1060                                 else
1061                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1062                                 break;
1063                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1064                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1065                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1066                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1067                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1068                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1069                                 else
1070                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1071                                 break;
1072                         }
1073                         break;
1074                 case 2:
1075                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1076                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1077                         switch (radeon_encoder->encoder_id) {
1078                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1079                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1080                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1081                                 if (ASIC_IS_DCE32(rdev)) {
1082                                         if (radeon_crtc->crtc_id)
1083                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1084                                         else
1085                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1086                                 } else {
1087                                         struct drm_connector *connector;
1088                                         struct radeon_connector *radeon_connector;
1089                                         struct radeon_connector_atom_dig *dig_connector;
1090
1091                                         connector = radeon_get_connector_for_encoder(encoder);
1092                                         if (!connector)
1093                                                 return;
1094                                         radeon_connector = to_radeon_connector(connector);
1095                                         if (!radeon_connector->con_priv)
1096                                                 return;
1097                                         dig_connector = radeon_connector->con_priv;
1098
1099                                         /* XXX doesn't really matter which dig encoder we pick as long as it's
1100                                          * not already in use
1101                                          */
1102                                         if (dig_connector->linkb)
1103                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1104                                         else
1105                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1106                                 }
1107                                 break;
1108                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1109                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1110                                 break;
1111                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1112                                 /* Only dig2 encoder can drive LVTMA */
1113                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1114                                 break;
1115                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1116                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1117                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1118                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1119                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1120                                 else
1121                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1122                                 break;
1123                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1124                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1126                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1127                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1128                                 else
1129                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1130                                 break;
1131                         }
1132                         break;
1133                 }
1134                 break;
1135         default:
1136                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1137                 break;
1138         }
1139
1140         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1141
1142 }
1143
1144 static void
1145 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1146                               struct drm_display_mode *mode)
1147 {
1148         struct drm_device *dev = encoder->dev;
1149         struct radeon_device *rdev = dev->dev_private;
1150         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1151         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1152
1153         /* Funky macbooks */
1154         if ((dev->pdev->device == 0x71C5) &&
1155             (dev->pdev->subsystem_vendor == 0x106b) &&
1156             (dev->pdev->subsystem_device == 0x0080)) {
1157                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1158                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1159
1160                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1161                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1162
1163                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1164                 }
1165         }
1166
1167         /* set scaler clears this on some chips */
1168         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1169                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1170                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1171                                AVIVO_D1MODE_INTERLEAVE_EN);
1172         }
1173 }
1174
1175 static void
1176 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1177                              struct drm_display_mode *mode,
1178                              struct drm_display_mode *adjusted_mode)
1179 {
1180         struct drm_device *dev = encoder->dev;
1181         struct radeon_device *rdev = dev->dev_private;
1182         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1183         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1184
1185         if (radeon_encoder->enc_priv) {
1186                 struct radeon_encoder_atom_dig *dig;
1187
1188                 dig = radeon_encoder->enc_priv;
1189                 dig->dig_block = radeon_crtc->crtc_id;
1190         }
1191         radeon_encoder->pixel_clock = adjusted_mode->clock;
1192
1193         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1194         atombios_set_encoder_crtc_source(encoder);
1195
1196         if (ASIC_IS_AVIVO(rdev)) {
1197                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1198                         atombios_yuv_setup(encoder, true);
1199                 else
1200                         atombios_yuv_setup(encoder, false);
1201         }
1202
1203         switch (radeon_encoder->encoder_id) {
1204         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1205         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1206         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1207         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1208                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1209                 break;
1210         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1211         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1212         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1213         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1214                 /* disable the encoder and transmitter */
1215                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1216                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1217
1218                 /* setup and enable the encoder and transmitter */
1219                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1220                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1221                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1222                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1223                 break;
1224         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1225                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1226                 break;
1227         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1228         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1229                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1230                 break;
1231         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1232         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1233         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1234         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1235                 atombios_dac_setup(encoder, ATOM_ENABLE);
1236                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1237                         atombios_tv_setup(encoder, ATOM_ENABLE);
1238                 break;
1239         }
1240         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1241 }
1242
1243 static bool
1244 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1245 {
1246         struct drm_device *dev = encoder->dev;
1247         struct radeon_device *rdev = dev->dev_private;
1248         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1249         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1250
1251         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1252                                        ATOM_DEVICE_CV_SUPPORT |
1253                                        ATOM_DEVICE_CRT_SUPPORT)) {
1254                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1255                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1256                 uint8_t frev, crev;
1257
1258                 memset(&args, 0, sizeof(args));
1259
1260                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1261
1262                 args.sDacload.ucMisc = 0;
1263
1264                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1265                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1266                         args.sDacload.ucDacType = ATOM_DAC_A;
1267                 else
1268                         args.sDacload.ucDacType = ATOM_DAC_B;
1269
1270                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1271                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1272                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1273                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1274                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1275                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1276                         if (crev >= 3)
1277                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1278                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1279                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1280                         if (crev >= 3)
1281                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1282                 }
1283
1284                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1285
1286                 return true;
1287         } else
1288                 return false;
1289 }
1290
1291 static enum drm_connector_status
1292 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1293 {
1294         struct drm_device *dev = encoder->dev;
1295         struct radeon_device *rdev = dev->dev_private;
1296         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1297         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1298         uint32_t bios_0_scratch;
1299
1300         if (!atombios_dac_load_detect(encoder, connector)) {
1301                 DRM_DEBUG("detect returned false \n");
1302                 return connector_status_unknown;
1303         }
1304
1305         if (rdev->family >= CHIP_R600)
1306                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1307         else
1308                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1309
1310         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1311         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1312                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1313                         return connector_status_connected;
1314         }
1315         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1316                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1317                         return connector_status_connected;
1318         }
1319         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1320                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1321                         return connector_status_connected;
1322         }
1323         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1324                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1325                         return connector_status_connected; /* CTV */
1326                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1327                         return connector_status_connected; /* STV */
1328         }
1329         return connector_status_disconnected;
1330 }
1331
1332 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1333 {
1334         radeon_atom_output_lock(encoder, true);
1335         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1336 }
1337
1338 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1339 {
1340         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1341         radeon_atom_output_lock(encoder, false);
1342 }
1343
1344 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1345 {
1346         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1347         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1348         radeon_encoder->active_device = 0;
1349 }
1350
1351 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1352         .dpms = radeon_atom_encoder_dpms,
1353         .mode_fixup = radeon_atom_mode_fixup,
1354         .prepare = radeon_atom_encoder_prepare,
1355         .mode_set = radeon_atom_encoder_mode_set,
1356         .commit = radeon_atom_encoder_commit,
1357         .disable = radeon_atom_encoder_disable,
1358         /* no detect for TMDS/LVDS yet */
1359 };
1360
1361 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1362         .dpms = radeon_atom_encoder_dpms,
1363         .mode_fixup = radeon_atom_mode_fixup,
1364         .prepare = radeon_atom_encoder_prepare,
1365         .mode_set = radeon_atom_encoder_mode_set,
1366         .commit = radeon_atom_encoder_commit,
1367         .detect = radeon_atom_dac_detect,
1368 };
1369
1370 void radeon_enc_destroy(struct drm_encoder *encoder)
1371 {
1372         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1373         kfree(radeon_encoder->enc_priv);
1374         drm_encoder_cleanup(encoder);
1375         kfree(radeon_encoder);
1376 }
1377
1378 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1379         .destroy = radeon_enc_destroy,
1380 };
1381
1382 struct radeon_encoder_atom_dac *
1383 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1384 {
1385         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1386
1387         if (!dac)
1388                 return NULL;
1389
1390         dac->tv_std = TV_STD_NTSC;
1391         return dac;
1392 }
1393
1394 struct radeon_encoder_atom_dig *
1395 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1396 {
1397         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1398
1399         if (!dig)
1400                 return NULL;
1401
1402         /* coherent mode by default */
1403         dig->coherent_mode = true;
1404
1405         return dig;
1406 }
1407
1408 void
1409 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1410 {
1411         struct radeon_device *rdev = dev->dev_private;
1412         struct drm_encoder *encoder;
1413         struct radeon_encoder *radeon_encoder;
1414
1415         /* see if we already added it */
1416         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1417                 radeon_encoder = to_radeon_encoder(encoder);
1418                 if (radeon_encoder->encoder_id == encoder_id) {
1419                         radeon_encoder->devices |= supported_device;
1420                         return;
1421                 }
1422
1423         }
1424
1425         /* add a new one */
1426         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1427         if (!radeon_encoder)
1428                 return;
1429
1430         encoder = &radeon_encoder->base;
1431         if (rdev->flags & RADEON_SINGLE_CRTC)
1432                 encoder->possible_crtcs = 0x1;
1433         else
1434                 encoder->possible_crtcs = 0x3;
1435
1436         radeon_encoder->enc_priv = NULL;
1437
1438         radeon_encoder->encoder_id = encoder_id;
1439         radeon_encoder->devices = supported_device;
1440         radeon_encoder->rmx_type = RMX_OFF;
1441
1442         switch (radeon_encoder->encoder_id) {
1443         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1444         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1445         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1446         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1447                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1448                         radeon_encoder->rmx_type = RMX_FULL;
1449                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1450                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1451                 } else {
1452                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1453                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1454                 }
1455                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1456                 break;
1457         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1458                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1459                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1460                 break;
1461         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1462         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1463         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1464                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1465                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1466                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1467                 break;
1468         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1469         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1470         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1471         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1472         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1473         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1474         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1475                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1476                         radeon_encoder->rmx_type = RMX_FULL;
1477                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1478                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1479                 } else {
1480                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1481                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1482                 }
1483                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1484                 break;
1485         }
1486 }