SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  47 {
  48         u32 val;
  49
  50         if (dev_priv->flags & RADEON_IS_AGP) {
  51                 val = DRM_READ32(dev_priv->ring_rptr, off);
  52         } else {
  53                 val = *(((volatile u32 *)
  54                          dev_priv->ring_rptr->handle) +
  55                         (off / sizeof(u32)));
  56                 val = le32_to_cpu(val);
  57         }
  58         return val;
  59 }
  60
  61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  62 {
  63         if (dev_priv->writeback_works)
  64                 return radeon_read_ring_rptr(dev_priv, 0);
  65         else {
  66                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  67                         return RADEON_READ(R600_CP_RB_RPTR);
  68                 else
  69                         return RADEON_READ(RADEON_CP_RB_RPTR);
  70         }
  71 }
  72
  73 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  74 {
  75         if (dev_priv->flags & RADEON_IS_AGP)
  76                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  77         else
  78                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  79                   (off / sizeof(u32))) = cpu_to_le32(val);
  80 }
  81
  82 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  83 {
  84         radeon_write_ring_rptr(dev_priv, 0, val);
  85 }
  86
  87 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  88 {
  89         if (dev_priv->writeback_works) {
  90                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  91                         return radeon_read_ring_rptr(dev_priv,
  92                                                      R600_SCRATCHOFF(index));
  93                 else
  94                         return radeon_read_ring_rptr(dev_priv,
  95                                                      RADEON_SCRATCHOFF(index));
  96         } else {
  97                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  98                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
  99                 else
 100                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 101         }
 102 }
 103
 104 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 105 {
 106         u32 ret;
 107
 108         if (addr < 0x10000)
 109                 ret = DRM_READ32(dev_priv->mmio, addr);
 110         else {
 111                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 112                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 113         }
 114
 115         return ret;
 116 }
 117
 118 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 119 {
 120         u32 ret;
 121         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 122         ret = RADEON_READ(R520_MC_IND_DATA);
 123         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 124         return ret;
 125 }
 126
 127 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 128 {
 129         u32 ret;
 130         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 131         ret = RADEON_READ(RS480_NB_MC_DATA);
 132         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 133         return ret;
 134 }
 135
 136 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 137 {
 138         u32 ret;
 139         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 140         ret = RADEON_READ(RS690_MC_DATA);
 141         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 142         return ret;
 143 }
 144
 145 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 146 {
 147         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 148             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 149                 return RS690_READ_MCIND(dev_priv, addr);
 150         else
 151                 return RS480_READ_MCIND(dev_priv, addr);
 152 }
 153
 154 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 155 {
 156
 157         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 158                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 159         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 160                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 161         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 162                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 163         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 164                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 165                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 166         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 167                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 168         else
 169                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 170 }
 171
 172 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 173 {
 174         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 175                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 176         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 177                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 178         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 179                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 180         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 181                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 182                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 183         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 184                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 185         else
 186                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 187 }
 188
 189 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 190 {
 191         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 192         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 193                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 194                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 195         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 196                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 197                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 198         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 199                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 200         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 201                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 202                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 203         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 204                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 205         else
 206                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 207 }
 208
 209 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 210 {
 211         u32 agp_base_hi = upper_32_bits(agp_base);
 212         u32 agp_base_lo = agp_base & 0xffffffff;
 213         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 214
 215         /* R6xx/R7xx must be aligned to a 4MB boundry */
 216         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 217                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 218         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 219                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 220         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 221                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 222                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 223         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 224                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 225                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 226                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 227         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 228                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 229                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 230         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 231                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 232                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 233                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 234         } else {
 235                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 236                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 237                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 238         }
 239 }
 240
 241 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 242 {
 243         u32 tmp;
 244         /* Turn on bus mastering */
 245         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 246             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 247                 /* rs600/rs690/rs740 */
 248                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 249                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 250         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 251                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 252                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 253                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 254                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 255                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 256                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 257         } /* PCIE cards appears to not need this */
 258 }
 259
 260 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 261 {
 262         drm_radeon_private_t *dev_priv = dev->dev_private;
 263
 264         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 265         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 266 }
 267
 268 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 269 {
 270         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 271         return RADEON_READ(RADEON_PCIE_DATA);
 272 }
 273
 274 #if RADEON_FIFO_DEBUG
 275 static void radeon_status(drm_radeon_private_t * dev_priv)
 276 {
 277         printk("%s:\n", __func__);
 278         printk("RBBM_STATUS = 0x%08x\n",
 279                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 280         printk("CP_RB_RTPR = 0x%08x\n",
 281                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 282         printk("CP_RB_WTPR = 0x%08x\n",
 283                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 284         printk("AIC_CNTL = 0x%08x\n",
 285                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 286         printk("AIC_STAT = 0x%08x\n",
 287                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 288         printk("AIC_PT_BASE = 0x%08x\n",
 289                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 290         printk("TLB_ADDR = 0x%08x\n",
 291                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 292         printk("TLB_DATA = 0x%08x\n",
 293                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 294 }
 295 #endif
 296
 297 /* ================================================================
 298  * Engine, FIFO control
 299  */
 300
 301 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 302 {
 303         u32 tmp;
 304         int i;
 305
 306         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 307
 308         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 309                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 310                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 311                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 312
 313                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 314                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 315                               & RADEON_RB3D_DC_BUSY)) {
 316                                 return 0;
 317                         }
 318                         DRM_UDELAY(1);
 319                 }
 320         } else {
 321                 /* don't flush or purge cache here or lockup */
 322                 return 0;
 323         }
 324
 325 #if RADEON_FIFO_DEBUG
 326         DRM_ERROR("failed!\n");
 327         radeon_status(dev_priv);
 328 #endif
 329         return -EBUSY;
 330 }
 331
 332 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 333 {
 334         int i;
 335
 336         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 337
 338         for (i = 0; i < dev_priv->usec_timeout; i++) {
 339                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 340                              & RADEON_RBBM_FIFOCNT_MASK);
 341                 if (slots >= entries)
 342                         return 0;
 343                 DRM_UDELAY(1);
 344         }
 345         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 346                  RADEON_READ(RADEON_RBBM_STATUS),
 347                  RADEON_READ(R300_VAP_CNTL_STATUS));
 348
 349 #if RADEON_FIFO_DEBUG
 350         DRM_ERROR("failed!\n");
 351         radeon_status(dev_priv);
 352 #endif
 353         return -EBUSY;
 354 }
 355
 356 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 357 {
 358         int i, ret;
 359
 360         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 361
 362         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 363         if (ret)
 364                 return ret;
 365
 366         for (i = 0; i < dev_priv->usec_timeout; i++) {
 367                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 368                       & RADEON_RBBM_ACTIVE)) {
 369                         radeon_do_pixcache_flush(dev_priv);
 370                         return 0;
 371                 }
 372                 DRM_UDELAY(1);
 373         }
 374         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 375                  RADEON_READ(RADEON_RBBM_STATUS),
 376                  RADEON_READ(R300_VAP_CNTL_STATUS));
 377
 378 #if RADEON_FIFO_DEBUG
 379         DRM_ERROR("failed!\n");
 380         radeon_status(dev_priv);
 381 #endif
 382         return -EBUSY;
 383 }
 384
 385 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 386 {
 387         uint32_t gb_tile_config, gb_pipe_sel = 0;
 388
 389         /* RS4xx/RS6xx/R4xx/R5xx */
 390         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 391                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 392                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 393         } else {
 394                 /* R3xx */
 395                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 396                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 397                         dev_priv->num_gb_pipes = 2;
 398                 } else {
 399                         /* R3Vxx */
 400                         dev_priv->num_gb_pipes = 1;
 401                 }
 402         }
 403         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 404
 405         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 406
 407         switch (dev_priv->num_gb_pipes) {
 408         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 409         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 410         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 411         default:
 412         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 413         }
 414
 415         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 416                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 417                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 418         }
 419         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 420         radeon_do_wait_for_idle(dev_priv);
 421         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 422         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 423                                                R300_DC_AUTOFLUSH_ENABLE |
 424                                                R300_DC_DC_DISABLE_IGNORE_PE));
 425
 426
 427 }
 428
 429 /* ================================================================
 430  * CP control, initialization
 431  */
 432
 433 /* Load the microcode for the CP */
 434 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 435 {
 436         int i;
 437         DRM_DEBUG("\n");
 438
 439         radeon_do_wait_for_idle(dev_priv);
 440
 441         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 442         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 443             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 444             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 445             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 446             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 447                 DRM_INFO("Loading R100 Microcode\n");
 448                 for (i = 0; i < 256; i++) {
 449                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 450                                      R100_cp_microcode[i][1]);
 451                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 452                                      R100_cp_microcode[i][0]);
 453                 }
 454         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 455                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 456                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 457                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 458                 DRM_INFO("Loading R200 Microcode\n");
 459                 for (i = 0; i < 256; i++) {
 460                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 461                                      R200_cp_microcode[i][1]);
 462                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 463                                      R200_cp_microcode[i][0]);
 464                 }
 465         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 466                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 467                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 468                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 469                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 470                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 471                 DRM_INFO("Loading R300 Microcode\n");
 472                 for (i = 0; i < 256; i++) {
 473                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 474                                      R300_cp_microcode[i][1]);
 475                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 476                                      R300_cp_microcode[i][0]);
 477                 }
 478         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 479                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 480                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 481                 DRM_INFO("Loading R400 Microcode\n");
 482                 for (i = 0; i < 256; i++) {
 483                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 484                                      R420_cp_microcode[i][1]);
 485                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 486                                      R420_cp_microcode[i][0]);
 487                 }
 488         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 489                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 490                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 491                 for (i = 0; i < 256; i++) {
 492                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 493                                      RS690_cp_microcode[i][1]);
 494                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 495                                      RS690_cp_microcode[i][0]);
 496                 }
 497         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 498                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 499                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 500                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 503                 DRM_INFO("Loading R500 Microcode\n");
 504                 for (i = 0; i < 256; i++) {
 505                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 506                                      R520_cp_microcode[i][1]);
 507                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 508                                      R520_cp_microcode[i][0]);
 509                 }
 510         }
 511 }
 512
 513 /* Flush any pending commands to the CP.  This should only be used just
 514  * prior to a wait for idle, as it informs the engine that the command
 515  * stream is ending.
 516  */
 517 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 518 {
 519         DRM_DEBUG("\n");
 520 #if 0
 521         u32 tmp;
 522
 523         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 524         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 525 #endif
 526 }
 527
 528 /* Wait for the CP to go idle.
 529  */
 530 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 531 {
 532         RING_LOCALS;
 533         DRM_DEBUG("\n");
 534
 535         BEGIN_RING(6);
 536
 537         RADEON_PURGE_CACHE();
 538         RADEON_PURGE_ZCACHE();
 539         RADEON_WAIT_UNTIL_IDLE();
 540
 541         ADVANCE_RING();
 542         COMMIT_RING();
 543
 544         return radeon_do_wait_for_idle(dev_priv);
 545 }
 546
 547 /* Start the Command Processor.
 548  */
 549 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 550 {
 551         RING_LOCALS;
 552         DRM_DEBUG("\n");
 553
 554         radeon_do_wait_for_idle(dev_priv);
 555
 556         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 557
 558         dev_priv->cp_running = 1;
 559
 560         BEGIN_RING(8);
 561         /* isync can only be written through cp on r5xx write it here */
 562         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 563         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 564                  RADEON_ISYNC_ANY3D_IDLE2D |
 565                  RADEON_ISYNC_WAIT_IDLEGUI |
 566                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 567         RADEON_PURGE_CACHE();
 568         RADEON_PURGE_ZCACHE();
 569         RADEON_WAIT_UNTIL_IDLE();
 570         ADVANCE_RING();
 571         COMMIT_RING();
 572
 573         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 574 }
 575
 576 /* Reset the Command Processor.  This will not flush any pending
 577  * commands, so you must wait for the CP command stream to complete
 578  * before calling this routine.
 579  */
 580 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 581 {
 582         u32 cur_read_ptr;
 583         DRM_DEBUG("\n");
 584
 585         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 586         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 587         SET_RING_HEAD(dev_priv, cur_read_ptr);
 588         dev_priv->ring.tail = cur_read_ptr;
 589 }
 590
 591 /* Stop the Command Processor.  This will not flush any pending
 592  * commands, so you must flush the command stream and wait for the CP
 593  * to go idle before calling this routine.
 594  */
 595 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 596 {
 597         DRM_DEBUG("\n");
 598
 599         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 600
 601         dev_priv->cp_running = 0;
 602 }
 603
 604 /* Reset the engine.  This will stop the CP if it is running.
 605  */
 606 static int radeon_do_engine_reset(struct drm_device * dev)
 607 {
 608         drm_radeon_private_t *dev_priv = dev->dev_private;
 609         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 610         DRM_DEBUG("\n");
 611
 612         radeon_do_pixcache_flush(dev_priv);
 613
 614         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 615                 /* may need something similar for newer chips */
 616                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 617                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 618
 619                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 620                                                     RADEON_FORCEON_MCLKA |
 621                                                     RADEON_FORCEON_MCLKB |
 622                                                     RADEON_FORCEON_YCLKA |
 623                                                     RADEON_FORCEON_YCLKB |
 624                                                     RADEON_FORCEON_MC |
 625                                                     RADEON_FORCEON_AIC));
 626         }
 627
 628         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 629
 630         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 631                                               RADEON_SOFT_RESET_CP |
 632                                               RADEON_SOFT_RESET_HI |
 633                                               RADEON_SOFT_RESET_SE |
 634                                               RADEON_SOFT_RESET_RE |
 635                                               RADEON_SOFT_RESET_PP |
 636                                               RADEON_SOFT_RESET_E2 |
 637                                               RADEON_SOFT_RESET_RB));
 638         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 639         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 640                                               ~(RADEON_SOFT_RESET_CP |
 641                                                 RADEON_SOFT_RESET_HI |
 642                                                 RADEON_SOFT_RESET_SE |
 643                                                 RADEON_SOFT_RESET_RE |
 644                                                 RADEON_SOFT_RESET_PP |
 645                                                 RADEON_SOFT_RESET_E2 |
 646                                                 RADEON_SOFT_RESET_RB)));
 647         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 648
 649         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 650                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 651                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 652                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 653         }
 654
 655         /* setup the raster pipes */
 656         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 657             radeon_init_pipes(dev_priv);
 658
 659         /* Reset the CP ring */
 660         radeon_do_cp_reset(dev_priv);
 661
 662         /* The CP is no longer running after an engine reset */
 663         dev_priv->cp_running = 0;
 664
 665         /* Reset any pending vertex, indirect buffers */
 666         radeon_freelist_reset(dev);
 667
 668         return 0;
 669 }
 670
 671 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 672                                        drm_radeon_private_t *dev_priv,
 673                                        struct drm_file *file_priv)
 674 {
 675         struct drm_radeon_master_private *master_priv;
 676         u32 ring_start, cur_read_ptr;
 677
 678         /* Initialize the memory controller. With new memory map, the fb location
 679          * is not changed, it should have been properly initialized already. Part
 680          * of the problem is that the code below is bogus, assuming the GART is
 681          * always appended to the fb which is not necessarily the case
 682          */
 683         if (!dev_priv->new_memmap)
 684                 radeon_write_fb_location(dev_priv,
 685                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 686                              | (dev_priv->fb_location >> 16));
 687
 688 #if __OS_HAS_AGP
 689         if (dev_priv->flags & RADEON_IS_AGP) {
 690                 radeon_write_agp_base(dev_priv, dev->agp->base);
 691
 692                 radeon_write_agp_location(dev_priv,
 693                              (((dev_priv->gart_vm_start - 1 +
 694                                 dev_priv->gart_size) & 0xffff0000) |
 695                               (dev_priv->gart_vm_start >> 16)));
 696
 697                 ring_start = (dev_priv->cp_ring->offset
 698                               - dev->agp->base
 699                               + dev_priv->gart_vm_start);
 700         } else
 701 #endif
 702                 ring_start = (dev_priv->cp_ring->offset
 703                               - (unsigned long)dev->sg->virtual
 704                               + dev_priv->gart_vm_start);
 705
 706         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 707
 708         /* Set the write pointer delay */
 709         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 710
 711         /* Initialize the ring buffer's read and write pointers */
 712         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 713         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 714         SET_RING_HEAD(dev_priv, cur_read_ptr);
 715         dev_priv->ring.tail = cur_read_ptr;
 716
 717 #if __OS_HAS_AGP
 718         if (dev_priv->flags & RADEON_IS_AGP) {
 719                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 720                              dev_priv->ring_rptr->offset
 721                              - dev->agp->base + dev_priv->gart_vm_start);
 722         } else
 723 #endif
 724         {
 725                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 726                              dev_priv->ring_rptr->offset
 727                              - ((unsigned long) dev->sg->virtual)
 728                              + dev_priv->gart_vm_start);
 729         }
 730
 731         /* Set ring buffer size */
 732 #ifdef __BIG_ENDIAN
 733         RADEON_WRITE(RADEON_CP_RB_CNTL,
 734                      RADEON_BUF_SWAP_32BIT |
 735                      (dev_priv->ring.fetch_size_l2ow << 18) |
 736                      (dev_priv->ring.rptr_update_l2qw << 8) |
 737                      dev_priv->ring.size_l2qw);
 738 #else
 739         RADEON_WRITE(RADEON_CP_RB_CNTL,
 740                      (dev_priv->ring.fetch_size_l2ow << 18) |
 741                      (dev_priv->ring.rptr_update_l2qw << 8) |
 742                      dev_priv->ring.size_l2qw);
 743 #endif
 744
 745
 746         /* Initialize the scratch register pointer.  This will cause
 747          * the scratch register values to be written out to memory
 748          * whenever they are updated.
 749          *
 750          * We simply put this behind the ring read pointer, this works
 751          * with PCI GART as well as (whatever kind of) AGP GART
 752          */
 753         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 754                      + RADEON_SCRATCH_REG_OFFSET);
 755
 756         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 757
 758         radeon_enable_bm(dev_priv);
 759
 760         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 761         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 762
 763         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 764         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 765
 766         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 767         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 768
 769         /* reset sarea copies of these */
 770         master_priv = file_priv->master->driver_priv;
 771         if (master_priv->sarea_priv) {
 772                 master_priv->sarea_priv->last_frame = 0;
 773                 master_priv->sarea_priv->last_dispatch = 0;
 774                 master_priv->sarea_priv->last_clear = 0;
 775         }
 776
 777         radeon_do_wait_for_idle(dev_priv);
 778
 779         /* Sync everything up */
 780         RADEON_WRITE(RADEON_ISYNC_CNTL,
 781                      (RADEON_ISYNC_ANY2D_IDLE3D |
 782                       RADEON_ISYNC_ANY3D_IDLE2D |
 783                       RADEON_ISYNC_WAIT_IDLEGUI |
 784                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 785
 786 }
 787
 788 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 789 {
 790         u32 tmp;
 791
 792         /* Start with assuming that writeback doesn't work */
 793         dev_priv->writeback_works = 0;
 794
 795         /* Writeback doesn't seem to work everywhere, test it here and possibly
 796          * enable it if it appears to work
 797          */
 798         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 799
 800         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 801
 802         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 803                 u32 val;
 804
 805                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 806                 if (val == 0xdeadbeef)
 807                         break;
 808                 DRM_UDELAY(1);
 809         }
 810
 811         if (tmp < dev_priv->usec_timeout) {
 812                 dev_priv->writeback_works = 1;
 813                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 814         } else {
 815                 dev_priv->writeback_works = 0;
 816                 DRM_INFO("writeback test failed\n");
 817         }
 818         if (radeon_no_wb == 1) {
 819                 dev_priv->writeback_works = 0;
 820                 DRM_INFO("writeback forced off\n");
 821         }
 822
 823         if (!dev_priv->writeback_works) {
 824                 /* Disable writeback to avoid unnecessary bus master transfer */
 825                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 826                              RADEON_RB_NO_UPDATE);
 827                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 828         }
 829 }
 830
 831 /* Enable or disable IGP GART on the chip */
 832 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 833 {
 834         u32 temp;
 835
 836         if (on) {
 837                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 838                           dev_priv->gart_vm_start,
 839                           (long)dev_priv->gart_info.bus_addr,
 840                           dev_priv->gart_size);
 841
 842                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 843                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 844                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 845                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 846                                                              RS690_BLOCK_GFX_D3_EN));
 847                 else
 848                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 849
 850                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 851                                                                RS480_VA_SIZE_32MB));
 852
 853                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 854                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 855                                                         RS480_TLB_ENABLE |
 856                                                         RS480_GTW_LAC_EN |
 857                                                         RS480_1LEVEL_GART));
 858
 859                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 860                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 861                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 862
 863                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 864                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 865                                                       RS480_REQ_TYPE_SNOOP_DIS));
 866
 867                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 868
 869                 dev_priv->gart_size = 32*1024*1024;
 870                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 871                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 872
 873                 radeon_write_agp_location(dev_priv, temp);
 874
 875                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 876                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 877                                                                RS480_VA_SIZE_32MB));
 878
 879                 do {
 880                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 881                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 882                                 break;
 883                         DRM_UDELAY(1);
 884                 } while (1);
 885
 886                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 887                                 RS480_GART_CACHE_INVALIDATE);
 888
 889                 do {
 890                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 891                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 892                                 break;
 893                         DRM_UDELAY(1);
 894                 } while (1);
 895
 896                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 897         } else {
 898                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 899         }
 900 }
 901
 902 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 903 {
 904         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 905         if (on) {
 906
 907                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 908                           dev_priv->gart_vm_start,
 909                           (long)dev_priv->gart_info.bus_addr,
 910                           dev_priv->gart_size);
 911                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 912                                   dev_priv->gart_vm_start);
 913                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 914                                   dev_priv->gart_info.bus_addr);
 915                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 916                                   dev_priv->gart_vm_start);
 917                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 918                                   dev_priv->gart_vm_start +
 919                                   dev_priv->gart_size - 1);
 920
 921                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 922
 923                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 924                                   RADEON_PCIE_TX_GART_EN);
 925         } else {
 926                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 927                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 928         }
 929 }
 930
 931 /* Enable or disable PCI GART on the chip */
 932 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 933 {
 934         u32 tmp;
 935
 936         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 937             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 938             (dev_priv->flags & RADEON_IS_IGPGART)) {
 939                 radeon_set_igpgart(dev_priv, on);
 940                 return;
 941         }
 942
 943         if (dev_priv->flags & RADEON_IS_PCIE) {
 944                 radeon_set_pciegart(dev_priv, on);
 945                 return;
 946         }
 947
 948         tmp = RADEON_READ(RADEON_AIC_CNTL);
 949
 950         if (on) {
 951                 RADEON_WRITE(RADEON_AIC_CNTL,
 952                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 953
 954                 /* set PCI GART page-table base address
 955                  */
 956                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 957
 958                 /* set address range for PCI address translate
 959                  */
 960                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 961                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 962                              + dev_priv->gart_size - 1);
 963
 964                 /* Turn off AGP aperture -- is this required for PCI GART?
 965                  */
 966                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 967                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 968         } else {
 969                 RADEON_WRITE(RADEON_AIC_CNTL,
 970                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 971         }
 972 }
 973
 974 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
 975 {
 976         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 977         struct radeon_virt_surface *vp;
 978         int i;
 979
 980         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
 981                 if (!dev_priv->virt_surfaces[i].file_priv ||
 982                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
 983                         break;
 984         }
 985         if (i >= 2 * RADEON_MAX_SURFACES)
 986                 return -ENOMEM;
 987         vp = &dev_priv->virt_surfaces[i];
 988
 989         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
 990                 struct radeon_surface *sp = &dev_priv->surfaces[i];
 991                 if (sp->refcount)
 992                         continue;
 993
 994                 vp->surface_index = i;
 995                 vp->lower = gart_info->bus_addr;
 996                 vp->upper = vp->lower + gart_info->table_size;
 997                 vp->flags = 0;
 998                 vp->file_priv = PCIGART_FILE_PRIV;
 999
1000                 sp->refcount = 1;
1001                 sp->lower = vp->lower;
1002                 sp->upper = vp->upper;
1003                 sp->flags = 0;
1004
1005                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1006                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1007                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1008                 return 0;
1009         }
1010
1011         return -ENOMEM;
1012 }
1013
1014 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1015                              struct drm_file *file_priv)
1016 {
1017         drm_radeon_private_t *dev_priv = dev->dev_private;
1018         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1019
1020         DRM_DEBUG("\n");
1021
1022         /* if we require new memory map but we don't have it fail */
1023         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1024                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1025                 radeon_do_cleanup_cp(dev);
1026                 return -EINVAL;
1027         }
1028
1029         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1030                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1031                 dev_priv->flags &= ~RADEON_IS_AGP;
1032         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1033                    && !init->is_pci) {
1034                 DRM_DEBUG("Restoring AGP flag\n");
1035                 dev_priv->flags |= RADEON_IS_AGP;
1036         }
1037
1038         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1039                 DRM_ERROR("PCI GART memory not allocated!\n");
1040                 radeon_do_cleanup_cp(dev);
1041                 return -EINVAL;
1042         }
1043
1044         dev_priv->usec_timeout = init->usec_timeout;
1045         if (dev_priv->usec_timeout < 1 ||
1046             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1047                 DRM_DEBUG("TIMEOUT problem!\n");
1048                 radeon_do_cleanup_cp(dev);
1049                 return -EINVAL;
1050         }
1051
1052         /* Enable vblank on CRTC1 for older X servers
1053          */
1054         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1055
1056         switch(init->func) {
1057         case RADEON_INIT_R200_CP:
1058                 dev_priv->microcode_version = UCODE_R200;
1059                 break;
1060         case RADEON_INIT_R300_CP:
1061                 dev_priv->microcode_version = UCODE_R300;
1062                 break;
1063         default:
1064                 dev_priv->microcode_version = UCODE_R100;
1065         }
1066
1067         dev_priv->do_boxes = 0;
1068         dev_priv->cp_mode = init->cp_mode;
1069
1070         /* We don't support anything other than bus-mastering ring mode,
1071          * but the ring can be in either AGP or PCI space for the ring
1072          * read pointer.
1073          */
1074         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1075             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1076                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1077                 radeon_do_cleanup_cp(dev);
1078                 return -EINVAL;
1079         }
1080
1081         switch (init->fb_bpp) {
1082         case 16:
1083                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1084                 break;
1085         case 32:
1086         default:
1087                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1088                 break;
1089         }
1090         dev_priv->front_offset = init->front_offset;
1091         dev_priv->front_pitch = init->front_pitch;
1092         dev_priv->back_offset = init->back_offset;
1093         dev_priv->back_pitch = init->back_pitch;
1094
1095         switch (init->depth_bpp) {
1096         case 16:
1097                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1098                 break;
1099         case 32:
1100         default:
1101                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1102                 break;
1103         }
1104         dev_priv->depth_offset = init->depth_offset;
1105         dev_priv->depth_pitch = init->depth_pitch;
1106
1107         /* Hardware state for depth clears.  Remove this if/when we no
1108          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1109          * all values to prevent unwanted 3D state from slipping through
1110          * and screwing with the clear operation.
1111          */
1112         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1113                                            (dev_priv->color_fmt << 10) |
1114                                            (dev_priv->microcode_version ==
1115                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1116
1117         dev_priv->depth_clear.rb3d_zstencilcntl =
1118             (dev_priv->depth_fmt |
1119              RADEON_Z_TEST_ALWAYS |
1120              RADEON_STENCIL_TEST_ALWAYS |
1121              RADEON_STENCIL_S_FAIL_REPLACE |
1122              RADEON_STENCIL_ZPASS_REPLACE |
1123              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1124
1125         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1126                                          RADEON_BFACE_SOLID |
1127                                          RADEON_FFACE_SOLID |
1128                                          RADEON_FLAT_SHADE_VTX_LAST |
1129                                          RADEON_DIFFUSE_SHADE_FLAT |
1130                                          RADEON_ALPHA_SHADE_FLAT |
1131                                          RADEON_SPECULAR_SHADE_FLAT |
1132                                          RADEON_FOG_SHADE_FLAT |
1133                                          RADEON_VTX_PIX_CENTER_OGL |
1134                                          RADEON_ROUND_MODE_TRUNC |
1135                                          RADEON_ROUND_PREC_8TH_PIX);
1136
1137
1138         dev_priv->ring_offset = init->ring_offset;
1139         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1140         dev_priv->buffers_offset = init->buffers_offset;
1141         dev_priv->gart_textures_offset = init->gart_textures_offset;
1142
1143         master_priv->sarea = drm_getsarea(dev);
1144         if (!master_priv->sarea) {
1145                 DRM_ERROR("could not find sarea!\n");
1146                 radeon_do_cleanup_cp(dev);
1147                 return -EINVAL;
1148         }
1149
1150         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1151         if (!dev_priv->cp_ring) {
1152                 DRM_ERROR("could not find cp ring region!\n");
1153                 radeon_do_cleanup_cp(dev);
1154                 return -EINVAL;
1155         }
1156         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1157         if (!dev_priv->ring_rptr) {
1158                 DRM_ERROR("could not find ring read pointer!\n");
1159                 radeon_do_cleanup_cp(dev);
1160                 return -EINVAL;
1161         }
1162         dev->agp_buffer_token = init->buffers_offset;
1163         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1164         if (!dev->agp_buffer_map) {
1165                 DRM_ERROR("could not find dma buffer region!\n");
1166                 radeon_do_cleanup_cp(dev);
1167                 return -EINVAL;
1168         }
1169
1170         if (init->gart_textures_offset) {
1171                 dev_priv->gart_textures =
1172                     drm_core_findmap(dev, init->gart_textures_offset);
1173                 if (!dev_priv->gart_textures) {
1174                         DRM_ERROR("could not find GART texture region!\n");
1175                         radeon_do_cleanup_cp(dev);
1176                         return -EINVAL;
1177                 }
1178         }
1179
1180 #if __OS_HAS_AGP
1181         if (dev_priv->flags & RADEON_IS_AGP) {
1182                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1183                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1184                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1185                 if (!dev_priv->cp_ring->handle ||
1186                     !dev_priv->ring_rptr->handle ||
1187                     !dev->agp_buffer_map->handle) {
1188                         DRM_ERROR("could not find ioremap agp regions!\n");
1189                         radeon_do_cleanup_cp(dev);
1190                         return -EINVAL;
1191                 }
1192         } else
1193 #endif
1194         {
1195                 dev_priv->cp_ring->handle =
1196                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1197                 dev_priv->ring_rptr->handle =
1198                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1199                 dev->agp_buffer_map->handle =
1200                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1201
1202                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1203                           dev_priv->cp_ring->handle);
1204                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1205                           dev_priv->ring_rptr->handle);
1206                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1207                           dev->agp_buffer_map->handle);
1208         }
1209
1210         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1211         dev_priv->fb_size =
1212                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1213                 - dev_priv->fb_location;
1214
1215         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1216                                         ((dev_priv->front_offset
1217                                           + dev_priv->fb_location) >> 10));
1218
1219         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1220                                        ((dev_priv->back_offset
1221                                          + dev_priv->fb_location) >> 10));
1222
1223         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1224                                         ((dev_priv->depth_offset
1225                                           + dev_priv->fb_location) >> 10));
1226
1227         dev_priv->gart_size = init->gart_size;
1228
1229         /* New let's set the memory map ... */
1230         if (dev_priv->new_memmap) {
1231                 u32 base = 0;
1232
1233                 DRM_INFO("Setting GART location based on new memory map\n");
1234
1235                 /* If using AGP, try to locate the AGP aperture at the same
1236                  * location in the card and on the bus, though we have to
1237                  * align it down.
1238                  */
1239 #if __OS_HAS_AGP
1240                 if (dev_priv->flags & RADEON_IS_AGP) {
1241                         base = dev->agp->base;
1242                         /* Check if valid */
1243                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1244                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1245                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1246                                          dev->agp->base);
1247                                 base = 0;
1248                         }
1249                 }
1250 #endif
1251                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1252                 if (base == 0) {
1253                         base = dev_priv->fb_location + dev_priv->fb_size;
1254                         if (base < dev_priv->fb_location ||
1255                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1256                                 base = dev_priv->fb_location
1257                                         - dev_priv->gart_size;
1258                 }
1259                 dev_priv->gart_vm_start = base & 0xffc00000u;
1260                 if (dev_priv->gart_vm_start != base)
1261                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1262                                  base, dev_priv->gart_vm_start);
1263         } else {
1264                 DRM_INFO("Setting GART location based on old memory map\n");
1265                 dev_priv->gart_vm_start = dev_priv->fb_location +
1266                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1267         }
1268
1269 #if __OS_HAS_AGP
1270         if (dev_priv->flags & RADEON_IS_AGP)
1271                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1272                                                  - dev->agp->base
1273                                                  + dev_priv->gart_vm_start);
1274         else
1275 #endif
1276                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1277                                         - (unsigned long)dev->sg->virtual
1278                                         + dev_priv->gart_vm_start);
1279
1280         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1281         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1282         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1283                   dev_priv->gart_buffers_offset);
1284
1285         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1286         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1287                               + init->ring_size / sizeof(u32));
1288         dev_priv->ring.size = init->ring_size;
1289         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1290
1291         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1292         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1293
1294         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1295         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1296         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1297
1298         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1299
1300 #if __OS_HAS_AGP
1301         if (dev_priv->flags & RADEON_IS_AGP) {
1302                 /* Turn off PCI GART */
1303                 radeon_set_pcigart(dev_priv, 0);
1304         } else
1305 #endif
1306         {
1307                 u32 sctrl;
1308                 int ret;
1309
1310                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1311                 /* if we have an offset set from userspace */
1312                 if (dev_priv->pcigart_offset_set) {
1313                         dev_priv->gart_info.bus_addr =
1314                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1315                         dev_priv->gart_info.mapping.offset =
1316                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1317                         dev_priv->gart_info.mapping.size =
1318                             dev_priv->gart_info.table_size;
1319
1320                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1321                         dev_priv->gart_info.addr =
1322                             dev_priv->gart_info.mapping.handle;
1323
1324                         if (dev_priv->flags & RADEON_IS_PCIE)
1325                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1326                         else
1327                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1328                         dev_priv->gart_info.gart_table_location =
1329                             DRM_ATI_GART_FB;
1330
1331                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1332                                   dev_priv->gart_info.addr,
1333                                   dev_priv->pcigart_offset);
1334                 } else {
1335                         if (dev_priv->flags & RADEON_IS_IGPGART)
1336                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1337                         else
1338                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1339                         dev_priv->gart_info.gart_table_location =
1340                             DRM_ATI_GART_MAIN;
1341                         dev_priv->gart_info.addr = NULL;
1342                         dev_priv->gart_info.bus_addr = 0;
1343                         if (dev_priv->flags & RADEON_IS_PCIE) {
1344                                 DRM_ERROR
1345                                     ("Cannot use PCI Express without GART in FB memory\n");
1346                                 radeon_do_cleanup_cp(dev);
1347                                 return -EINVAL;
1348                         }
1349                 }
1350
1351                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1352                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1353                 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1354                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1355
1356                 if (!ret) {
1357                         DRM_ERROR("failed to init PCI GART!\n");
1358                         radeon_do_cleanup_cp(dev);
1359                         return -ENOMEM;
1360                 }
1361
1362                 ret = radeon_setup_pcigart_surface(dev_priv);
1363                 if (ret) {
1364                         DRM_ERROR("failed to setup GART surface!\n");
1365                         drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1366                         radeon_do_cleanup_cp(dev);
1367                         return ret;
1368                 }
1369
1370                 /* Turn on PCI GART */
1371                 radeon_set_pcigart(dev_priv, 1);
1372         }
1373
1374         radeon_cp_load_microcode(dev_priv);
1375         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1376
1377         dev_priv->last_buf = 0;
1378
1379         radeon_do_engine_reset(dev);
1380         radeon_test_writeback(dev_priv);
1381
1382         return 0;
1383 }
1384
1385 static int radeon_do_cleanup_cp(struct drm_device * dev)
1386 {
1387         drm_radeon_private_t *dev_priv = dev->dev_private;
1388         DRM_DEBUG("\n");
1389
1390         /* Make sure interrupts are disabled here because the uninstall ioctl
1391          * may not have been called from userspace and after dev_private
1392          * is freed, it's too late.
1393          */
1394         if (dev->irq_enabled)
1395                 drm_irq_uninstall(dev);
1396
1397 #if __OS_HAS_AGP
1398         if (dev_priv->flags & RADEON_IS_AGP) {
1399                 if (dev_priv->cp_ring != NULL) {
1400                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1401                         dev_priv->cp_ring = NULL;
1402                 }
1403                 if (dev_priv->ring_rptr != NULL) {
1404                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1405                         dev_priv->ring_rptr = NULL;
1406                 }
1407                 if (dev->agp_buffer_map != NULL) {
1408                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1409                         dev->agp_buffer_map = NULL;
1410                 }
1411         } else
1412 #endif
1413         {
1414
1415                 if (dev_priv->gart_info.bus_addr) {
1416                         /* Turn off PCI GART */
1417                         radeon_set_pcigart(dev_priv, 0);
1418                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1419                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1420                 }
1421
1422                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1423                 {
1424                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1425                         dev_priv->gart_info.addr = 0;
1426                 }
1427         }
1428         /* only clear to the start of flags */
1429         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1430
1431         return 0;
1432 }
1433
1434 /* This code will reinit the Radeon CP hardware after a resume from disc.
1435  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1436  * here we make sure that all Radeon hardware initialisation is re-done without
1437  * affecting running applications.
1438  *
1439  * Charl P. Botha <http://cpbotha.net>
1440  */
1441 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1442 {
1443         drm_radeon_private_t *dev_priv = dev->dev_private;
1444
1445         if (!dev_priv) {
1446                 DRM_ERROR("Called with no initialization\n");
1447                 return -EINVAL;
1448         }
1449
1450         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1451
1452 #if __OS_HAS_AGP
1453         if (dev_priv->flags & RADEON_IS_AGP) {
1454                 /* Turn off PCI GART */
1455                 radeon_set_pcigart(dev_priv, 0);
1456         } else
1457 #endif
1458         {
1459                 /* Turn on PCI GART */
1460                 radeon_set_pcigart(dev_priv, 1);
1461         }
1462
1463         radeon_cp_load_microcode(dev_priv);
1464         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1465
1466         radeon_do_engine_reset(dev);
1467         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1468
1469         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1470
1471         return 0;
1472 }
1473
1474 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1475 {
1476         drm_radeon_private_t *dev_priv = dev->dev_private;
1477         drm_radeon_init_t *init = data;
1478
1479         LOCK_TEST_WITH_RETURN(dev, file_priv);
1480
1481         if (init->func == RADEON_INIT_R300_CP)
1482                 r300_init_reg_flags(dev);
1483
1484         switch (init->func) {
1485         case RADEON_INIT_CP:
1486         case RADEON_INIT_R200_CP:
1487         case RADEON_INIT_R300_CP:
1488                 return radeon_do_init_cp(dev, init, file_priv);
1489         case RADEON_INIT_R600_CP:
1490                 return r600_do_init_cp(dev, init, file_priv);
1491         case RADEON_CLEANUP_CP:
1492                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1493                         return r600_do_cleanup_cp(dev);
1494                 else
1495                         return radeon_do_cleanup_cp(dev);
1496         }
1497
1498         return -EINVAL;
1499 }
1500
1501 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1502 {
1503         drm_radeon_private_t *dev_priv = dev->dev_private;
1504         DRM_DEBUG("\n");
1505
1506         LOCK_TEST_WITH_RETURN(dev, file_priv);
1507
1508         if (dev_priv->cp_running) {
1509                 DRM_DEBUG("while CP running\n");
1510                 return 0;
1511         }
1512         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1513                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1514                           dev_priv->cp_mode);
1515                 return 0;
1516         }
1517
1518         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1519                 r600_do_cp_start(dev_priv);
1520         else
1521                 radeon_do_cp_start(dev_priv);
1522
1523         return 0;
1524 }
1525
1526 /* Stop the CP.  The engine must have been idled before calling this
1527  * routine.
1528  */
1529 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1530 {
1531         drm_radeon_private_t *dev_priv = dev->dev_private;
1532         drm_radeon_cp_stop_t *stop = data;
1533         int ret;
1534         DRM_DEBUG("\n");
1535
1536         LOCK_TEST_WITH_RETURN(dev, file_priv);
1537
1538         if (!dev_priv->cp_running)
1539                 return 0;
1540
1541         /* Flush any pending CP commands.  This ensures any outstanding
1542          * commands are exectuted by the engine before we turn it off.
1543          */
1544         if (stop->flush) {
1545                 radeon_do_cp_flush(dev_priv);
1546         }
1547
1548         /* If we fail to make the engine go idle, we return an error
1549          * code so that the DRM ioctl wrapper can try again.
1550          */
1551         if (stop->idle) {
1552                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1553                         ret = r600_do_cp_idle(dev_priv);
1554                 else
1555                         ret = radeon_do_cp_idle(dev_priv);
1556                 if (ret)
1557                         return ret;
1558         }
1559
1560         /* Finally, we can turn off the CP.  If the engine isn't idle,
1561          * we will get some dropped triangles as they won't be fully
1562          * rendered before the CP is shut down.
1563          */
1564         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1565                 r600_do_cp_stop(dev_priv);
1566         else
1567                 radeon_do_cp_stop(dev_priv);
1568
1569         /* Reset the engine */
1570         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1571                 r600_do_engine_reset(dev);
1572         else
1573                 radeon_do_engine_reset(dev);
1574
1575         return 0;
1576 }
1577
1578 void radeon_do_release(struct drm_device * dev)
1579 {
1580         drm_radeon_private_t *dev_priv = dev->dev_private;
1581         int i, ret;
1582
1583         if (dev_priv) {
1584                 if (dev_priv->cp_running) {
1585                         /* Stop the cp */
1586                         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1587                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1588                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1589 #ifdef __linux__
1590                                         schedule();
1591 #else
1592                                         tsleep(&ret, PZERO, "rdnrel", 1);
1593 #endif
1594                                 }
1595                         } else {
1596                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1597                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1598 #ifdef __linux__
1599                                         schedule();
1600 #else
1601                                         tsleep(&ret, PZERO, "rdnrel", 1);
1602 #endif
1603                                 }
1604                         }
1605                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1606                                 r600_do_cp_stop(dev_priv);
1607                                 r600_do_engine_reset(dev);
1608                         } else {
1609                                 radeon_do_cp_stop(dev_priv);
1610                                 radeon_do_engine_reset(dev);
1611                         }
1612                 }
1613
1614                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1615                         /* Disable *all* interrupts */
1616                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1617                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1618
1619                         if (dev_priv->mmio) {   /* remove all surfaces */
1620                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1621                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1622                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1623                                                      16 * i, 0);
1624                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1625                                                      16 * i, 0);
1626                                 }
1627                         }
1628                 }
1629
1630                 /* Free memory heap structures */
1631                 radeon_mem_takedown(&(dev_priv->gart_heap));
1632                 radeon_mem_takedown(&(dev_priv->fb_heap));
1633
1634                 /* deallocate kernel resources */
1635                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1636                         r600_do_cleanup_cp(dev);
1637                 else
1638                         radeon_do_cleanup_cp(dev);
1639         }
1640 }
1641
1642 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1643  */
1644 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1645 {
1646         drm_radeon_private_t *dev_priv = dev->dev_private;
1647         DRM_DEBUG("\n");
1648
1649         LOCK_TEST_WITH_RETURN(dev, file_priv);
1650
1651         if (!dev_priv) {
1652                 DRM_DEBUG("called before init done\n");
1653                 return -EINVAL;
1654         }
1655
1656         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1657                 r600_do_cp_reset(dev_priv);
1658         else
1659                 radeon_do_cp_reset(dev_priv);
1660
1661         /* The CP is no longer running after an engine reset */
1662         dev_priv->cp_running = 0;
1663
1664         return 0;
1665 }
1666
1667 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1668 {
1669         drm_radeon_private_t *dev_priv = dev->dev_private;
1670         DRM_DEBUG("\n");
1671
1672         LOCK_TEST_WITH_RETURN(dev, file_priv);
1673
1674         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1675                 return r600_do_cp_idle(dev_priv);
1676         else
1677                 return radeon_do_cp_idle(dev_priv);
1678 }
1679
1680 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1681  */
1682 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1683 {
1684         drm_radeon_private_t *dev_priv = dev->dev_private;
1685         DRM_DEBUG("\n");
1686
1687         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1688                 return r600_do_resume_cp(dev, file_priv);
1689         else
1690                 return radeon_do_resume_cp(dev, file_priv);
1691 }
1692
1693 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1694 {
1695         drm_radeon_private_t *dev_priv = dev->dev_private;
1696         DRM_DEBUG("\n");
1697
1698         LOCK_TEST_WITH_RETURN(dev, file_priv);
1699
1700         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1701                 return r600_do_engine_reset(dev);
1702         else
1703                 return radeon_do_engine_reset(dev);
1704 }
1705
1706 /* ================================================================
1707  * Fullscreen mode
1708  */
1709
1710 /* KW: Deprecated to say the least:
1711  */
1712 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1713 {
1714         return 0;
1715 }
1716
1717 /* ================================================================
1718  * Freelist management
1719  */
1720
1721 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1722  *   bufs until freelist code is used.  Note this hides a problem with
1723  *   the scratch register * (used to keep track of last buffer
1724  *   completed) being written to before * the last buffer has actually
1725  *   completed rendering.
1726  *
1727  * KW:  It's also a good way to find free buffers quickly.
1728  *
1729  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1730  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1731  * we essentially have to do this, else old clients will break.
1732  *
1733  * However, it does leave open a potential deadlock where all the
1734  * buffers are held by other clients, which can't release them because
1735  * they can't get the lock.
1736  */
1737
1738 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1739 {
1740         struct drm_device_dma *dma = dev->dma;
1741         drm_radeon_private_t *dev_priv = dev->dev_private;
1742         drm_radeon_buf_priv_t *buf_priv;
1743         struct drm_buf *buf;
1744         int i, t;
1745         int start;
1746
1747         if (++dev_priv->last_buf >= dma->buf_count)
1748                 dev_priv->last_buf = 0;
1749
1750         start = dev_priv->last_buf;
1751
1752         for (t = 0; t < dev_priv->usec_timeout; t++) {
1753                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1754                 DRM_DEBUG("done_age = %d\n", done_age);
1755                 for (i = start; i < dma->buf_count; i++) {
1756                         buf = dma->buflist[i];
1757                         buf_priv = buf->dev_private;
1758                         if (buf->file_priv == NULL || (buf->pending &&
1759                                                        buf_priv->age <=
1760                                                        done_age)) {
1761                                 dev_priv->stats.requested_bufs++;
1762                                 buf->pending = 0;
1763                                 return buf;
1764                         }
1765                         start = 0;
1766                 }
1767
1768                 if (t) {
1769                         DRM_UDELAY(1);
1770                         dev_priv->stats.freelist_loops++;
1771                 }
1772         }
1773
1774         DRM_DEBUG("returning NULL!\n");
1775         return NULL;
1776 }
1777
1778 #if 0
1779 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1780 {
1781         struct drm_device_dma *dma = dev->dma;
1782         drm_radeon_private_t *dev_priv = dev->dev_private;
1783         drm_radeon_buf_priv_t *buf_priv;
1784         struct drm_buf *buf;
1785         int i, t;
1786         int start;
1787         u32 done_age;
1788
1789         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1790         if (++dev_priv->last_buf >= dma->buf_count)
1791                 dev_priv->last_buf = 0;
1792
1793         start = dev_priv->last_buf;
1794         dev_priv->stats.freelist_loops++;
1795
1796         for (t = 0; t < 2; t++) {
1797                 for (i = start; i < dma->buf_count; i++) {
1798                         buf = dma->buflist[i];
1799                         buf_priv = buf->dev_private;
1800                         if (buf->file_priv == 0 || (buf->pending &&
1801                                                     buf_priv->age <=
1802                                                     done_age)) {
1803                                 dev_priv->stats.requested_bufs++;
1804                                 buf->pending = 0;
1805                                 return buf;
1806                         }
1807                 }
1808                 start = 0;
1809         }
1810
1811         return NULL;
1812 }
1813 #endif
1814
1815 void radeon_freelist_reset(struct drm_device * dev)
1816 {
1817         struct drm_device_dma *dma = dev->dma;
1818         drm_radeon_private_t *dev_priv = dev->dev_private;
1819         int i;
1820
1821         dev_priv->last_buf = 0;
1822         for (i = 0; i < dma->buf_count; i++) {
1823                 struct drm_buf *buf = dma->buflist[i];
1824                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1825                 buf_priv->age = 0;
1826         }
1827 }
1828
1829 /* ================================================================
1830  * CP command submission
1831  */
1832
1833 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1834 {
1835         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1836         int i;
1837         u32 last_head = GET_RING_HEAD(dev_priv);
1838
1839         for (i = 0; i < dev_priv->usec_timeout; i++) {
1840                 u32 head = GET_RING_HEAD(dev_priv);
1841
1842                 ring->space = (head - ring->tail) * sizeof(u32);
1843                 if (ring->space <= 0)
1844                         ring->space += ring->size;
1845                 if (ring->space > n)
1846                         return 0;
1847
1848                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1849
1850                 if (head != last_head)
1851                         i = 0;
1852                 last_head = head;
1853
1854                 DRM_UDELAY(1);
1855         }
1856
1857         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1858 #if RADEON_FIFO_DEBUG
1859         radeon_status(dev_priv);
1860         DRM_ERROR("failed!\n");
1861 #endif
1862         return -EBUSY;
1863 }
1864
1865 static int radeon_cp_get_buffers(struct drm_device *dev,
1866                                  struct drm_file *file_priv,
1867                                  struct drm_dma * d)
1868 {
1869         int i;
1870         struct drm_buf *buf;
1871
1872         for (i = d->granted_count; i < d->request_count; i++) {
1873                 buf = radeon_freelist_get(dev);
1874                 if (!buf)
1875                         return -EBUSY;  /* NOTE: broken client */
1876
1877                 buf->file_priv = file_priv;
1878
1879                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1880                                      sizeof(buf->idx)))
1881                         return -EFAULT;
1882                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1883                                      sizeof(buf->total)))
1884                         return -EFAULT;
1885
1886                 d->granted_count++;
1887         }
1888         return 0;
1889 }
1890
1891 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1892 {
1893         struct drm_device_dma *dma = dev->dma;
1894         int ret = 0;
1895         struct drm_dma *d = data;
1896
1897         LOCK_TEST_WITH_RETURN(dev, file_priv);
1898
1899         /* Please don't send us buffers.
1900          */
1901         if (d->send_count != 0) {
1902                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1903                           DRM_CURRENTPID, d->send_count);
1904                 return -EINVAL;
1905         }
1906
1907         /* We'll send you buffers.
1908          */
1909         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1910                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1911                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1912                 return -EINVAL;
1913         }
1914
1915         d->granted_count = 0;
1916
1917         if (d->request_count) {
1918                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1919         }
1920
1921         return ret;
1922 }
1923
1924 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1925 {
1926         drm_radeon_private_t *dev_priv;
1927         int ret = 0;
1928
1929         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1930         if (dev_priv == NULL)
1931                 return -ENOMEM;
1932
1933         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1934         dev->dev_private = (void *)dev_priv;
1935         dev_priv->flags = flags;
1936
1937         switch (flags & RADEON_FAMILY_MASK) {
1938         case CHIP_R100:
1939         case CHIP_RV200:
1940         case CHIP_R200:
1941         case CHIP_R300:
1942         case CHIP_R350:
1943         case CHIP_R420:
1944         case CHIP_R423:
1945         case CHIP_RV410:
1946         case CHIP_RV515:
1947         case CHIP_R520:
1948         case CHIP_RV570:
1949         case CHIP_R580:
1950                 dev_priv->flags |= RADEON_HAS_HIERZ;
1951                 break;
1952         default:
1953                 /* all other chips have no hierarchical z buffer */
1954                 break;
1955         }
1956
1957         if (drm_device_is_agp(dev))
1958                 dev_priv->flags |= RADEON_IS_AGP;
1959         else if (drm_device_is_pcie(dev))
1960                 dev_priv->flags |= RADEON_IS_PCIE;
1961         else
1962                 dev_priv->flags |= RADEON_IS_PCI;
1963
1964         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1965                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1966                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1967         if (ret != 0)
1968                 return ret;
1969
1970         ret = drm_vblank_init(dev, 2);
1971         if (ret) {
1972                 radeon_driver_unload(dev);
1973                 return ret;
1974         }
1975
1976         DRM_DEBUG("%s card detected\n",
1977                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1978         return ret;
1979 }
1980
1981 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1982 {
1983         struct drm_radeon_master_private *master_priv;
1984         unsigned long sareapage;
1985         int ret;
1986
1987         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1988         if (!master_priv)
1989                 return -ENOMEM;
1990
1991         /* prebuild the SAREA */
1992         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1993         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1994                          &master_priv->sarea);
1995         if (ret) {
1996                 DRM_ERROR("SAREA setup failed\n");
1997                 return ret;
1998         }
1999         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2000         master_priv->sarea_priv->pfCurrentPage = 0;
2001
2002         master->driver_priv = master_priv;
2003         return 0;
2004 }
2005
2006 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2007 {
2008         struct drm_radeon_master_private *master_priv = master->driver_priv;
2009
2010         if (!master_priv)
2011                 return;
2012
2013         if (master_priv->sarea_priv &&
2014             master_priv->sarea_priv->pfCurrentPage != 0)
2015                 radeon_cp_dispatch_flip(dev, master);
2016
2017         master_priv->sarea_priv = NULL;
2018         if (master_priv->sarea)
2019                 drm_rmmap_locked(dev, master_priv->sarea);
2020
2021         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
2022
2023         master->driver_priv = NULL;
2024 }
2025
2026 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2027  * have to find them.
2028  */
2029 int radeon_driver_firstopen(struct drm_device *dev)
2030 {
2031         int ret;
2032         drm_local_map_t *map;
2033         drm_radeon_private_t *dev_priv = dev->dev_private;
2034
2035         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2036
2037         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2038         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2039                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2040                          _DRM_WRITE_COMBINING, &map);
2041         if (ret != 0)
2042                 return ret;
2043
2044         return 0;
2045 }
2046
2047 int radeon_driver_unload(struct drm_device *dev)
2048 {
2049         drm_radeon_private_t *dev_priv = dev->dev_private;
2050
2051         DRM_DEBUG("\n");
2052
2053         drm_rmmap(dev, dev_priv->mmio);
2054
2055         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2056
2057         dev->dev_private = NULL;
2058         return 0;
2059 }
2060
2061 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2062 {
2063         int i;
2064         u32 *ring;
2065         int tail_aligned;
2066
2067         /* check if the ring is padded out to 16-dword alignment */
2068
2069         tail_aligned = dev_priv->ring.tail & 0xf;
2070         if (tail_aligned) {
2071                 int num_p2 = 16 - tail_aligned;
2072
2073                 ring = dev_priv->ring.start;
2074                 /* pad with some CP_PACKET2 */
2075                 for (i = 0; i < num_p2; i++)
2076                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2077
2078                 dev_priv->ring.tail += i;
2079
2080                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2081         }
2082
2083         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2084
2085         DRM_MEMORYBARRIER();
2086         GET_RING_HEAD( dev_priv );
2087
2088         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2089                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2090                 /* read from PCI bus to ensure correct posting */
2091                 RADEON_READ(R600_CP_RB_RPTR);
2092         } else {
2093                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2094                 /* read from PCI bus to ensure correct posting */
2095                 RADEON_READ(RADEON_CP_RB_RPTR);
2096         }
2097 }