SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                         break;
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 125                                                         u8 id)
 126 {
 127         struct atom_context *ctx = rdev->mode_info.atom_context;
 128         struct radeon_gpio_rec gpio;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 130         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 131         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 132         u16 data_offset, size;
 133         int i, num_indices;
 134
 135         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 136         gpio.valid = false;
 137
 138         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 139
 140         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 141
 142         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 143
 144         for (i = 0; i < num_indices; i++) {
 145                 pin = &gpio_info->asGPIO_Pin[i];
 146                 if (id == pin->ucGPIO_ID) {
 147                         gpio.id = pin->ucGPIO_ID;
 148                         gpio.reg = pin->usGpioPin_AIndex * 4;
 149                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 150                         gpio.valid = true;
 151                         break;
 152                 }
 153         }
 154
 155         return gpio;
 156 }
 157
 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 159                                                             struct radeon_gpio_rec *gpio)
 160 {
 161         struct radeon_hpd hpd;
 162         u32 reg;
 163
 164         if (ASIC_IS_DCE4(rdev))
 165                 reg = EVERGREEN_DC_GPIO_HPD_A;
 166         else
 167                 reg = AVIVO_DC_GPIO_HPD_A;
 168
 169         hpd.gpio = *gpio;
 170         if (gpio->reg == reg) {
 171                 switch(gpio->mask) {
 172                 case (1 << 0):
 173                         hpd.hpd = RADEON_HPD_1;
 174                         break;
 175                 case (1 << 8):
 176                         hpd.hpd = RADEON_HPD_2;
 177                         break;
 178                 case (1 << 16):
 179                         hpd.hpd = RADEON_HPD_3;
 180                         break;
 181                 case (1 << 24):
 182                         hpd.hpd = RADEON_HPD_4;
 183                         break;
 184                 case (1 << 26):
 185                         hpd.hpd = RADEON_HPD_5;
 186                         break;
 187                 case (1 << 28):
 188                         hpd.hpd = RADEON_HPD_6;
 189                         break;
 190                 default:
 191                         hpd.hpd = RADEON_HPD_NONE;
 192                         break;
 193                 }
 194         } else
 195                 hpd.hpd = RADEON_HPD_NONE;
 196         return hpd;
 197 }
 198
 199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 200                                      uint32_t supported_device,
 201                                      int *connector_type,
 202                                      struct radeon_i2c_bus_rec *i2c_bus,
 203                                      uint16_t *line_mux,
 204                                      struct radeon_hpd *hpd)
 205 {
 206
 207         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 208         if ((dev->pdev->device == 0x791e) &&
 209             (dev->pdev->subsystem_vendor == 0x1043) &&
 210             (dev->pdev->subsystem_device == 0x826d)) {
 211                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 212                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 213                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 214         }
 215
 216         /* Asrock RS600 board lists the DVI port as HDMI */
 217         if ((dev->pdev->device == 0x7941) &&
 218             (dev->pdev->subsystem_vendor == 0x1849) &&
 219             (dev->pdev->subsystem_device == 0x7941)) {
 220                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 221                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 222                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 223         }
 224
 225         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 226         if ((dev->pdev->device == 0x7941) &&
 227             (dev->pdev->subsystem_vendor == 0x147b) &&
 228             (dev->pdev->subsystem_device == 0x2412)) {
 229                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 230                         return false;
 231         }
 232
 233         /* Falcon NW laptop lists vga ddc line for LVDS */
 234         if ((dev->pdev->device == 0x5653) &&
 235             (dev->pdev->subsystem_vendor == 0x1462) &&
 236             (dev->pdev->subsystem_device == 0x0291)) {
 237                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 238                         i2c_bus->valid = false;
 239                         *line_mux = 53;
 240                 }
 241         }
 242
 243         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 244         if ((dev->pdev->device == 0x7146) &&
 245             (dev->pdev->subsystem_vendor == 0x17af) &&
 246             (dev->pdev->subsystem_device == 0x2058)) {
 247                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 248                         return false;
 249         }
 250
 251         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 252         if ((dev->pdev->device == 0x7142) &&
 253             (dev->pdev->subsystem_vendor == 0x1458) &&
 254             (dev->pdev->subsystem_device == 0x2134)) {
 255                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 256                         return false;
 257         }
 258
 259
 260         /* Funky macbooks */
 261         if ((dev->pdev->device == 0x71C5) &&
 262             (dev->pdev->subsystem_vendor == 0x106b) &&
 263             (dev->pdev->subsystem_device == 0x0080)) {
 264                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 265                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 266                         return false;
 267         }
 268
 269         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 270         if ((dev->pdev->device == 0x9598) &&
 271             (dev->pdev->subsystem_vendor == 0x1043) &&
 272             (dev->pdev->subsystem_device == 0x01da)) {
 273                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 274                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 275                 }
 276         }
 277
 278         /* ASUS HD 3450 board lists the DVI port as HDMI */
 279         if ((dev->pdev->device == 0x95C5) &&
 280             (dev->pdev->subsystem_vendor == 0x1043) &&
 281             (dev->pdev->subsystem_device == 0x01e2)) {
 282                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 283                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 284                 }
 285         }
 286
 287         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 288          * HDMI + VGA reporting as HDMI
 289          */
 290         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 291                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 292                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 293                         *line_mux = 0;
 294                 }
 295         }
 296
 297         /* Acer laptop reports DVI-D as DVI-I */
 298         if ((dev->pdev->device == 0x95c4) &&
 299             (dev->pdev->subsystem_vendor == 0x1025) &&
 300             (dev->pdev->subsystem_device == 0x013c)) {
 301                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 302                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 303                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 304         }
 305
 306         /* XFX Pine Group device rv730 reports no VGA DDC lines
 307          * even though they are wired up to record 0x93
 308          */
 309         if ((dev->pdev->device == 0x9498) &&
 310             (dev->pdev->subsystem_vendor == 0x1682) &&
 311             (dev->pdev->subsystem_device == 0x2452)) {
 312                 struct radeon_device *rdev = dev->dev_private;
 313                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 314         }
 315         return true;
 316 }
 317
 318 const int supported_devices_connector_convert[] = {
 319         DRM_MODE_CONNECTOR_Unknown,
 320         DRM_MODE_CONNECTOR_VGA,
 321         DRM_MODE_CONNECTOR_DVII,
 322         DRM_MODE_CONNECTOR_DVID,
 323         DRM_MODE_CONNECTOR_DVIA,
 324         DRM_MODE_CONNECTOR_SVIDEO,
 325         DRM_MODE_CONNECTOR_Composite,
 326         DRM_MODE_CONNECTOR_LVDS,
 327         DRM_MODE_CONNECTOR_Unknown,
 328         DRM_MODE_CONNECTOR_Unknown,
 329         DRM_MODE_CONNECTOR_HDMIA,
 330         DRM_MODE_CONNECTOR_HDMIB,
 331         DRM_MODE_CONNECTOR_Unknown,
 332         DRM_MODE_CONNECTOR_Unknown,
 333         DRM_MODE_CONNECTOR_9PinDIN,
 334         DRM_MODE_CONNECTOR_DisplayPort
 335 };
 336
 337 const uint16_t supported_devices_connector_object_id_convert[] = {
 338         CONNECTOR_OBJECT_ID_NONE,
 339         CONNECTOR_OBJECT_ID_VGA,
 340         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 341         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 342         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 343         CONNECTOR_OBJECT_ID_COMPOSITE,
 344         CONNECTOR_OBJECT_ID_SVIDEO,
 345         CONNECTOR_OBJECT_ID_LVDS,
 346         CONNECTOR_OBJECT_ID_9PIN_DIN,
 347         CONNECTOR_OBJECT_ID_9PIN_DIN,
 348         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 349         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 350         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 351         CONNECTOR_OBJECT_ID_SVIDEO
 352 };
 353
 354 const int object_connector_convert[] = {
 355         DRM_MODE_CONNECTOR_Unknown,
 356         DRM_MODE_CONNECTOR_DVII,
 357         DRM_MODE_CONNECTOR_DVII,
 358         DRM_MODE_CONNECTOR_DVID,
 359         DRM_MODE_CONNECTOR_DVID,
 360         DRM_MODE_CONNECTOR_VGA,
 361         DRM_MODE_CONNECTOR_Composite,
 362         DRM_MODE_CONNECTOR_SVIDEO,
 363         DRM_MODE_CONNECTOR_Unknown,
 364         DRM_MODE_CONNECTOR_Unknown,
 365         DRM_MODE_CONNECTOR_9PinDIN,
 366         DRM_MODE_CONNECTOR_Unknown,
 367         DRM_MODE_CONNECTOR_HDMIA,
 368         DRM_MODE_CONNECTOR_HDMIB,
 369         DRM_MODE_CONNECTOR_LVDS,
 370         DRM_MODE_CONNECTOR_9PinDIN,
 371         DRM_MODE_CONNECTOR_Unknown,
 372         DRM_MODE_CONNECTOR_Unknown,
 373         DRM_MODE_CONNECTOR_Unknown,
 374         DRM_MODE_CONNECTOR_DisplayPort,
 375         DRM_MODE_CONNECTOR_eDP,
 376         DRM_MODE_CONNECTOR_Unknown
 377 };
 378
 379 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 380 {
 381         struct radeon_device *rdev = dev->dev_private;
 382         struct radeon_mode_info *mode_info = &rdev->mode_info;
 383         struct atom_context *ctx = mode_info->atom_context;
 384         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 385         u16 size, data_offset;
 386         u8 frev, crev;
 387         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 388         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 389         ATOM_OBJECT_HEADER *obj_header;
 390         int i, j, path_size, device_support;
 391         int connector_type;
 392         u16 igp_lane_info, conn_id, connector_object_id;
 393         bool linkb;
 394         struct radeon_i2c_bus_rec ddc_bus;
 395         struct radeon_gpio_rec gpio;
 396         struct radeon_hpd hpd;
 397
 398         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 399
 400         if (data_offset == 0)
 401                 return false;
 402
 403         if (crev < 2)
 404                 return false;
 405
 406         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 407         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 408             (ctx->bios + data_offset +
 409              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 410         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 411             (ctx->bios + data_offset +
 412              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 413         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 414
 415         path_size = 0;
 416         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 417                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 418                 ATOM_DISPLAY_OBJECT_PATH *path;
 419                 addr += path_size;
 420                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 421                 path_size += le16_to_cpu(path->usSize);
 422                 linkb = false;
 423                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 424                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 425
 426                         con_obj_id =
 427                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 428                             >> OBJECT_ID_SHIFT;
 429                         con_obj_num =
 430                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 431                             >> ENUM_ID_SHIFT;
 432                         con_obj_type =
 433                             (le16_to_cpu(path->usConnObjectId) &
 434                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 435
 436                         /* TODO CV support */
 437                         if (le16_to_cpu(path->usDeviceTag) ==
 438                                 ATOM_DEVICE_CV_SUPPORT)
 439                                 continue;
 440
 441                         /* IGP chips */
 442                         if ((rdev->flags & RADEON_IS_IGP) &&
 443                             (con_obj_id ==
 444                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 445                                 uint16_t igp_offset = 0;
 446                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 447
 448                                 index =
 449                                     GetIndexIntoMasterTable(DATA,
 450                                                             IntegratedSystemInfo);
 451
 452                                 atom_parse_data_header(ctx, index, &size, &frev,
 453                                                        &crev, &igp_offset);
 454
 455                                 if (crev >= 2) {
 456                                         igp_obj =
 457                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 458                                              *) (ctx->bios + igp_offset);
 459
 460                                         if (igp_obj) {
 461                                                 uint32_t slot_config, ct;
 462
 463                                                 if (con_obj_num == 1)
 464                                                         slot_config =
 465                                                             igp_obj->
 466                                                             ulDDISlot1Config;
 467                                                 else
 468                                                         slot_config =
 469                                                             igp_obj->
 470                                                             ulDDISlot2Config;
 471
 472                                                 ct = (slot_config >> 16) & 0xff;
 473                                                 connector_type =
 474                                                     object_connector_convert
 475                                                     [ct];
 476                                                 connector_object_id = ct;
 477                                                 igp_lane_info =
 478                                                     slot_config & 0xffff;
 479                                         } else
 480                                                 continue;
 481                                 } else
 482                                         continue;
 483                         } else {
 484                                 igp_lane_info = 0;
 485                                 connector_type =
 486                                     object_connector_convert[con_obj_id];
 487                                 connector_object_id = con_obj_id;
 488                         }
 489
 490                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 491                                 continue;
 492
 493                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 494                              j++) {
 495                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 496
 497                                 enc_obj_id =
 498                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 499                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 500                                 enc_obj_num =
 501                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 502                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 503                                 enc_obj_type =
 504                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 505                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 506
 507                                 /* FIXME: add support for router objects */
 508                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 509                                         if (enc_obj_num == 2)
 510                                                 linkb = true;
 511                                         else
 512                                                 linkb = false;
 513
 514                                         radeon_add_atom_encoder(dev,
 515                                                                 enc_obj_id,
 516                                                                 le16_to_cpu
 517                                                                 (path->
 518                                                                  usDeviceTag));
 519
 520                                 }
 521                         }
 522
 523                         /* look up gpio for ddc, hpd */
 524                         if ((le16_to_cpu(path->usDeviceTag) &
 525                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 526                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 527                                         if (le16_to_cpu(path->usConnObjectId) ==
 528                                             le16_to_cpu(con_obj->asObjects[j].
 529                                                         usObjectID)) {
 530                                                 ATOM_COMMON_RECORD_HEADER
 531                                                     *record =
 532                                                     (ATOM_COMMON_RECORD_HEADER
 533                                                      *)
 534                                                     (ctx->bios + data_offset +
 535                                                      le16_to_cpu(con_obj->
 536                                                                  asObjects[j].
 537                                                                  usRecordOffset));
 538                                                 ATOM_I2C_RECORD *i2c_record;
 539                                                 ATOM_HPD_INT_RECORD *hpd_record;
 540                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 541                                                 hpd.hpd = RADEON_HPD_NONE;
 542
 543                                                 while (record->ucRecordType > 0
 544                                                        && record->
 545                                                        ucRecordType <=
 546                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 547                                                         switch (record->ucRecordType) {
 548                                                         case ATOM_I2C_RECORD_TYPE:
 549                                                                 i2c_record =
 550                                                                     (ATOM_I2C_RECORD *)
 551                                                                         record;
 552                                                                 i2c_config =
 553                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 554                                                                         &i2c_record->sucI2cId;
 555                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 556                                                                                                  i2c_config->
 557                                                                                                  ucAccess);
 558                                                                 break;
 559                                                         case ATOM_HPD_INT_RECORD_TYPE:
 560                                                                 hpd_record =
 561                                                                         (ATOM_HPD_INT_RECORD *)
 562                                                                         record;
 563                                                                 gpio = radeon_lookup_gpio(rdev,
 564                                                                                           hpd_record->ucHPDIntGPIOID);
 565                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 566                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 567                                                                 break;
 568                                                         }
 569                                                         record =
 570                                                             (ATOM_COMMON_RECORD_HEADER
 571                                                              *) ((char *)record
 572                                                                  +
 573                                                                  record->
 574                                                                  ucRecordSize);
 575                                                 }
 576                                                 break;
 577                                         }
 578                                 }
 579                         } else {
 580                                 hpd.hpd = RADEON_HPD_NONE;
 581                                 ddc_bus.valid = false;
 582                         }
 583
 584                         /* needed for aux chan transactions */
 585                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 586
 587                         conn_id = le16_to_cpu(path->usConnObjectId);
 588
 589                         if (!radeon_atom_apply_quirks
 590                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 591                              &ddc_bus, &conn_id, &hpd))
 592                                 continue;
 593
 594                         radeon_add_atom_connector(dev,
 595                                                   conn_id,
 596                                                   le16_to_cpu(path->
 597                                                               usDeviceTag),
 598                                                   connector_type, &ddc_bus,
 599                                                   linkb, igp_lane_info,
 600                                                   connector_object_id,
 601                                                   &hpd);
 602
 603                 }
 604         }
 605
 606         radeon_link_encoder_connector(dev);
 607
 608         return true;
 609 }
 610
 611 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 612                                                  int connector_type,
 613                                                  uint16_t devices)
 614 {
 615         struct radeon_device *rdev = dev->dev_private;
 616
 617         if (rdev->flags & RADEON_IS_IGP) {
 618                 return supported_devices_connector_object_id_convert
 619                         [connector_type];
 620         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 621                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 622                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 623                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 624                 struct atom_context *ctx = mode_info->atom_context;
 625                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 626                 uint16_t size, data_offset;
 627                 uint8_t frev, crev;
 628                 ATOM_XTMDS_INFO *xtmds;
 629
 630                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 631                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 632
 633                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 634                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 635                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 636                         else
 637                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 638                 } else {
 639                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 640                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 641                         else
 642                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 643                 }
 644         } else {
 645                 return supported_devices_connector_object_id_convert
 646                         [connector_type];
 647         }
 648 }
 649
 650 struct bios_connector {
 651         bool valid;
 652         uint16_t line_mux;
 653         uint16_t devices;
 654         int connector_type;
 655         struct radeon_i2c_bus_rec ddc_bus;
 656         struct radeon_hpd hpd;
 657 };
 658
 659 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 660                                                                  drm_device
 661                                                                  *dev)
 662 {
 663         struct radeon_device *rdev = dev->dev_private;
 664         struct radeon_mode_info *mode_info = &rdev->mode_info;
 665         struct atom_context *ctx = mode_info->atom_context;
 666         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 667         uint16_t size, data_offset;
 668         uint8_t frev, crev;
 669         uint16_t device_support;
 670         uint8_t dac;
 671         union atom_supported_devices *supported_devices;
 672         int i, j, max_device;
 673         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 674
 675         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 676
 677         supported_devices =
 678             (union atom_supported_devices *)(ctx->bios + data_offset);
 679
 680         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 681
 682         if (frev > 1)
 683                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 684         else
 685                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 686
 687         for (i = 0; i < max_device; i++) {
 688                 ATOM_CONNECTOR_INFO_I2C ci =
 689                     supported_devices->info.asConnInfo[i];
 690
 691                 bios_connectors[i].valid = false;
 692
 693                 if (!(device_support & (1 << i))) {
 694                         continue;
 695                 }
 696
 697                 if (i == ATOM_DEVICE_CV_INDEX) {
 698                         DRM_DEBUG("Skipping Component Video\n");
 699                         continue;
 700                 }
 701
 702                 bios_connectors[i].connector_type =
 703                     supported_devices_connector_convert[ci.sucConnectorInfo.
 704                                                         sbfAccess.
 705                                                         bfConnectorType];
 706
 707                 if (bios_connectors[i].connector_type ==
 708                     DRM_MODE_CONNECTOR_Unknown)
 709                         continue;
 710
 711                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 712
 713                 bios_connectors[i].line_mux =
 714                         ci.sucI2cId.ucAccess;
 715
 716                 /* give tv unique connector ids */
 717                 if (i == ATOM_DEVICE_TV1_INDEX) {
 718                         bios_connectors[i].ddc_bus.valid = false;
 719                         bios_connectors[i].line_mux = 50;
 720                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 721                         bios_connectors[i].ddc_bus.valid = false;
 722                         bios_connectors[i].line_mux = 51;
 723                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 724                         bios_connectors[i].ddc_bus.valid = false;
 725                         bios_connectors[i].line_mux = 52;
 726                 } else
 727                         bios_connectors[i].ddc_bus =
 728                             radeon_lookup_i2c_gpio(rdev,
 729                                                    bios_connectors[i].line_mux);
 730
 731                 if ((crev > 1) && (frev > 1)) {
 732                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 733                         switch (isb) {
 734                         case 0x4:
 735                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 736                                 break;
 737                         case 0xa:
 738                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 739                                 break;
 740                         default:
 741                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 742                                 break;
 743                         }
 744                 } else {
 745                         if (i == ATOM_DEVICE_DFP1_INDEX)
 746                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 747                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 748                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 749                         else
 750                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 751                 }
 752
 753                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 754                  * shared with a DVI port, we'll pick up the DVI connector when we
 755                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 756                  */
 757                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 758                         bios_connectors[i].connector_type =
 759                             DRM_MODE_CONNECTOR_VGA;
 760
 761                 if (!radeon_atom_apply_quirks
 762                     (dev, (1 << i), &bios_connectors[i].connector_type,
 763                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 764                      &bios_connectors[i].hpd))
 765                         continue;
 766
 767                 bios_connectors[i].valid = true;
 768                 bios_connectors[i].devices = (1 << i);
 769
 770                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 771                         radeon_add_atom_encoder(dev,
 772                                                 radeon_get_encoder_id(dev,
 773                                                                       (1 << i),
 774                                                                       dac),
 775                                                 (1 << i));
 776                 else
 777                         radeon_add_legacy_encoder(dev,
 778                                                   radeon_get_encoder_id(dev,
 779                                                                         (1 << i),
 780                                                                         dac),
 781                                                   (1 << i));
 782         }
 783
 784         /* combine shared connectors */
 785         for (i = 0; i < max_device; i++) {
 786                 if (bios_connectors[i].valid) {
 787                         for (j = 0; j < max_device; j++) {
 788                                 if (bios_connectors[j].valid && (i != j)) {
 789                                         if (bios_connectors[i].line_mux ==
 790                                             bios_connectors[j].line_mux) {
 791                                                 /* make sure not to combine LVDS */
 792                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 793                                                         bios_connectors[i].line_mux = 53;
 794                                                         bios_connectors[i].ddc_bus.valid = false;
 795                                                         continue;
 796                                                 }
 797                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 798                                                         bios_connectors[j].line_mux = 53;
 799                                                         bios_connectors[j].ddc_bus.valid = false;
 800                                                         continue;
 801                                                 }
 802                                                 /* combine analog and digital for DVI-I */
 803                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 804                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 805                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 806                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 807                                                         bios_connectors[i].devices |=
 808                                                                 bios_connectors[j].devices;
 809                                                         bios_connectors[i].connector_type =
 810                                                                 DRM_MODE_CONNECTOR_DVII;
 811                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 812                                                                 bios_connectors[i].hpd =
 813                                                                         bios_connectors[j].hpd;
 814                                                         bios_connectors[j].valid = false;
 815                                                 }
 816                                         }
 817                                 }
 818                         }
 819                 }
 820         }
 821
 822         /* add the connectors */
 823         for (i = 0; i < max_device; i++) {
 824                 if (bios_connectors[i].valid) {
 825                         uint16_t connector_object_id =
 826                                 atombios_get_connector_object_id(dev,
 827                                                       bios_connectors[i].connector_type,
 828                                                       bios_connectors[i].devices);
 829                         radeon_add_atom_connector(dev,
 830                                                   bios_connectors[i].line_mux,
 831                                                   bios_connectors[i].devices,
 832                                                   bios_connectors[i].
 833                                                   connector_type,
 834                                                   &bios_connectors[i].ddc_bus,
 835                                                   false, 0,
 836                                                   connector_object_id,
 837                                                   &bios_connectors[i].hpd);
 838                 }
 839         }
 840
 841         radeon_link_encoder_connector(dev);
 842
 843         return true;
 844 }
 845
 846 union firmware_info {
 847         ATOM_FIRMWARE_INFO info;
 848         ATOM_FIRMWARE_INFO_V1_2 info_12;
 849         ATOM_FIRMWARE_INFO_V1_3 info_13;
 850         ATOM_FIRMWARE_INFO_V1_4 info_14;
 851         ATOM_FIRMWARE_INFO_V2_1 info_21;
 852 };
 853
 854 bool radeon_atom_get_clock_info(struct drm_device *dev)
 855 {
 856         struct radeon_device *rdev = dev->dev_private;
 857         struct radeon_mode_info *mode_info = &rdev->mode_info;
 858         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 859         union firmware_info *firmware_info;
 860         uint8_t frev, crev;
 861         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 862         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 863         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 864         struct radeon_pll *spll = &rdev->clock.spll;
 865         struct radeon_pll *mpll = &rdev->clock.mpll;
 866         uint16_t data_offset;
 867
 868         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 869                                &crev, &data_offset);
 870
 871         firmware_info =
 872             (union firmware_info *)(mode_info->atom_context->bios +
 873                                     data_offset);
 874
 875         if (firmware_info) {
 876                 /* pixel clocks */
 877                 p1pll->reference_freq =
 878                     le16_to_cpu(firmware_info->info.usReferenceClock);
 879                 p1pll->reference_div = 0;
 880
 881                 if (crev < 2)
 882                         p1pll->pll_out_min =
 883                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 884                 else
 885                         p1pll->pll_out_min =
 886                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 887                 p1pll->pll_out_max =
 888                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 889
 890                 if (crev >= 4) {
 891                         p1pll->lcd_pll_out_min =
 892                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 893                         if (p1pll->lcd_pll_out_min == 0)
 894                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 895                         p1pll->lcd_pll_out_max =
 896                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 897                         if (p1pll->lcd_pll_out_max == 0)
 898                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 899                 } else {
 900                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 901                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 902                 }
 903
 904                 if (p1pll->pll_out_min == 0) {
 905                         if (ASIC_IS_AVIVO(rdev))
 906                                 p1pll->pll_out_min = 64800;
 907                         else
 908                                 p1pll->pll_out_min = 20000;
 909                 } else if (p1pll->pll_out_min > 64800) {
 910                         /* Limiting the pll output range is a good thing generally as
 911                          * it limits the number of possible pll combinations for a given
 912                          * frequency presumably to the ones that work best on each card.
 913                          * However, certain duallink DVI monitors seem to like
 914                          * pll combinations that would be limited by this at least on
 915                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 916                          * family.
 917                          */
 918                         if (!radeon_new_pll)
 919                                 p1pll->pll_out_min = 64800;
 920                 }
 921
 922                 p1pll->pll_in_min =
 923                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 924                 p1pll->pll_in_max =
 925                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 926
 927                 *p2pll = *p1pll;
 928
 929                 /* system clock */
 930                 spll->reference_freq =
 931                     le16_to_cpu(firmware_info->info.usReferenceClock);
 932                 spll->reference_div = 0;
 933
 934                 spll->pll_out_min =
 935                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 936                 spll->pll_out_max =
 937                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 938
 939                 /* ??? */
 940                 if (spll->pll_out_min == 0) {
 941                         if (ASIC_IS_AVIVO(rdev))
 942                                 spll->pll_out_min = 64800;
 943                         else
 944                                 spll->pll_out_min = 20000;
 945                 }
 946
 947                 spll->pll_in_min =
 948                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 949                 spll->pll_in_max =
 950                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 951
 952                 /* memory clock */
 953                 mpll->reference_freq =
 954                     le16_to_cpu(firmware_info->info.usReferenceClock);
 955                 mpll->reference_div = 0;
 956
 957                 mpll->pll_out_min =
 958                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 959                 mpll->pll_out_max =
 960                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 961
 962                 /* ??? */
 963                 if (mpll->pll_out_min == 0) {
 964                         if (ASIC_IS_AVIVO(rdev))
 965                                 mpll->pll_out_min = 64800;
 966                         else
 967                                 mpll->pll_out_min = 20000;
 968                 }
 969
 970                 mpll->pll_in_min =
 971                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 972                 mpll->pll_in_max =
 973                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 974
 975                 rdev->clock.default_sclk =
 976                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 977                 rdev->clock.default_mclk =
 978                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 979
 980                 if (ASIC_IS_DCE4(rdev)) {
 981                         rdev->clock.default_dispclk =
 982                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 983                         if (rdev->clock.default_dispclk == 0)
 984                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
 985                         rdev->clock.dp_extclk =
 986                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 987                 }
 988                 *dcpll = *p1pll;
 989
 990                 return true;
 991         }
 992
 993         return false;
 994 }
 995
 996 union igp_info {
 997         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 998         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 999 };
1000
1001 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1002 {
1003         struct radeon_mode_info *mode_info = &rdev->mode_info;
1004         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1005         union igp_info *igp_info;
1006         u8 frev, crev;
1007         u16 data_offset;
1008
1009         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1010                                &crev, &data_offset);
1011
1012         igp_info = (union igp_info *)(mode_info->atom_context->bios +
1013                                       data_offset);
1014
1015         if (igp_info) {
1016                 switch (crev) {
1017                 case 1:
1018                         if (igp_info->info.ucMemoryType & 0xf0)
1019                                 return true;
1020                         break;
1021                 case 2:
1022                         if (igp_info->info_2.ucMemoryType & 0x0f)
1023                                 return true;
1024                         break;
1025                 default:
1026                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1027                         break;
1028                 }
1029         }
1030         return false;
1031 }
1032
1033 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1034                                    struct radeon_encoder_int_tmds *tmds)
1035 {
1036         struct drm_device *dev = encoder->base.dev;
1037         struct radeon_device *rdev = dev->dev_private;
1038         struct radeon_mode_info *mode_info = &rdev->mode_info;
1039         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1040         uint16_t data_offset;
1041         struct _ATOM_TMDS_INFO *tmds_info;
1042         uint8_t frev, crev;
1043         uint16_t maxfreq;
1044         int i;
1045
1046         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1047                                &crev, &data_offset);
1048
1049         tmds_info =
1050             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1051                                        data_offset);
1052
1053         if (tmds_info) {
1054                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1055                 for (i = 0; i < 4; i++) {
1056                         tmds->tmds_pll[i].freq =
1057                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1058                         tmds->tmds_pll[i].value =
1059                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1060                         tmds->tmds_pll[i].value |=
1061                             (tmds_info->asMiscInfo[i].
1062                              ucPLL_VCO_Gain & 0x3f) << 6;
1063                         tmds->tmds_pll[i].value |=
1064                             (tmds_info->asMiscInfo[i].
1065                              ucPLL_DutyCycle & 0xf) << 12;
1066                         tmds->tmds_pll[i].value |=
1067                             (tmds_info->asMiscInfo[i].
1068                              ucPLL_VoltageSwing & 0xf) << 16;
1069
1070                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1071                                   tmds->tmds_pll[i].freq,
1072                                   tmds->tmds_pll[i].value);
1073
1074                         if (maxfreq == tmds->tmds_pll[i].freq) {
1075                                 tmds->tmds_pll[i].freq = 0xffffffff;
1076                                 break;
1077                         }
1078                 }
1079                 return true;
1080         }
1081         return false;
1082 }
1083
1084 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1085                                                           radeon_encoder
1086                                                           *encoder,
1087                                                           int id)
1088 {
1089         struct drm_device *dev = encoder->base.dev;
1090         struct radeon_device *rdev = dev->dev_private;
1091         struct radeon_mode_info *mode_info = &rdev->mode_info;
1092         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1093         uint16_t data_offset;
1094         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1095         uint8_t frev, crev;
1096         struct radeon_atom_ss *ss = NULL;
1097         int i;
1098
1099         if (id > ATOM_MAX_SS_ENTRY)
1100                 return NULL;
1101
1102         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1103                                &crev, &data_offset);
1104
1105         ss_info =
1106             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1107
1108         if (ss_info) {
1109                 ss =
1110                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1111
1112                 if (!ss)
1113                         return NULL;
1114
1115                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1116                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1117                                 ss->percentage =
1118                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1119                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1120                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1121                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1122                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1123                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1124                                 break;
1125                         }
1126                 }
1127         }
1128         return ss;
1129 }
1130
1131 union lvds_info {
1132         struct _ATOM_LVDS_INFO info;
1133         struct _ATOM_LVDS_INFO_V12 info_12;
1134 };
1135
1136 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1137                                                               radeon_encoder
1138                                                               *encoder)
1139 {
1140         struct drm_device *dev = encoder->base.dev;
1141         struct radeon_device *rdev = dev->dev_private;
1142         struct radeon_mode_info *mode_info = &rdev->mode_info;
1143         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1144         uint16_t data_offset, misc;
1145         union lvds_info *lvds_info;
1146         uint8_t frev, crev;
1147         struct radeon_encoder_atom_dig *lvds = NULL;
1148
1149         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1150                                &crev, &data_offset);
1151
1152         lvds_info =
1153             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1154
1155         if (lvds_info) {
1156                 lvds =
1157                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1158
1159                 if (!lvds)
1160                         return NULL;
1161
1162                 lvds->native_mode.clock =
1163                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1164                 lvds->native_mode.hdisplay =
1165                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1166                 lvds->native_mode.vdisplay =
1167                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1168                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1169                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1170                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1171                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1172                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1173                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1174                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1175                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1176                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1177                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1178                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1179                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1180                 lvds->panel_pwr_delay =
1181                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1182                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1183
1184                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1185                 if (misc & ATOM_VSYNC_POLARITY)
1186                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1187                 if (misc & ATOM_HSYNC_POLARITY)
1188                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1189                 if (misc & ATOM_COMPOSITESYNC)
1190                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1191                 if (misc & ATOM_INTERLACE)
1192                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1193                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1194                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1195
1196                 /* set crtc values */
1197                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1198
1199                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1200
1201                 if (ASIC_IS_AVIVO(rdev)) {
1202                         if (radeon_new_pll == 0)
1203                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1204                         else
1205                                 lvds->pll_algo = PLL_ALGO_NEW;
1206                 } else {
1207                         if (radeon_new_pll == 1)
1208                                 lvds->pll_algo = PLL_ALGO_NEW;
1209                         else
1210                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1211                 }
1212
1213                 encoder->native_mode = lvds->native_mode;
1214         }
1215         return lvds;
1216 }
1217
1218 struct radeon_encoder_primary_dac *
1219 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1220 {
1221         struct drm_device *dev = encoder->base.dev;
1222         struct radeon_device *rdev = dev->dev_private;
1223         struct radeon_mode_info *mode_info = &rdev->mode_info;
1224         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1225         uint16_t data_offset;
1226         struct _COMPASSIONATE_DATA *dac_info;
1227         uint8_t frev, crev;
1228         uint8_t bg, dac;
1229         struct radeon_encoder_primary_dac *p_dac = NULL;
1230
1231         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1232
1233         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1234
1235         if (dac_info) {
1236                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1237
1238                 if (!p_dac)
1239                         return NULL;
1240
1241                 bg = dac_info->ucDAC1_BG_Adjustment;
1242                 dac = dac_info->ucDAC1_DAC_Adjustment;
1243                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1244
1245         }
1246         return p_dac;
1247 }
1248
1249 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1250                                 struct drm_display_mode *mode)
1251 {
1252         struct radeon_mode_info *mode_info = &rdev->mode_info;
1253         ATOM_ANALOG_TV_INFO *tv_info;
1254         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1255         ATOM_DTD_FORMAT *dtd_timings;
1256         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1257         u8 frev, crev;
1258         u16 data_offset, misc;
1259
1260         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1261
1262         switch (crev) {
1263         case 1:
1264                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1265                 if (index > MAX_SUPPORTED_TV_TIMING)
1266                         return false;
1267
1268                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1269                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1270                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1271                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1272                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1273
1274                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1275                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1276                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1277                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1278                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1279
1280                 mode->flags = 0;
1281                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1282                 if (misc & ATOM_VSYNC_POLARITY)
1283                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1284                 if (misc & ATOM_HSYNC_POLARITY)
1285                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1286                 if (misc & ATOM_COMPOSITESYNC)
1287                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1288                 if (misc & ATOM_INTERLACE)
1289                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1290                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1291                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1292
1293                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1294
1295                 if (index == 1) {
1296                         /* PAL timings appear to have wrong values for totals */
1297                         mode->crtc_htotal -= 1;
1298                         mode->crtc_vtotal -= 1;
1299                 }
1300                 break;
1301         case 2:
1302                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1303                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1304                         return false;
1305
1306                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1307                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1308                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1309                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1310                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1311                         le16_to_cpu(dtd_timings->usHSyncOffset);
1312                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1313                         le16_to_cpu(dtd_timings->usHSyncWidth);
1314
1315                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1316                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1317                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1318                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1319                         le16_to_cpu(dtd_timings->usVSyncOffset);
1320                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1321                         le16_to_cpu(dtd_timings->usVSyncWidth);
1322
1323                 mode->flags = 0;
1324                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1325                 if (misc & ATOM_VSYNC_POLARITY)
1326                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1327                 if (misc & ATOM_HSYNC_POLARITY)
1328                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1329                 if (misc & ATOM_COMPOSITESYNC)
1330                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1331                 if (misc & ATOM_INTERLACE)
1332                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1333                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1334                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1335
1336                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1337                 break;
1338         }
1339         return true;
1340 }
1341
1342 enum radeon_tv_std
1343 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1344 {
1345         struct radeon_mode_info *mode_info = &rdev->mode_info;
1346         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1347         uint16_t data_offset;
1348         uint8_t frev, crev;
1349         struct _ATOM_ANALOG_TV_INFO *tv_info;
1350         enum radeon_tv_std tv_std = TV_STD_NTSC;
1351
1352         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1353
1354         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1355
1356         switch (tv_info->ucTV_BootUpDefaultStandard) {
1357         case ATOM_TV_NTSC:
1358                 tv_std = TV_STD_NTSC;
1359                 DRM_INFO("Default TV standard: NTSC\n");
1360                 break;
1361         case ATOM_TV_NTSCJ:
1362                 tv_std = TV_STD_NTSC_J;
1363                 DRM_INFO("Default TV standard: NTSC-J\n");
1364                 break;
1365         case ATOM_TV_PAL:
1366                 tv_std = TV_STD_PAL;
1367                 DRM_INFO("Default TV standard: PAL\n");
1368                 break;
1369         case ATOM_TV_PALM:
1370                 tv_std = TV_STD_PAL_M;
1371                 DRM_INFO("Default TV standard: PAL-M\n");
1372                 break;
1373         case ATOM_TV_PALN:
1374                 tv_std = TV_STD_PAL_N;
1375                 DRM_INFO("Default TV standard: PAL-N\n");
1376                 break;
1377         case ATOM_TV_PALCN:
1378                 tv_std = TV_STD_PAL_CN;
1379                 DRM_INFO("Default TV standard: PAL-CN\n");
1380                 break;
1381         case ATOM_TV_PAL60:
1382                 tv_std = TV_STD_PAL_60;
1383                 DRM_INFO("Default TV standard: PAL-60\n");
1384                 break;
1385         case ATOM_TV_SECAM:
1386                 tv_std = TV_STD_SECAM;
1387                 DRM_INFO("Default TV standard: SECAM\n");
1388                 break;
1389         default:
1390                 tv_std = TV_STD_NTSC;
1391                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1392                 break;
1393         }
1394         return tv_std;
1395 }
1396
1397 struct radeon_encoder_tv_dac *
1398 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1399 {
1400         struct drm_device *dev = encoder->base.dev;
1401         struct radeon_device *rdev = dev->dev_private;
1402         struct radeon_mode_info *mode_info = &rdev->mode_info;
1403         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1404         uint16_t data_offset;
1405         struct _COMPASSIONATE_DATA *dac_info;
1406         uint8_t frev, crev;
1407         uint8_t bg, dac;
1408         struct radeon_encoder_tv_dac *tv_dac = NULL;
1409
1410         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1411
1412         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1413
1414         if (dac_info) {
1415                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1416
1417                 if (!tv_dac)
1418                         return NULL;
1419
1420                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1421                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1422                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1423
1424                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1425                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1426                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1427
1428                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1429                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1430                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1431
1432                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1433         }
1434         return tv_dac;
1435 }
1436
1437 static const char *thermal_controller_names[] = {
1438         "NONE",
1439         "LM63",
1440         "ADM1032",
1441         "ADM1030",
1442         "MUA6649",
1443         "LM64",
1444         "F75375",
1445         "ASC7512",
1446 };
1447
1448 static const char *pp_lib_thermal_controller_names[] = {
1449         "NONE",
1450         "LM63",
1451         "ADM1032",
1452         "ADM1030",
1453         "MUA6649",
1454         "LM64",
1455         "F75375",
1456         "RV6xx",
1457         "RV770",
1458         "ADT7473",
1459 };
1460
1461 union power_info {
1462         struct _ATOM_POWERPLAY_INFO info;
1463         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1464         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1465         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1466 };
1467
1468 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1469 {
1470         struct radeon_mode_info *mode_info = &rdev->mode_info;
1471         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1472         u16 data_offset;
1473         u8 frev, crev;
1474         u32 misc, misc2 = 0, sclk, mclk;
1475         union power_info *power_info;
1476         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1477         struct _ATOM_PPLIB_STATE *power_state;
1478         int num_modes = 0, i, j;
1479         int state_index = 0, mode_index = 0;
1480         struct radeon_i2c_bus_rec i2c_bus;
1481
1482         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1483
1484         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1485
1486         rdev->pm.default_power_state = NULL;
1487
1488         if (power_info) {
1489                 if (frev < 4) {
1490                         /* add the i2c bus for thermal/fan chip */
1491                         if (power_info->info.ucOverdriveThermalController > 0) {
1492                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1493                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1494                                          power_info->info.ucOverdriveControllerAddress >> 1);
1495                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1496                                 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1497                         }
1498                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1499                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1500                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1501                         for (i = 0; i < num_modes; i++) {
1502                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1503                                 switch (frev) {
1504                                 case 1:
1505                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1506                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1507                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1508                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1509                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1510                                         /* skip invalid modes */
1511                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1512                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1513                                                 continue;
1514                                         /* skip overclock modes for now */
1515                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1516                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1517                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1518                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1519                                                 continue;
1520                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1521                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1522                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1523                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1524                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1525                                                         VOLTAGE_GPIO;
1526                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1527                                                         radeon_lookup_gpio(rdev,
1528                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1529                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1530                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1531                                                                 true;
1532                                                 else
1533                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1534                                                                 false;
1535                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1536                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1537                                                         VOLTAGE_VDDC;
1538                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1539                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1540                                         }
1541                                         /* order matters! */
1542                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1543                                                 rdev->pm.power_state[state_index].type =
1544                                                         POWER_STATE_TYPE_POWERSAVE;
1545                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1546                                                 rdev->pm.power_state[state_index].type =
1547                                                         POWER_STATE_TYPE_BATTERY;
1548                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1549                                                 rdev->pm.power_state[state_index].type =
1550                                                         POWER_STATE_TYPE_BATTERY;
1551                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1552                                                 rdev->pm.power_state[state_index].type =
1553                                                         POWER_STATE_TYPE_BALANCED;
1554                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1555                                                 rdev->pm.power_state[state_index].type =
1556                                                         POWER_STATE_TYPE_PERFORMANCE;
1557                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1558                                                 rdev->pm.power_state[state_index].type =
1559                                                         POWER_STATE_TYPE_DEFAULT;
1560                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1561                                                 rdev->pm.power_state[state_index].default_clock_mode =
1562                                                         &rdev->pm.power_state[state_index].clock_info[0];
1563                                         }
1564                                         state_index++;
1565                                         break;
1566                                 case 2:
1567                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1568                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1569                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1570                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1571                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1572                                         /* skip invalid modes */
1573                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1574                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1575                                                 continue;
1576                                         /* skip overclock modes for now */
1577                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1578                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1579                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1580                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1581                                                 continue;
1582                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1583                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1584                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1585                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1586                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1587                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1588                                                         VOLTAGE_GPIO;
1589                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1590                                                         radeon_lookup_gpio(rdev,
1591                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1592                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1593                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1594                                                                 true;
1595                                                 else
1596                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1597                                                                 false;
1598                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1599                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1600                                                         VOLTAGE_VDDC;
1601                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1602                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1603                                         }
1604                                         /* order matters! */
1605                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1606                                                 rdev->pm.power_state[state_index].type =
1607                                                         POWER_STATE_TYPE_POWERSAVE;
1608                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1609                                                 rdev->pm.power_state[state_index].type =
1610                                                         POWER_STATE_TYPE_BATTERY;
1611                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1612                                                 rdev->pm.power_state[state_index].type =
1613                                                         POWER_STATE_TYPE_BATTERY;
1614                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1615                                                 rdev->pm.power_state[state_index].type =
1616                                                         POWER_STATE_TYPE_BALANCED;
1617                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1618                                                 rdev->pm.power_state[state_index].type =
1619                                                         POWER_STATE_TYPE_PERFORMANCE;
1620                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1621                                                 rdev->pm.power_state[state_index].type =
1622                                                         POWER_STATE_TYPE_BALANCED;
1623                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1624                                                 rdev->pm.power_state[state_index].type =
1625                                                         POWER_STATE_TYPE_DEFAULT;
1626                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1627                                                 rdev->pm.power_state[state_index].default_clock_mode =
1628                                                         &rdev->pm.power_state[state_index].clock_info[0];
1629                                         }
1630                                         state_index++;
1631                                         break;
1632                                 case 3:
1633                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1634                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1635                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1636                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1637                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1638                                         /* skip invalid modes */
1639                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1640                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1641                                                 continue;
1642                                         /* skip overclock modes for now */
1643                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1644                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1645                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1646                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1647                                                 continue;
1648                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1649                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1650                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1651                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1652                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1653                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1654                                                         VOLTAGE_GPIO;
1655                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1656                                                         radeon_lookup_gpio(rdev,
1657                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1658                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1659                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1660                                                                 true;
1661                                                 else
1662                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1663                                                                 false;
1664                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1665                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1666                                                         VOLTAGE_VDDC;
1667                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1668                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1669                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1670                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1671                                                                 true;
1672                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1673                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1674                                                 }
1675                                         }
1676                                         /* order matters! */
1677                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1678                                                 rdev->pm.power_state[state_index].type =
1679                                                         POWER_STATE_TYPE_POWERSAVE;
1680                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1681                                                 rdev->pm.power_state[state_index].type =
1682                                                         POWER_STATE_TYPE_BATTERY;
1683                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1684                                                 rdev->pm.power_state[state_index].type =
1685                                                         POWER_STATE_TYPE_BATTERY;
1686                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1687                                                 rdev->pm.power_state[state_index].type =
1688                                                         POWER_STATE_TYPE_BALANCED;
1689                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1690                                                 rdev->pm.power_state[state_index].type =
1691                                                         POWER_STATE_TYPE_PERFORMANCE;
1692                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1693                                                 rdev->pm.power_state[state_index].type =
1694                                                         POWER_STATE_TYPE_BALANCED;
1695                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1696                                                 rdev->pm.power_state[state_index].type =
1697                                                         POWER_STATE_TYPE_DEFAULT;
1698                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1699                                                 rdev->pm.power_state[state_index].default_clock_mode =
1700                                                         &rdev->pm.power_state[state_index].clock_info[0];
1701                                         }
1702                                         state_index++;
1703                                         break;
1704                                 }
1705                         }
1706                 } else if (frev == 4) {
1707                         /* add the i2c bus for thermal/fan chip */
1708                         /* no support for internal controller yet */
1709                         if (power_info->info_4.sThermalController.ucType > 0) {
1710                                 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1711                                     (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1712                                         DRM_INFO("Internal thermal controller %s fan control\n",
1713                                                  (power_info->info_4.sThermalController.ucFanParameters &
1714                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1715                                 } else {
1716                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1717                                                  pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1718                                                  power_info->info_4.sThermalController.ucI2cAddress >> 1,
1719                                                  (power_info->info_4.sThermalController.ucFanParameters &
1720                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1721                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1722                                         rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1723                                 }
1724                         }
1725                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1726                                 mode_index = 0;
1727                                 power_state = (struct _ATOM_PPLIB_STATE *)
1728                                         (mode_info->atom_context->bios +
1729                                          data_offset +
1730                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1731                                          i * power_info->info_4.ucStateEntrySize);
1732                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1733                                         (mode_info->atom_context->bios +
1734                                          data_offset +
1735                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1736                                          (power_state->ucNonClockStateIndex *
1737                                           power_info->info_4.ucNonClockSize));
1738                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1739                                         if (rdev->flags & RADEON_IS_IGP) {
1740                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1741                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1742                                                         (mode_info->atom_context->bios +
1743                                                          data_offset +
1744                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1745                                                          (power_state->ucClockStateIndices[j] *
1746                                                           power_info->info_4.ucClockInfoSize));
1747                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1748                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1749                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1750                                                 /* skip invalid modes */
1751                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1752                                                         continue;
1753                                                 /* skip overclock modes for now */
1754                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1755                                                     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1756                                                         continue;
1757                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1758                                                         VOLTAGE_SW;
1759                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1760                                                         clock_info->usVDDC;
1761                                                 mode_index++;
1762                                         } else {
1763                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1764                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1765                                                         (mode_info->atom_context->bios +
1766                                                          data_offset +
1767                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1768                                                          (power_state->ucClockStateIndices[j] *
1769                                                           power_info->info_4.ucClockInfoSize));
1770                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1771                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1772                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1773                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1774                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1775                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1776                                                 /* skip invalid modes */
1777                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1778                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1779                                                         continue;
1780                                                 /* skip overclock modes for now */
1781                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1782                                                      rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1783                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1784                                                      rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1785                                                         continue;
1786                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1787                                                         VOLTAGE_SW;
1788                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1789                                                         clock_info->usVDDC;
1790                                                 mode_index++;
1791                                         }
1792                                 }
1793                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1794                                 if (mode_index) {
1795                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1796                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1797                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1798                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1799                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1800                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1801                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1802                                                 rdev->pm.power_state[state_index].type =
1803                                                         POWER_STATE_TYPE_BATTERY;
1804                                                 break;
1805                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1806                                                 rdev->pm.power_state[state_index].type =
1807                                                         POWER_STATE_TYPE_BALANCED;
1808                                                 break;
1809                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1810                                                 rdev->pm.power_state[state_index].type =
1811                                                         POWER_STATE_TYPE_PERFORMANCE;
1812                                                 break;
1813                                         }
1814                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1815                                                 rdev->pm.power_state[state_index].type =
1816                                                         POWER_STATE_TYPE_DEFAULT;
1817                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1818                                                 rdev->pm.power_state[state_index].default_clock_mode =
1819                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1820                                         }
1821                                         state_index++;
1822                                 }
1823                         }
1824                 }
1825         } else {
1826                 /* XXX figure out some good default low power mode for cards w/out power tables */
1827         }
1828
1829         if (rdev->pm.default_power_state == NULL) {
1830                 /* add the default mode */
1831                 rdev->pm.power_state[state_index].type =
1832                         POWER_STATE_TYPE_DEFAULT;
1833                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1834                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1835                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1836                 rdev->pm.power_state[state_index].default_clock_mode =
1837                         &rdev->pm.power_state[state_index].clock_info[0];
1838                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1839                 if (rdev->asic->get_pcie_lanes)
1840                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1841                 else
1842                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1843                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1844                 state_index++;
1845         }
1846         rdev->pm.num_power_states = state_index;
1847
1848         rdev->pm.current_power_state = rdev->pm.default_power_state;
1849         rdev->pm.current_clock_mode =
1850                 rdev->pm.default_power_state->default_clock_mode;
1851 }
1852
1853 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1854 {
1855         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1856         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1857
1858         args.ucEnable = enable;
1859
1860         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1861 }
1862
1863 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1864 {
1865         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1866         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1867
1868         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1869         return args.ulReturnEngineClock;
1870 }
1871
1872 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1873 {
1874         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1875         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1876
1877         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1878         return args.ulReturnMemoryClock;
1879 }
1880
1881 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1882                                   uint32_t eng_clock)
1883 {
1884         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1885         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1886
1887         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1888
1889         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1890 }
1891
1892 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1893                                   uint32_t mem_clock)
1894 {
1895         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1896         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1897
1898         if (rdev->flags & RADEON_IS_IGP)
1899                 return;
1900
1901         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1902
1903         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1904 }
1905
1906 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1907 {
1908         struct radeon_device *rdev = dev->dev_private;
1909         uint32_t bios_2_scratch, bios_6_scratch;
1910
1911         if (rdev->family >= CHIP_R600) {
1912                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1913                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1914         } else {
1915                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1916                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1917         }
1918
1919         /* let the bios control the backlight */
1920         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1921
1922         /* tell the bios not to handle mode switching */
1923         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1924
1925         if (rdev->family >= CHIP_R600) {
1926                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1927                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1928         } else {
1929                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1930                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1931         }
1932
1933 }
1934
1935 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1936 {
1937         uint32_t scratch_reg;
1938         int i;
1939
1940         if (rdev->family >= CHIP_R600)
1941                 scratch_reg = R600_BIOS_0_SCRATCH;
1942         else
1943                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1944
1945         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1946                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1947 }
1948
1949 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1950 {
1951         uint32_t scratch_reg;
1952         int i;
1953
1954         if (rdev->family >= CHIP_R600)
1955                 scratch_reg = R600_BIOS_0_SCRATCH;
1956         else
1957                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1958
1959         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1960                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1961 }
1962
1963 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1964 {
1965         struct drm_device *dev = encoder->dev;
1966         struct radeon_device *rdev = dev->dev_private;
1967         uint32_t bios_6_scratch;
1968
1969         if (rdev->family >= CHIP_R600)
1970                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1971         else
1972                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1973
1974         if (lock)
1975                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1976         else
1977                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1978
1979         if (rdev->family >= CHIP_R600)
1980                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1981         else
1982                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1983 }
1984
1985 /* at some point we may want to break this out into individual functions */
1986 void
1987 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1988                                        struct drm_encoder *encoder,
1989                                        bool connected)
1990 {
1991         struct drm_device *dev = connector->dev;
1992         struct radeon_device *rdev = dev->dev_private;
1993         struct radeon_connector *radeon_connector =
1994             to_radeon_connector(connector);
1995         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1996         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1997
1998         if (rdev->family >= CHIP_R600) {
1999                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2000                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2001                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2002         } else {
2003                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2004                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2005                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2006         }
2007
2008         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2009             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2010                 if (connected) {
2011                         DRM_DEBUG("TV1 connected\n");
2012                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2013                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2014                 } else {
2015                         DRM_DEBUG("TV1 disconnected\n");
2016                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2017                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2018                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2019                 }
2020         }
2021         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2022             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2023                 if (connected) {
2024                         DRM_DEBUG("CV connected\n");
2025                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2026                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2027                 } else {
2028                         DRM_DEBUG("CV disconnected\n");
2029                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2030                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2031                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2032                 }
2033         }
2034         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2035             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2036                 if (connected) {
2037                         DRM_DEBUG("LCD1 connected\n");
2038                         bios_0_scratch |= ATOM_S0_LCD1;
2039                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2040                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2041                 } else {
2042                         DRM_DEBUG("LCD1 disconnected\n");
2043                         bios_0_scratch &= ~ATOM_S0_LCD1;
2044                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2045                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2046                 }
2047         }
2048         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2049             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2050                 if (connected) {
2051                         DRM_DEBUG("CRT1 connected\n");
2052                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2053                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2054                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2055                 } else {
2056                         DRM_DEBUG("CRT1 disconnected\n");
2057                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2058                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2059                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2060                 }
2061         }
2062         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2063             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2064                 if (connected) {
2065                         DRM_DEBUG("CRT2 connected\n");
2066                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2067                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2068                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2069                 } else {
2070                         DRM_DEBUG("CRT2 disconnected\n");
2071                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2072                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2073                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2074                 }
2075         }
2076         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2077             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2078                 if (connected) {
2079                         DRM_DEBUG("DFP1 connected\n");
2080                         bios_0_scratch |= ATOM_S0_DFP1;
2081                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2082                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2083                 } else {
2084                         DRM_DEBUG("DFP1 disconnected\n");
2085                         bios_0_scratch &= ~ATOM_S0_DFP1;
2086                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2087                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2088                 }
2089         }
2090         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2091             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2092                 if (connected) {
2093                         DRM_DEBUG("DFP2 connected\n");
2094                         bios_0_scratch |= ATOM_S0_DFP2;
2095                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2096                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2097                 } else {
2098                         DRM_DEBUG("DFP2 disconnected\n");
2099                         bios_0_scratch &= ~ATOM_S0_DFP2;
2100                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2101                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2102                 }
2103         }
2104         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2105             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2106                 if (connected) {
2107                         DRM_DEBUG("DFP3 connected\n");
2108                         bios_0_scratch |= ATOM_S0_DFP3;
2109                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2110                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2111                 } else {
2112                         DRM_DEBUG("DFP3 disconnected\n");
2113                         bios_0_scratch &= ~ATOM_S0_DFP3;
2114                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2115                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2116                 }
2117         }
2118         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2119             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2120                 if (connected) {
2121                         DRM_DEBUG("DFP4 connected\n");
2122                         bios_0_scratch |= ATOM_S0_DFP4;
2123                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2124                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2125                 } else {
2126                         DRM_DEBUG("DFP4 disconnected\n");
2127                         bios_0_scratch &= ~ATOM_S0_DFP4;
2128                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2129                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2130                 }
2131         }
2132         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2133             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2134                 if (connected) {
2135                         DRM_DEBUG("DFP5 connected\n");
2136                         bios_0_scratch |= ATOM_S0_DFP5;
2137                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2138                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2139                 } else {
2140                         DRM_DEBUG("DFP5 disconnected\n");
2141                         bios_0_scratch &= ~ATOM_S0_DFP5;
2142                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2143                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2144                 }
2145         }
2146
2147         if (rdev->family >= CHIP_R600) {
2148                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2149                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2150                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2151         } else {
2152                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2153                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2154                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2155         }
2156 }
2157
2158 void
2159 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2160 {
2161         struct drm_device *dev = encoder->dev;
2162         struct radeon_device *rdev = dev->dev_private;
2163         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2164         uint32_t bios_3_scratch;
2165
2166         if (rdev->family >= CHIP_R600)
2167                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2168         else
2169                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2170
2171         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2172                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2173                 bios_3_scratch |= (crtc << 18);
2174         }
2175         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2176                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2177                 bios_3_scratch |= (crtc << 24);
2178         }
2179         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2180                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2181                 bios_3_scratch |= (crtc << 16);
2182         }
2183         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2184                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2185                 bios_3_scratch |= (crtc << 20);
2186         }
2187         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2188                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2189                 bios_3_scratch |= (crtc << 17);
2190         }
2191         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2192                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2193                 bios_3_scratch |= (crtc << 19);
2194         }
2195         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2196                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2197                 bios_3_scratch |= (crtc << 23);
2198         }
2199         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2200                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2201                 bios_3_scratch |= (crtc << 25);
2202         }
2203
2204         if (rdev->family >= CHIP_R600)
2205                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2206         else
2207                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2208 }
2209
2210 void
2211 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2212 {
2213         struct drm_device *dev = encoder->dev;
2214         struct radeon_device *rdev = dev->dev_private;
2215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2216         uint32_t bios_2_scratch;
2217
2218         if (rdev->family >= CHIP_R600)
2219                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2220         else
2221                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2222
2223         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2224                 if (on)
2225                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2226                 else
2227                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2228         }
2229         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2230                 if (on)
2231                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2232                 else
2233                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2234         }
2235         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2236                 if (on)
2237                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2238                 else
2239                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2240         }
2241         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2242                 if (on)
2243                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2244                 else
2245                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2246         }
2247         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2248                 if (on)
2249                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2250                 else
2251                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2252         }
2253         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2254                 if (on)
2255                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2256                 else
2257                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2258         }
2259         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2260                 if (on)
2261                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2262                 else
2263                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2264         }
2265         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2266                 if (on)
2267                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2268                 else
2269                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2270         }
2271         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2272                 if (on)
2273                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2274                 else
2275                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2276         }
2277         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2278                 if (on)
2279                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2280                 else
2281                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2282         }
2283
2284         if (rdev->family >= CHIP_R600)
2285                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2286         else
2287                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2288 }