2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
82 gpio = &i2c_info->asGPIO_Info[i];
84 if (gpio->sucI2cId.ucAccess == id) {
85 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
86 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
87 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
88 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
89 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
90 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
91 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
92 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
93 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
94 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
95 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
96 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
97 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
98 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
99 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
100 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
102 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
103 i2c.hw_capable = true;
105 i2c.hw_capable = false;
107 if (gpio->sucI2cId.ucAccess == 0xa0)
112 i2c.i2c_id = gpio->sucI2cId.ucAccess;
123 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
126 struct atom_context *ctx = rdev->mode_info.atom_context;
127 struct radeon_gpio_rec gpio;
128 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
129 struct _ATOM_GPIO_PIN_LUT *gpio_info;
130 ATOM_GPIO_PIN_ASSIGNMENT *pin;
131 u16 data_offset, size;
134 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
137 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
138 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
140 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
141 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
143 for (i = 0; i < num_indices; i++) {
144 pin = &gpio_info->asGPIO_Pin[i];
145 if (id == pin->ucGPIO_ID) {
146 gpio.id = pin->ucGPIO_ID;
147 gpio.reg = pin->usGpioPin_AIndex * 4;
148 gpio.mask = (1 << pin->ucGpioPinBitShift);
158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
161 struct radeon_hpd hpd;
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
167 reg = AVIVO_DC_GPIO_HPD_A;
170 if (gpio->reg == reg) {
173 hpd.hpd = RADEON_HPD_1;
176 hpd.hpd = RADEON_HPD_2;
179 hpd.hpd = RADEON_HPD_3;
182 hpd.hpd = RADEON_HPD_4;
185 hpd.hpd = RADEON_HPD_5;
188 hpd.hpd = RADEON_HPD_6;
191 hpd.hpd = RADEON_HPD_NONE;
195 hpd.hpd = RADEON_HPD_NONE;
199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
202 struct radeon_i2c_bus_rec *i2c_bus,
204 struct radeon_hpd *hpd)
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
216 /* Asrock RS600 board lists the DVI port as HDMI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x1849) &&
219 (dev->pdev->subsystem_device == 0x7941)) {
220 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
221 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
222 *connector_type = DRM_MODE_CONNECTOR_DVID;
225 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
226 if ((dev->pdev->device == 0x7941) &&
227 (dev->pdev->subsystem_vendor == 0x147b) &&
228 (dev->pdev->subsystem_device == 0x2412)) {
229 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
233 /* Falcon NW laptop lists vga ddc line for LVDS */
234 if ((dev->pdev->device == 0x5653) &&
235 (dev->pdev->subsystem_vendor == 0x1462) &&
236 (dev->pdev->subsystem_device == 0x0291)) {
237 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
238 i2c_bus->valid = false;
243 /* HIS X1300 is DVI+VGA, not DVI+DVI */
244 if ((dev->pdev->device == 0x7146) &&
245 (dev->pdev->subsystem_vendor == 0x17af) &&
246 (dev->pdev->subsystem_device == 0x2058)) {
247 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
251 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
252 if ((dev->pdev->device == 0x7142) &&
253 (dev->pdev->subsystem_vendor == 0x1458) &&
254 (dev->pdev->subsystem_device == 0x2134)) {
255 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
261 if ((dev->pdev->device == 0x71C5) &&
262 (dev->pdev->subsystem_vendor == 0x106b) &&
263 (dev->pdev->subsystem_device == 0x0080)) {
264 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
265 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
269 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
270 if ((dev->pdev->device == 0x9598) &&
271 (dev->pdev->subsystem_vendor == 0x1043) &&
272 (dev->pdev->subsystem_device == 0x01da)) {
273 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
274 *connector_type = DRM_MODE_CONNECTOR_DVII;
278 /* ASUS HD 3450 board lists the DVI port as HDMI */
279 if ((dev->pdev->device == 0x95C5) &&
280 (dev->pdev->subsystem_vendor == 0x1043) &&
281 (dev->pdev->subsystem_device == 0x01e2)) {
282 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
283 *connector_type = DRM_MODE_CONNECTOR_DVII;
287 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
288 * HDMI + VGA reporting as HDMI
290 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
291 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
292 *connector_type = DRM_MODE_CONNECTOR_VGA;
297 /* Acer laptop reports DVI-D as DVI-I */
298 if ((dev->pdev->device == 0x95c4) &&
299 (dev->pdev->subsystem_vendor == 0x1025) &&
300 (dev->pdev->subsystem_device == 0x013c)) {
301 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
302 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
303 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 /* XFX Pine Group device rv730 reports no VGA DDC lines
307 * even though they are wired up to record 0x93
309 if ((dev->pdev->device == 0x9498) &&
310 (dev->pdev->subsystem_vendor == 0x1682) &&
311 (dev->pdev->subsystem_device == 0x2452)) {
312 struct radeon_device *rdev = dev->dev_private;
313 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
318 const int supported_devices_connector_convert[] = {
319 DRM_MODE_CONNECTOR_Unknown,
320 DRM_MODE_CONNECTOR_VGA,
321 DRM_MODE_CONNECTOR_DVII,
322 DRM_MODE_CONNECTOR_DVID,
323 DRM_MODE_CONNECTOR_DVIA,
324 DRM_MODE_CONNECTOR_SVIDEO,
325 DRM_MODE_CONNECTOR_Composite,
326 DRM_MODE_CONNECTOR_LVDS,
327 DRM_MODE_CONNECTOR_Unknown,
328 DRM_MODE_CONNECTOR_Unknown,
329 DRM_MODE_CONNECTOR_HDMIA,
330 DRM_MODE_CONNECTOR_HDMIB,
331 DRM_MODE_CONNECTOR_Unknown,
332 DRM_MODE_CONNECTOR_Unknown,
333 DRM_MODE_CONNECTOR_9PinDIN,
334 DRM_MODE_CONNECTOR_DisplayPort
337 const uint16_t supported_devices_connector_object_id_convert[] = {
338 CONNECTOR_OBJECT_ID_NONE,
339 CONNECTOR_OBJECT_ID_VGA,
340 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
341 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
342 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
343 CONNECTOR_OBJECT_ID_COMPOSITE,
344 CONNECTOR_OBJECT_ID_SVIDEO,
345 CONNECTOR_OBJECT_ID_LVDS,
346 CONNECTOR_OBJECT_ID_9PIN_DIN,
347 CONNECTOR_OBJECT_ID_9PIN_DIN,
348 CONNECTOR_OBJECT_ID_DISPLAYPORT,
349 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
350 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
351 CONNECTOR_OBJECT_ID_SVIDEO
354 const int object_connector_convert[] = {
355 DRM_MODE_CONNECTOR_Unknown,
356 DRM_MODE_CONNECTOR_DVII,
357 DRM_MODE_CONNECTOR_DVII,
358 DRM_MODE_CONNECTOR_DVID,
359 DRM_MODE_CONNECTOR_DVID,
360 DRM_MODE_CONNECTOR_VGA,
361 DRM_MODE_CONNECTOR_Composite,
362 DRM_MODE_CONNECTOR_SVIDEO,
363 DRM_MODE_CONNECTOR_Unknown,
364 DRM_MODE_CONNECTOR_Unknown,
365 DRM_MODE_CONNECTOR_9PinDIN,
366 DRM_MODE_CONNECTOR_Unknown,
367 DRM_MODE_CONNECTOR_HDMIA,
368 DRM_MODE_CONNECTOR_HDMIB,
369 DRM_MODE_CONNECTOR_LVDS,
370 DRM_MODE_CONNECTOR_9PinDIN,
371 DRM_MODE_CONNECTOR_Unknown,
372 DRM_MODE_CONNECTOR_Unknown,
373 DRM_MODE_CONNECTOR_Unknown,
374 DRM_MODE_CONNECTOR_DisplayPort,
375 DRM_MODE_CONNECTOR_eDP,
376 DRM_MODE_CONNECTOR_Unknown
379 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
381 struct radeon_device *rdev = dev->dev_private;
382 struct radeon_mode_info *mode_info = &rdev->mode_info;
383 struct atom_context *ctx = mode_info->atom_context;
384 int index = GetIndexIntoMasterTable(DATA, Object_Header);
385 u16 size, data_offset;
387 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
388 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
389 ATOM_OBJECT_HEADER *obj_header;
390 int i, j, path_size, device_support;
392 u16 igp_lane_info, conn_id, connector_object_id;
394 struct radeon_i2c_bus_rec ddc_bus;
395 struct radeon_gpio_rec gpio;
396 struct radeon_hpd hpd;
398 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
404 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
405 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
406 (ctx->bios + data_offset +
407 le16_to_cpu(obj_header->usDisplayPathTableOffset));
408 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
409 (ctx->bios + data_offset +
410 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
411 device_support = le16_to_cpu(obj_header->usDeviceSupport);
414 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
415 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
416 ATOM_DISPLAY_OBJECT_PATH *path;
418 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
419 path_size += le16_to_cpu(path->usSize);
421 if (device_support & le16_to_cpu(path->usDeviceTag)) {
422 uint8_t con_obj_id, con_obj_num, con_obj_type;
425 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
428 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
431 (le16_to_cpu(path->usConnObjectId) &
432 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
434 /* TODO CV support */
435 if (le16_to_cpu(path->usDeviceTag) ==
436 ATOM_DEVICE_CV_SUPPORT)
440 if ((rdev->flags & RADEON_IS_IGP) &&
442 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
443 uint16_t igp_offset = 0;
444 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
447 GetIndexIntoMasterTable(DATA,
448 IntegratedSystemInfo);
450 if (atom_parse_data_header(ctx, index, &size, &frev,
451 &crev, &igp_offset)) {
455 (ATOM_INTEGRATED_SYSTEM_INFO_V2
456 *) (ctx->bios + igp_offset);
459 uint32_t slot_config, ct;
461 if (con_obj_num == 1)
470 ct = (slot_config >> 16) & 0xff;
472 object_connector_convert
474 connector_object_id = ct;
476 slot_config & 0xffff;
484 object_connector_convert[con_obj_id];
485 connector_object_id = con_obj_id;
490 object_connector_convert[con_obj_id];
491 connector_object_id = con_obj_id;
494 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
497 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
499 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
502 (le16_to_cpu(path->usGraphicObjIds[j]) &
503 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
505 (le16_to_cpu(path->usGraphicObjIds[j]) &
506 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
508 (le16_to_cpu(path->usGraphicObjIds[j]) &
509 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
511 /* FIXME: add support for router objects */
512 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
513 if (enc_obj_num == 2)
518 radeon_add_atom_encoder(dev,
527 /* look up gpio for ddc, hpd */
528 if ((le16_to_cpu(path->usDeviceTag) &
529 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
530 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
531 if (le16_to_cpu(path->usConnObjectId) ==
532 le16_to_cpu(con_obj->asObjects[j].
534 ATOM_COMMON_RECORD_HEADER
536 (ATOM_COMMON_RECORD_HEADER
538 (ctx->bios + data_offset +
539 le16_to_cpu(con_obj->
542 ATOM_I2C_RECORD *i2c_record;
543 ATOM_HPD_INT_RECORD *hpd_record;
544 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
545 hpd.hpd = RADEON_HPD_NONE;
547 while (record->ucRecordType > 0
550 ATOM_MAX_OBJECT_RECORD_NUMBER) {
551 switch (record->ucRecordType) {
552 case ATOM_I2C_RECORD_TYPE:
557 (ATOM_I2C_ID_CONFIG_ACCESS *)
558 &i2c_record->sucI2cId;
559 ddc_bus = radeon_lookup_i2c_gpio(rdev,
563 case ATOM_HPD_INT_RECORD_TYPE:
565 (ATOM_HPD_INT_RECORD *)
567 gpio = radeon_lookup_gpio(rdev,
568 hpd_record->ucHPDIntGPIOID);
569 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
570 hpd.plugged_state = hpd_record->ucPlugged_PinState;
574 (ATOM_COMMON_RECORD_HEADER
584 hpd.hpd = RADEON_HPD_NONE;
585 ddc_bus.valid = false;
588 /* needed for aux chan transactions */
589 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
591 conn_id = le16_to_cpu(path->usConnObjectId);
593 if (!radeon_atom_apply_quirks
594 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
595 &ddc_bus, &conn_id, &hpd))
598 radeon_add_atom_connector(dev,
602 connector_type, &ddc_bus,
603 linkb, igp_lane_info,
610 radeon_link_encoder_connector(dev);
615 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
619 struct radeon_device *rdev = dev->dev_private;
621 if (rdev->flags & RADEON_IS_IGP) {
622 return supported_devices_connector_object_id_convert
624 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
625 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
626 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
627 struct radeon_mode_info *mode_info = &rdev->mode_info;
628 struct atom_context *ctx = mode_info->atom_context;
629 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
630 uint16_t size, data_offset;
632 ATOM_XTMDS_INFO *xtmds;
634 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
635 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
637 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
638 if (connector_type == DRM_MODE_CONNECTOR_DVII)
639 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
641 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
643 if (connector_type == DRM_MODE_CONNECTOR_DVII)
644 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
646 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
649 return supported_devices_connector_object_id_convert
652 return supported_devices_connector_object_id_convert
657 struct bios_connector {
662 struct radeon_i2c_bus_rec ddc_bus;
663 struct radeon_hpd hpd;
666 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
670 struct radeon_device *rdev = dev->dev_private;
671 struct radeon_mode_info *mode_info = &rdev->mode_info;
672 struct atom_context *ctx = mode_info->atom_context;
673 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
674 uint16_t size, data_offset;
676 uint16_t device_support;
678 union atom_supported_devices *supported_devices;
679 int i, j, max_device;
680 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
682 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
686 (union atom_supported_devices *)(ctx->bios + data_offset);
688 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
691 max_device = ATOM_MAX_SUPPORTED_DEVICE;
693 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
695 for (i = 0; i < max_device; i++) {
696 ATOM_CONNECTOR_INFO_I2C ci =
697 supported_devices->info.asConnInfo[i];
699 bios_connectors[i].valid = false;
701 if (!(device_support & (1 << i))) {
705 if (i == ATOM_DEVICE_CV_INDEX) {
706 DRM_DEBUG("Skipping Component Video\n");
710 bios_connectors[i].connector_type =
711 supported_devices_connector_convert[ci.sucConnectorInfo.
715 if (bios_connectors[i].connector_type ==
716 DRM_MODE_CONNECTOR_Unknown)
719 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
721 bios_connectors[i].line_mux =
722 ci.sucI2cId.ucAccess;
724 /* give tv unique connector ids */
725 if (i == ATOM_DEVICE_TV1_INDEX) {
726 bios_connectors[i].ddc_bus.valid = false;
727 bios_connectors[i].line_mux = 50;
728 } else if (i == ATOM_DEVICE_TV2_INDEX) {
729 bios_connectors[i].ddc_bus.valid = false;
730 bios_connectors[i].line_mux = 51;
731 } else if (i == ATOM_DEVICE_CV_INDEX) {
732 bios_connectors[i].ddc_bus.valid = false;
733 bios_connectors[i].line_mux = 52;
735 bios_connectors[i].ddc_bus =
736 radeon_lookup_i2c_gpio(rdev,
737 bios_connectors[i].line_mux);
739 if ((crev > 1) && (frev > 1)) {
740 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
743 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
746 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
749 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
753 if (i == ATOM_DEVICE_DFP1_INDEX)
754 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
755 else if (i == ATOM_DEVICE_DFP2_INDEX)
756 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
758 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
761 /* Always set the connector type to VGA for CRT1/CRT2. if they are
762 * shared with a DVI port, we'll pick up the DVI connector when we
763 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
765 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
766 bios_connectors[i].connector_type =
767 DRM_MODE_CONNECTOR_VGA;
769 if (!radeon_atom_apply_quirks
770 (dev, (1 << i), &bios_connectors[i].connector_type,
771 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
772 &bios_connectors[i].hpd))
775 bios_connectors[i].valid = true;
776 bios_connectors[i].devices = (1 << i);
778 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
779 radeon_add_atom_encoder(dev,
780 radeon_get_encoder_id(dev,
785 radeon_add_legacy_encoder(dev,
786 radeon_get_encoder_id(dev,
792 /* combine shared connectors */
793 for (i = 0; i < max_device; i++) {
794 if (bios_connectors[i].valid) {
795 for (j = 0; j < max_device; j++) {
796 if (bios_connectors[j].valid && (i != j)) {
797 if (bios_connectors[i].line_mux ==
798 bios_connectors[j].line_mux) {
799 /* make sure not to combine LVDS */
800 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
801 bios_connectors[i].line_mux = 53;
802 bios_connectors[i].ddc_bus.valid = false;
805 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
806 bios_connectors[j].line_mux = 53;
807 bios_connectors[j].ddc_bus.valid = false;
810 /* combine analog and digital for DVI-I */
811 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
812 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
813 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
814 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
815 bios_connectors[i].devices |=
816 bios_connectors[j].devices;
817 bios_connectors[i].connector_type =
818 DRM_MODE_CONNECTOR_DVII;
819 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
820 bios_connectors[i].hpd =
821 bios_connectors[j].hpd;
822 bios_connectors[j].valid = false;
830 /* add the connectors */
831 for (i = 0; i < max_device; i++) {
832 if (bios_connectors[i].valid) {
833 uint16_t connector_object_id =
834 atombios_get_connector_object_id(dev,
835 bios_connectors[i].connector_type,
836 bios_connectors[i].devices);
837 radeon_add_atom_connector(dev,
838 bios_connectors[i].line_mux,
839 bios_connectors[i].devices,
842 &bios_connectors[i].ddc_bus,
845 &bios_connectors[i].hpd);
849 radeon_link_encoder_connector(dev);
854 union firmware_info {
855 ATOM_FIRMWARE_INFO info;
856 ATOM_FIRMWARE_INFO_V1_2 info_12;
857 ATOM_FIRMWARE_INFO_V1_3 info_13;
858 ATOM_FIRMWARE_INFO_V1_4 info_14;
859 ATOM_FIRMWARE_INFO_V2_1 info_21;
862 bool radeon_atom_get_clock_info(struct drm_device *dev)
864 struct radeon_device *rdev = dev->dev_private;
865 struct radeon_mode_info *mode_info = &rdev->mode_info;
866 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
867 union firmware_info *firmware_info;
869 struct radeon_pll *p1pll = &rdev->clock.p1pll;
870 struct radeon_pll *p2pll = &rdev->clock.p2pll;
871 struct radeon_pll *dcpll = &rdev->clock.dcpll;
872 struct radeon_pll *spll = &rdev->clock.spll;
873 struct radeon_pll *mpll = &rdev->clock.mpll;
874 uint16_t data_offset;
876 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
877 &frev, &crev, &data_offset)) {
879 (union firmware_info *)(mode_info->atom_context->bios +
882 p1pll->reference_freq =
883 le16_to_cpu(firmware_info->info.usReferenceClock);
884 p1pll->reference_div = 0;
888 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
891 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
893 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
896 p1pll->lcd_pll_out_min =
897 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
898 if (p1pll->lcd_pll_out_min == 0)
899 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
900 p1pll->lcd_pll_out_max =
901 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
902 if (p1pll->lcd_pll_out_max == 0)
903 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
905 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
906 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
909 if (p1pll->pll_out_min == 0) {
910 if (ASIC_IS_AVIVO(rdev))
911 p1pll->pll_out_min = 64800;
913 p1pll->pll_out_min = 20000;
914 } else if (p1pll->pll_out_min > 64800) {
915 /* Limiting the pll output range is a good thing generally as
916 * it limits the number of possible pll combinations for a given
917 * frequency presumably to the ones that work best on each card.
918 * However, certain duallink DVI monitors seem to like
919 * pll combinations that would be limited by this at least on
920 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
924 p1pll->pll_out_min = 64800;
928 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
930 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
935 spll->reference_freq =
936 le16_to_cpu(firmware_info->info.usReferenceClock);
937 spll->reference_div = 0;
940 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
942 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
945 if (spll->pll_out_min == 0) {
946 if (ASIC_IS_AVIVO(rdev))
947 spll->pll_out_min = 64800;
949 spll->pll_out_min = 20000;
953 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
955 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
958 mpll->reference_freq =
959 le16_to_cpu(firmware_info->info.usReferenceClock);
960 mpll->reference_div = 0;
963 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
965 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
968 if (mpll->pll_out_min == 0) {
969 if (ASIC_IS_AVIVO(rdev))
970 mpll->pll_out_min = 64800;
972 mpll->pll_out_min = 20000;
976 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
978 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
980 rdev->clock.default_sclk =
981 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
982 rdev->clock.default_mclk =
983 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
985 if (ASIC_IS_DCE4(rdev)) {
986 rdev->clock.default_dispclk =
987 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
988 if (rdev->clock.default_dispclk == 0)
989 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
990 rdev->clock.dp_extclk =
991 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1002 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1003 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1006 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1008 struct radeon_mode_info *mode_info = &rdev->mode_info;
1009 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1010 union igp_info *igp_info;
1014 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1015 &frev, &crev, &data_offset)) {
1016 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1020 if (igp_info->info.ucMemoryType & 0xf0)
1024 if (igp_info->info_2.ucMemoryType & 0x0f)
1028 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1035 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1036 struct radeon_encoder_int_tmds *tmds)
1038 struct drm_device *dev = encoder->base.dev;
1039 struct radeon_device *rdev = dev->dev_private;
1040 struct radeon_mode_info *mode_info = &rdev->mode_info;
1041 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1042 uint16_t data_offset;
1043 struct _ATOM_TMDS_INFO *tmds_info;
1048 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1049 &frev, &crev, &data_offset)) {
1051 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1054 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1055 for (i = 0; i < 4; i++) {
1056 tmds->tmds_pll[i].freq =
1057 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1058 tmds->tmds_pll[i].value =
1059 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1060 tmds->tmds_pll[i].value |=
1061 (tmds_info->asMiscInfo[i].
1062 ucPLL_VCO_Gain & 0x3f) << 6;
1063 tmds->tmds_pll[i].value |=
1064 (tmds_info->asMiscInfo[i].
1065 ucPLL_DutyCycle & 0xf) << 12;
1066 tmds->tmds_pll[i].value |=
1067 (tmds_info->asMiscInfo[i].
1068 ucPLL_VoltageSwing & 0xf) << 16;
1070 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1071 tmds->tmds_pll[i].freq,
1072 tmds->tmds_pll[i].value);
1074 if (maxfreq == tmds->tmds_pll[i].freq) {
1075 tmds->tmds_pll[i].freq = 0xffffffff;
1084 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1089 struct drm_device *dev = encoder->base.dev;
1090 struct radeon_device *rdev = dev->dev_private;
1091 struct radeon_mode_info *mode_info = &rdev->mode_info;
1092 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1093 uint16_t data_offset;
1094 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1096 struct radeon_atom_ss *ss = NULL;
1099 if (id > ATOM_MAX_SS_ENTRY)
1102 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1103 &frev, &crev, &data_offset)) {
1105 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1108 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1113 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1114 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1116 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1117 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1118 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1119 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1120 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1121 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1130 struct _ATOM_LVDS_INFO info;
1131 struct _ATOM_LVDS_INFO_V12 info_12;
1134 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1138 struct drm_device *dev = encoder->base.dev;
1139 struct radeon_device *rdev = dev->dev_private;
1140 struct radeon_mode_info *mode_info = &rdev->mode_info;
1141 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1142 uint16_t data_offset, misc;
1143 union lvds_info *lvds_info;
1145 struct radeon_encoder_atom_dig *lvds = NULL;
1147 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1148 &frev, &crev, &data_offset)) {
1150 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1152 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1157 lvds->native_mode.clock =
1158 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1159 lvds->native_mode.hdisplay =
1160 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1161 lvds->native_mode.vdisplay =
1162 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1163 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1164 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1165 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1166 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1167 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1168 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1169 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1170 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1171 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1172 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1173 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1174 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1175 lvds->panel_pwr_delay =
1176 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1177 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1179 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1180 if (misc & ATOM_VSYNC_POLARITY)
1181 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1182 if (misc & ATOM_HSYNC_POLARITY)
1183 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1184 if (misc & ATOM_COMPOSITESYNC)
1185 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1186 if (misc & ATOM_INTERLACE)
1187 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1188 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1189 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1191 /* set crtc values */
1192 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1194 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1196 if (ASIC_IS_AVIVO(rdev)) {
1197 if (radeon_new_pll == 0)
1198 lvds->pll_algo = PLL_ALGO_LEGACY;
1200 lvds->pll_algo = PLL_ALGO_NEW;
1202 if (radeon_new_pll == 1)
1203 lvds->pll_algo = PLL_ALGO_NEW;
1205 lvds->pll_algo = PLL_ALGO_LEGACY;
1208 encoder->native_mode = lvds->native_mode;
1213 struct radeon_encoder_primary_dac *
1214 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1216 struct drm_device *dev = encoder->base.dev;
1217 struct radeon_device *rdev = dev->dev_private;
1218 struct radeon_mode_info *mode_info = &rdev->mode_info;
1219 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1220 uint16_t data_offset;
1221 struct _COMPASSIONATE_DATA *dac_info;
1224 struct radeon_encoder_primary_dac *p_dac = NULL;
1226 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1227 &frev, &crev, &data_offset)) {
1228 dac_info = (struct _COMPASSIONATE_DATA *)
1229 (mode_info->atom_context->bios + data_offset);
1231 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1236 bg = dac_info->ucDAC1_BG_Adjustment;
1237 dac = dac_info->ucDAC1_DAC_Adjustment;
1238 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1244 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1245 struct drm_display_mode *mode)
1247 struct radeon_mode_info *mode_info = &rdev->mode_info;
1248 ATOM_ANALOG_TV_INFO *tv_info;
1249 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1250 ATOM_DTD_FORMAT *dtd_timings;
1251 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1253 u16 data_offset, misc;
1255 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1256 &frev, &crev, &data_offset))
1261 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1262 if (index > MAX_SUPPORTED_TV_TIMING)
1265 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1266 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1267 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1268 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1269 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1271 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1272 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1273 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1274 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1275 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1278 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1279 if (misc & ATOM_VSYNC_POLARITY)
1280 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1281 if (misc & ATOM_HSYNC_POLARITY)
1282 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1283 if (misc & ATOM_COMPOSITESYNC)
1284 mode->flags |= DRM_MODE_FLAG_CSYNC;
1285 if (misc & ATOM_INTERLACE)
1286 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1287 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1288 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1290 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1293 /* PAL timings appear to have wrong values for totals */
1294 mode->crtc_htotal -= 1;
1295 mode->crtc_vtotal -= 1;
1299 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1300 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1303 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1304 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1305 le16_to_cpu(dtd_timings->usHBlanking_Time);
1306 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1307 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1308 le16_to_cpu(dtd_timings->usHSyncOffset);
1309 mode->crtc_hsync_end = mode->crtc_hsync_start +
1310 le16_to_cpu(dtd_timings->usHSyncWidth);
1312 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1313 le16_to_cpu(dtd_timings->usVBlanking_Time);
1314 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1315 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1316 le16_to_cpu(dtd_timings->usVSyncOffset);
1317 mode->crtc_vsync_end = mode->crtc_vsync_start +
1318 le16_to_cpu(dtd_timings->usVSyncWidth);
1321 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1322 if (misc & ATOM_VSYNC_POLARITY)
1323 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1324 if (misc & ATOM_HSYNC_POLARITY)
1325 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1326 if (misc & ATOM_COMPOSITESYNC)
1327 mode->flags |= DRM_MODE_FLAG_CSYNC;
1328 if (misc & ATOM_INTERLACE)
1329 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1330 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1331 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1333 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1340 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1342 struct radeon_mode_info *mode_info = &rdev->mode_info;
1343 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1344 uint16_t data_offset;
1346 struct _ATOM_ANALOG_TV_INFO *tv_info;
1347 enum radeon_tv_std tv_std = TV_STD_NTSC;
1349 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1350 &frev, &crev, &data_offset)) {
1352 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1353 (mode_info->atom_context->bios + data_offset);
1355 switch (tv_info->ucTV_BootUpDefaultStandard) {
1357 tv_std = TV_STD_NTSC;
1358 DRM_INFO("Default TV standard: NTSC\n");
1361 tv_std = TV_STD_NTSC_J;
1362 DRM_INFO("Default TV standard: NTSC-J\n");
1365 tv_std = TV_STD_PAL;
1366 DRM_INFO("Default TV standard: PAL\n");
1369 tv_std = TV_STD_PAL_M;
1370 DRM_INFO("Default TV standard: PAL-M\n");
1373 tv_std = TV_STD_PAL_N;
1374 DRM_INFO("Default TV standard: PAL-N\n");
1377 tv_std = TV_STD_PAL_CN;
1378 DRM_INFO("Default TV standard: PAL-CN\n");
1381 tv_std = TV_STD_PAL_60;
1382 DRM_INFO("Default TV standard: PAL-60\n");
1385 tv_std = TV_STD_SECAM;
1386 DRM_INFO("Default TV standard: SECAM\n");
1389 tv_std = TV_STD_NTSC;
1390 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1397 struct radeon_encoder_tv_dac *
1398 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1400 struct drm_device *dev = encoder->base.dev;
1401 struct radeon_device *rdev = dev->dev_private;
1402 struct radeon_mode_info *mode_info = &rdev->mode_info;
1403 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1404 uint16_t data_offset;
1405 struct _COMPASSIONATE_DATA *dac_info;
1408 struct radeon_encoder_tv_dac *tv_dac = NULL;
1410 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1411 &frev, &crev, &data_offset)) {
1413 dac_info = (struct _COMPASSIONATE_DATA *)
1414 (mode_info->atom_context->bios + data_offset);
1416 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1421 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1422 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1423 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1425 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1426 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1427 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1429 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1430 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1431 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1433 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1438 static const char *thermal_controller_names[] = {
1449 static const char *pp_lib_thermal_controller_names[] = {
1463 struct _ATOM_POWERPLAY_INFO info;
1464 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1465 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1466 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1469 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1471 struct radeon_mode_info *mode_info = &rdev->mode_info;
1472 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1475 u32 misc, misc2 = 0, sclk, mclk;
1476 union power_info *power_info;
1477 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1478 struct _ATOM_PPLIB_STATE *power_state;
1479 int num_modes = 0, i, j;
1480 int state_index = 0, mode_index = 0;
1481 struct radeon_i2c_bus_rec i2c_bus;
1483 rdev->pm.default_power_state = NULL;
1485 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1486 &frev, &crev, &data_offset)) {
1487 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1489 /* add the i2c bus for thermal/fan chip */
1490 if (power_info->info.ucOverdriveThermalController > 0) {
1491 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1492 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1493 power_info->info.ucOverdriveControllerAddress >> 1);
1494 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1495 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1497 num_modes = power_info->info.ucNumOfPowerModeEntries;
1498 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1499 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1500 for (i = 0; i < num_modes; i++) {
1501 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1504 rdev->pm.power_state[state_index].num_clock_modes = 1;
1505 rdev->pm.power_state[state_index].clock_info[0].mclk =
1506 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1507 rdev->pm.power_state[state_index].clock_info[0].sclk =
1508 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1509 /* skip invalid modes */
1510 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1511 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1513 /* skip overclock modes for now */
1514 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1515 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1516 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1517 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1519 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1520 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1521 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1522 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1523 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1525 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1526 radeon_lookup_gpio(rdev,
1527 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1528 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1529 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1532 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1534 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1535 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1537 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1538 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1540 /* order matters! */
1541 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1542 rdev->pm.power_state[state_index].type =
1543 POWER_STATE_TYPE_POWERSAVE;
1544 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1545 rdev->pm.power_state[state_index].type =
1546 POWER_STATE_TYPE_BATTERY;
1547 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1548 rdev->pm.power_state[state_index].type =
1549 POWER_STATE_TYPE_BATTERY;
1550 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1551 rdev->pm.power_state[state_index].type =
1552 POWER_STATE_TYPE_BALANCED;
1553 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1554 rdev->pm.power_state[state_index].type =
1555 POWER_STATE_TYPE_PERFORMANCE;
1556 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1557 rdev->pm.power_state[state_index].type =
1558 POWER_STATE_TYPE_DEFAULT;
1559 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1560 rdev->pm.power_state[state_index].default_clock_mode =
1561 &rdev->pm.power_state[state_index].clock_info[0];
1566 rdev->pm.power_state[state_index].num_clock_modes = 1;
1567 rdev->pm.power_state[state_index].clock_info[0].mclk =
1568 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1569 rdev->pm.power_state[state_index].clock_info[0].sclk =
1570 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1571 /* skip invalid modes */
1572 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1573 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1575 /* skip overclock modes for now */
1576 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1577 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1578 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1579 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1581 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1582 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1583 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1584 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1585 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1586 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1588 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1589 radeon_lookup_gpio(rdev,
1590 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1591 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1592 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1595 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1597 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1598 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1600 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1601 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1603 /* order matters! */
1604 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1605 rdev->pm.power_state[state_index].type =
1606 POWER_STATE_TYPE_POWERSAVE;
1607 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1608 rdev->pm.power_state[state_index].type =
1609 POWER_STATE_TYPE_BATTERY;
1610 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1611 rdev->pm.power_state[state_index].type =
1612 POWER_STATE_TYPE_BATTERY;
1613 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1614 rdev->pm.power_state[state_index].type =
1615 POWER_STATE_TYPE_BALANCED;
1616 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1617 rdev->pm.power_state[state_index].type =
1618 POWER_STATE_TYPE_PERFORMANCE;
1619 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1620 rdev->pm.power_state[state_index].type =
1621 POWER_STATE_TYPE_BALANCED;
1622 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1623 rdev->pm.power_state[state_index].type =
1624 POWER_STATE_TYPE_DEFAULT;
1625 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1626 rdev->pm.power_state[state_index].default_clock_mode =
1627 &rdev->pm.power_state[state_index].clock_info[0];
1632 rdev->pm.power_state[state_index].num_clock_modes = 1;
1633 rdev->pm.power_state[state_index].clock_info[0].mclk =
1634 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1635 rdev->pm.power_state[state_index].clock_info[0].sclk =
1636 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1637 /* skip invalid modes */
1638 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1639 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1641 /* skip overclock modes for now */
1642 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1643 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1644 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1645 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1647 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1648 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1649 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1650 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1651 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1652 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1654 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1655 radeon_lookup_gpio(rdev,
1656 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1657 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1658 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1661 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1663 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1664 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1666 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1667 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1668 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1669 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1671 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1672 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1675 /* order matters! */
1676 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1677 rdev->pm.power_state[state_index].type =
1678 POWER_STATE_TYPE_POWERSAVE;
1679 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1680 rdev->pm.power_state[state_index].type =
1681 POWER_STATE_TYPE_BATTERY;
1682 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1683 rdev->pm.power_state[state_index].type =
1684 POWER_STATE_TYPE_BATTERY;
1685 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1686 rdev->pm.power_state[state_index].type =
1687 POWER_STATE_TYPE_BALANCED;
1688 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1689 rdev->pm.power_state[state_index].type =
1690 POWER_STATE_TYPE_PERFORMANCE;
1691 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1692 rdev->pm.power_state[state_index].type =
1693 POWER_STATE_TYPE_BALANCED;
1694 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1695 rdev->pm.power_state[state_index].type =
1696 POWER_STATE_TYPE_DEFAULT;
1697 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1698 rdev->pm.power_state[state_index].default_clock_mode =
1699 &rdev->pm.power_state[state_index].clock_info[0];
1705 } else if (frev == 4) {
1706 /* add the i2c bus for thermal/fan chip */
1707 /* no support for internal controller yet */
1708 if (power_info->info_4.sThermalController.ucType > 0) {
1709 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1710 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1711 DRM_INFO("Internal thermal controller %s fan control\n",
1712 (power_info->info_4.sThermalController.ucFanParameters &
1713 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1715 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1716 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1717 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1718 (power_info->info_4.sThermalController.ucFanParameters &
1719 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1720 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1721 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1724 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1726 power_state = (struct _ATOM_PPLIB_STATE *)
1727 (mode_info->atom_context->bios +
1729 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1730 i * power_info->info_4.ucStateEntrySize);
1731 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1732 (mode_info->atom_context->bios +
1734 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1735 (power_state->ucNonClockStateIndex *
1736 power_info->info_4.ucNonClockSize));
1737 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1738 if (rdev->flags & RADEON_IS_IGP) {
1739 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1740 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1741 (mode_info->atom_context->bios +
1743 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1744 (power_state->ucClockStateIndices[j] *
1745 power_info->info_4.ucClockInfoSize));
1746 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1747 sclk |= clock_info->ucLowEngineClockHigh << 16;
1748 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1749 /* skip invalid modes */
1750 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1752 /* skip overclock modes for now */
1753 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1754 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1756 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1758 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1762 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1763 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1764 (mode_info->atom_context->bios +
1766 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1767 (power_state->ucClockStateIndices[j] *
1768 power_info->info_4.ucClockInfoSize));
1769 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1770 sclk |= clock_info->ucEngineClockHigh << 16;
1771 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1772 mclk |= clock_info->ucMemoryClockHigh << 16;
1773 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1774 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1775 /* skip invalid modes */
1776 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1777 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1779 /* skip overclock modes for now */
1780 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1781 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1782 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1783 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1785 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1787 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1792 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1794 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1795 misc2 = le16_to_cpu(non_clock_info->usClassification);
1796 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1797 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1798 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1799 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1800 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1801 rdev->pm.power_state[state_index].type =
1802 POWER_STATE_TYPE_BATTERY;
1804 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1805 rdev->pm.power_state[state_index].type =
1806 POWER_STATE_TYPE_BALANCED;
1808 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1809 rdev->pm.power_state[state_index].type =
1810 POWER_STATE_TYPE_PERFORMANCE;
1813 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1814 rdev->pm.power_state[state_index].type =
1815 POWER_STATE_TYPE_DEFAULT;
1816 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1817 rdev->pm.power_state[state_index].default_clock_mode =
1818 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1825 /* XXX figure out some good default low power mode for cards w/out power tables */
1828 if (rdev->pm.default_power_state == NULL) {
1829 /* add the default mode */
1830 rdev->pm.power_state[state_index].type =
1831 POWER_STATE_TYPE_DEFAULT;
1832 rdev->pm.power_state[state_index].num_clock_modes = 1;
1833 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1834 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1835 rdev->pm.power_state[state_index].default_clock_mode =
1836 &rdev->pm.power_state[state_index].clock_info[0];
1837 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1838 if (rdev->asic->get_pcie_lanes)
1839 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1841 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1842 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1845 rdev->pm.num_power_states = state_index;
1847 rdev->pm.current_power_state = rdev->pm.default_power_state;
1848 rdev->pm.current_clock_mode =
1849 rdev->pm.default_power_state->default_clock_mode;
1852 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1854 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1855 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1857 args.ucEnable = enable;
1859 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1862 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1864 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1865 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1867 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1868 return args.ulReturnEngineClock;
1871 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1873 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1874 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1877 return args.ulReturnMemoryClock;
1880 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1883 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1884 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1886 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1888 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1891 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1894 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1895 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1897 if (rdev->flags & RADEON_IS_IGP)
1900 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1902 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1905 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1907 struct radeon_device *rdev = dev->dev_private;
1908 uint32_t bios_2_scratch, bios_6_scratch;
1910 if (rdev->family >= CHIP_R600) {
1911 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1912 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1914 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1915 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1918 /* let the bios control the backlight */
1919 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1921 /* tell the bios not to handle mode switching */
1922 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1924 if (rdev->family >= CHIP_R600) {
1925 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1926 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1928 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1929 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1934 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1936 uint32_t scratch_reg;
1939 if (rdev->family >= CHIP_R600)
1940 scratch_reg = R600_BIOS_0_SCRATCH;
1942 scratch_reg = RADEON_BIOS_0_SCRATCH;
1944 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1945 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1948 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1950 uint32_t scratch_reg;
1953 if (rdev->family >= CHIP_R600)
1954 scratch_reg = R600_BIOS_0_SCRATCH;
1956 scratch_reg = RADEON_BIOS_0_SCRATCH;
1958 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1959 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1962 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1964 struct drm_device *dev = encoder->dev;
1965 struct radeon_device *rdev = dev->dev_private;
1966 uint32_t bios_6_scratch;
1968 if (rdev->family >= CHIP_R600)
1969 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1971 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1974 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1976 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1978 if (rdev->family >= CHIP_R600)
1979 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1981 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1984 /* at some point we may want to break this out into individual functions */
1986 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1987 struct drm_encoder *encoder,
1990 struct drm_device *dev = connector->dev;
1991 struct radeon_device *rdev = dev->dev_private;
1992 struct radeon_connector *radeon_connector =
1993 to_radeon_connector(connector);
1994 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1995 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1997 if (rdev->family >= CHIP_R600) {
1998 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1999 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2000 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2002 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2003 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2004 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2007 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2008 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2010 DRM_DEBUG("TV1 connected\n");
2011 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2012 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2014 DRM_DEBUG("TV1 disconnected\n");
2015 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2016 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2017 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2020 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2021 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2023 DRM_DEBUG("CV connected\n");
2024 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2025 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2027 DRM_DEBUG("CV disconnected\n");
2028 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2029 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2030 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2033 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2034 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2036 DRM_DEBUG("LCD1 connected\n");
2037 bios_0_scratch |= ATOM_S0_LCD1;
2038 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2039 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2041 DRM_DEBUG("LCD1 disconnected\n");
2042 bios_0_scratch &= ~ATOM_S0_LCD1;
2043 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2044 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2047 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2048 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2050 DRM_DEBUG("CRT1 connected\n");
2051 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2052 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2053 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2055 DRM_DEBUG("CRT1 disconnected\n");
2056 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2057 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2058 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2061 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2062 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2064 DRM_DEBUG("CRT2 connected\n");
2065 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2066 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2067 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2069 DRM_DEBUG("CRT2 disconnected\n");
2070 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2071 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2072 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2075 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2076 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2078 DRM_DEBUG("DFP1 connected\n");
2079 bios_0_scratch |= ATOM_S0_DFP1;
2080 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2081 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2083 DRM_DEBUG("DFP1 disconnected\n");
2084 bios_0_scratch &= ~ATOM_S0_DFP1;
2085 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2086 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2089 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2090 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2092 DRM_DEBUG("DFP2 connected\n");
2093 bios_0_scratch |= ATOM_S0_DFP2;
2094 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2095 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2097 DRM_DEBUG("DFP2 disconnected\n");
2098 bios_0_scratch &= ~ATOM_S0_DFP2;
2099 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2100 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2103 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2104 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2106 DRM_DEBUG("DFP3 connected\n");
2107 bios_0_scratch |= ATOM_S0_DFP3;
2108 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2109 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2111 DRM_DEBUG("DFP3 disconnected\n");
2112 bios_0_scratch &= ~ATOM_S0_DFP3;
2113 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2114 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2117 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2118 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2120 DRM_DEBUG("DFP4 connected\n");
2121 bios_0_scratch |= ATOM_S0_DFP4;
2122 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2123 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2125 DRM_DEBUG("DFP4 disconnected\n");
2126 bios_0_scratch &= ~ATOM_S0_DFP4;
2127 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2128 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2131 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2132 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2134 DRM_DEBUG("DFP5 connected\n");
2135 bios_0_scratch |= ATOM_S0_DFP5;
2136 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2137 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2139 DRM_DEBUG("DFP5 disconnected\n");
2140 bios_0_scratch &= ~ATOM_S0_DFP5;
2141 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2142 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2146 if (rdev->family >= CHIP_R600) {
2147 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2148 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2149 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2151 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2152 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2153 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2158 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2160 struct drm_device *dev = encoder->dev;
2161 struct radeon_device *rdev = dev->dev_private;
2162 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2163 uint32_t bios_3_scratch;
2165 if (rdev->family >= CHIP_R600)
2166 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2168 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2170 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2171 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2172 bios_3_scratch |= (crtc << 18);
2174 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2175 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2176 bios_3_scratch |= (crtc << 24);
2178 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2179 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2180 bios_3_scratch |= (crtc << 16);
2182 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2183 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2184 bios_3_scratch |= (crtc << 20);
2186 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2187 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2188 bios_3_scratch |= (crtc << 17);
2190 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2191 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2192 bios_3_scratch |= (crtc << 19);
2194 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2195 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2196 bios_3_scratch |= (crtc << 23);
2198 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2199 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2200 bios_3_scratch |= (crtc << 25);
2203 if (rdev->family >= CHIP_R600)
2204 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2206 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2210 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2212 struct drm_device *dev = encoder->dev;
2213 struct radeon_device *rdev = dev->dev_private;
2214 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2215 uint32_t bios_2_scratch;
2217 if (rdev->family >= CHIP_R600)
2218 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2220 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2222 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2224 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2226 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2228 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2230 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2232 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2234 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2236 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2238 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2240 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2242 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2244 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2246 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2248 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2250 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2252 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2254 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2256 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2258 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2260 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2262 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2264 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2266 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2268 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2270 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2272 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2274 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2276 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2278 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2280 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2283 if (rdev->family >= CHIP_R600)
2284 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2286 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);