SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                         break;
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 125                                                         u8 id)
 126 {
 127         struct atom_context *ctx = rdev->mode_info.atom_context;
 128         struct radeon_gpio_rec gpio;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 130         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 131         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 132         u16 data_offset, size;
 133         int i, num_indices;
 134
 135         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 136         gpio.valid = false;
 137
 138         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 139
 140         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 141
 142         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 143
 144         for (i = 0; i < num_indices; i++) {
 145                 pin = &gpio_info->asGPIO_Pin[i];
 146                 if (id == pin->ucGPIO_ID) {
 147                         gpio.id = pin->ucGPIO_ID;
 148                         gpio.reg = pin->usGpioPin_AIndex * 4;
 149                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 150                         gpio.valid = true;
 151                         break;
 152                 }
 153         }
 154
 155         return gpio;
 156 }
 157
 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 159                                                             struct radeon_gpio_rec *gpio)
 160 {
 161         struct radeon_hpd hpd;
 162         u32 reg;
 163
 164         if (ASIC_IS_DCE4(rdev))
 165                 reg = EVERGREEN_DC_GPIO_HPD_A;
 166         else
 167                 reg = AVIVO_DC_GPIO_HPD_A;
 168
 169         hpd.gpio = *gpio;
 170         if (gpio->reg == reg) {
 171                 switch(gpio->mask) {
 172                 case (1 << 0):
 173                         hpd.hpd = RADEON_HPD_1;
 174                         break;
 175                 case (1 << 8):
 176                         hpd.hpd = RADEON_HPD_2;
 177                         break;
 178                 case (1 << 16):
 179                         hpd.hpd = RADEON_HPD_3;
 180                         break;
 181                 case (1 << 24):
 182                         hpd.hpd = RADEON_HPD_4;
 183                         break;
 184                 case (1 << 26):
 185                         hpd.hpd = RADEON_HPD_5;
 186                         break;
 187                 case (1 << 28):
 188                         hpd.hpd = RADEON_HPD_6;
 189                         break;
 190                 default:
 191                         hpd.hpd = RADEON_HPD_NONE;
 192                         break;
 193                 }
 194         } else
 195                 hpd.hpd = RADEON_HPD_NONE;
 196         return hpd;
 197 }
 198
 199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 200                                      uint32_t supported_device,
 201                                      int *connector_type,
 202                                      struct radeon_i2c_bus_rec *i2c_bus,
 203                                      uint16_t *line_mux,
 204                                      struct radeon_hpd *hpd)
 205 {
 206
 207         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 208         if ((dev->pdev->device == 0x791e) &&
 209             (dev->pdev->subsystem_vendor == 0x1043) &&
 210             (dev->pdev->subsystem_device == 0x826d)) {
 211                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 212                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 213                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 214         }
 215
 216         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 217         if ((dev->pdev->device == 0x7941) &&
 218             (dev->pdev->subsystem_vendor == 0x147b) &&
 219             (dev->pdev->subsystem_device == 0x2412)) {
 220                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 221                         return false;
 222         }
 223
 224         /* Falcon NW laptop lists vga ddc line for LVDS */
 225         if ((dev->pdev->device == 0x5653) &&
 226             (dev->pdev->subsystem_vendor == 0x1462) &&
 227             (dev->pdev->subsystem_device == 0x0291)) {
 228                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 229                         i2c_bus->valid = false;
 230                         *line_mux = 53;
 231                 }
 232         }
 233
 234         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 235         if ((dev->pdev->device == 0x7146) &&
 236             (dev->pdev->subsystem_vendor == 0x17af) &&
 237             (dev->pdev->subsystem_device == 0x2058)) {
 238                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 239                         return false;
 240         }
 241
 242         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 243         if ((dev->pdev->device == 0x7142) &&
 244             (dev->pdev->subsystem_vendor == 0x1458) &&
 245             (dev->pdev->subsystem_device == 0x2134)) {
 246                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 247                         return false;
 248         }
 249
 250
 251         /* Funky macbooks */
 252         if ((dev->pdev->device == 0x71C5) &&
 253             (dev->pdev->subsystem_vendor == 0x106b) &&
 254             (dev->pdev->subsystem_device == 0x0080)) {
 255                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 256                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 257                         return false;
 258         }
 259
 260         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 261         if ((dev->pdev->device == 0x9598) &&
 262             (dev->pdev->subsystem_vendor == 0x1043) &&
 263             (dev->pdev->subsystem_device == 0x01da)) {
 264                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 265                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 266                 }
 267         }
 268
 269         /* ASUS HD 3450 board lists the DVI port as HDMI */
 270         if ((dev->pdev->device == 0x95C5) &&
 271             (dev->pdev->subsystem_vendor == 0x1043) &&
 272             (dev->pdev->subsystem_device == 0x01e2)) {
 273                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 274                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 275                 }
 276         }
 277
 278         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 279          * HDMI + VGA reporting as HDMI
 280          */
 281         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 282                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 283                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 284                         *line_mux = 0;
 285                 }
 286         }
 287
 288         /* Acer laptop reports DVI-D as DVI-I */
 289         if ((dev->pdev->device == 0x95c4) &&
 290             (dev->pdev->subsystem_vendor == 0x1025) &&
 291             (dev->pdev->subsystem_device == 0x013c)) {
 292                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 293                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 294                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 295         }
 296
 297         return true;
 298 }
 299
 300 const int supported_devices_connector_convert[] = {
 301         DRM_MODE_CONNECTOR_Unknown,
 302         DRM_MODE_CONNECTOR_VGA,
 303         DRM_MODE_CONNECTOR_DVII,
 304         DRM_MODE_CONNECTOR_DVID,
 305         DRM_MODE_CONNECTOR_DVIA,
 306         DRM_MODE_CONNECTOR_SVIDEO,
 307         DRM_MODE_CONNECTOR_Composite,
 308         DRM_MODE_CONNECTOR_LVDS,
 309         DRM_MODE_CONNECTOR_Unknown,
 310         DRM_MODE_CONNECTOR_Unknown,
 311         DRM_MODE_CONNECTOR_HDMIA,
 312         DRM_MODE_CONNECTOR_HDMIB,
 313         DRM_MODE_CONNECTOR_Unknown,
 314         DRM_MODE_CONNECTOR_Unknown,
 315         DRM_MODE_CONNECTOR_9PinDIN,
 316         DRM_MODE_CONNECTOR_DisplayPort
 317 };
 318
 319 const uint16_t supported_devices_connector_object_id_convert[] = {
 320         CONNECTOR_OBJECT_ID_NONE,
 321         CONNECTOR_OBJECT_ID_VGA,
 322         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 323         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 324         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 325         CONNECTOR_OBJECT_ID_COMPOSITE,
 326         CONNECTOR_OBJECT_ID_SVIDEO,
 327         CONNECTOR_OBJECT_ID_LVDS,
 328         CONNECTOR_OBJECT_ID_9PIN_DIN,
 329         CONNECTOR_OBJECT_ID_9PIN_DIN,
 330         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 331         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 332         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 333         CONNECTOR_OBJECT_ID_SVIDEO
 334 };
 335
 336 const int object_connector_convert[] = {
 337         DRM_MODE_CONNECTOR_Unknown,
 338         DRM_MODE_CONNECTOR_DVII,
 339         DRM_MODE_CONNECTOR_DVII,
 340         DRM_MODE_CONNECTOR_DVID,
 341         DRM_MODE_CONNECTOR_DVID,
 342         DRM_MODE_CONNECTOR_VGA,
 343         DRM_MODE_CONNECTOR_Composite,
 344         DRM_MODE_CONNECTOR_SVIDEO,
 345         DRM_MODE_CONNECTOR_Unknown,
 346         DRM_MODE_CONNECTOR_Unknown,
 347         DRM_MODE_CONNECTOR_9PinDIN,
 348         DRM_MODE_CONNECTOR_Unknown,
 349         DRM_MODE_CONNECTOR_HDMIA,
 350         DRM_MODE_CONNECTOR_HDMIB,
 351         DRM_MODE_CONNECTOR_LVDS,
 352         DRM_MODE_CONNECTOR_9PinDIN,
 353         DRM_MODE_CONNECTOR_Unknown,
 354         DRM_MODE_CONNECTOR_Unknown,
 355         DRM_MODE_CONNECTOR_Unknown,
 356         DRM_MODE_CONNECTOR_DisplayPort,
 357         DRM_MODE_CONNECTOR_eDP,
 358         DRM_MODE_CONNECTOR_Unknown
 359 };
 360
 361 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 362 {
 363         struct radeon_device *rdev = dev->dev_private;
 364         struct radeon_mode_info *mode_info = &rdev->mode_info;
 365         struct atom_context *ctx = mode_info->atom_context;
 366         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 367         u16 size, data_offset;
 368         u8 frev, crev;
 369         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 370         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 371         ATOM_OBJECT_HEADER *obj_header;
 372         int i, j, path_size, device_support;
 373         int connector_type;
 374         u16 igp_lane_info, conn_id, connector_object_id;
 375         bool linkb;
 376         struct radeon_i2c_bus_rec ddc_bus;
 377         struct radeon_gpio_rec gpio;
 378         struct radeon_hpd hpd;
 379
 380         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 381
 382         if (data_offset == 0)
 383                 return false;
 384
 385         if (crev < 2)
 386                 return false;
 387
 388         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 389         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 390             (ctx->bios + data_offset +
 391              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 392         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 393             (ctx->bios + data_offset +
 394              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 395         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 396
 397         path_size = 0;
 398         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 399                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 400                 ATOM_DISPLAY_OBJECT_PATH *path;
 401                 addr += path_size;
 402                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 403                 path_size += le16_to_cpu(path->usSize);
 404                 linkb = false;
 405                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 406                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 407
 408                         con_obj_id =
 409                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 410                             >> OBJECT_ID_SHIFT;
 411                         con_obj_num =
 412                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 413                             >> ENUM_ID_SHIFT;
 414                         con_obj_type =
 415                             (le16_to_cpu(path->usConnObjectId) &
 416                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 417
 418                         /* TODO CV support */
 419                         if (le16_to_cpu(path->usDeviceTag) ==
 420                                 ATOM_DEVICE_CV_SUPPORT)
 421                                 continue;
 422
 423                         /* IGP chips */
 424                         if ((rdev->flags & RADEON_IS_IGP) &&
 425                             (con_obj_id ==
 426                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 427                                 uint16_t igp_offset = 0;
 428                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 429
 430                                 index =
 431                                     GetIndexIntoMasterTable(DATA,
 432                                                             IntegratedSystemInfo);
 433
 434                                 atom_parse_data_header(ctx, index, &size, &frev,
 435                                                        &crev, &igp_offset);
 436
 437                                 if (crev >= 2) {
 438                                         igp_obj =
 439                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 440                                              *) (ctx->bios + igp_offset);
 441
 442                                         if (igp_obj) {
 443                                                 uint32_t slot_config, ct;
 444
 445                                                 if (con_obj_num == 1)
 446                                                         slot_config =
 447                                                             igp_obj->
 448                                                             ulDDISlot1Config;
 449                                                 else
 450                                                         slot_config =
 451                                                             igp_obj->
 452                                                             ulDDISlot2Config;
 453
 454                                                 ct = (slot_config >> 16) & 0xff;
 455                                                 connector_type =
 456                                                     object_connector_convert
 457                                                     [ct];
 458                                                 connector_object_id = ct;
 459                                                 igp_lane_info =
 460                                                     slot_config & 0xffff;
 461                                         } else
 462                                                 continue;
 463                                 } else
 464                                         continue;
 465                         } else {
 466                                 igp_lane_info = 0;
 467                                 connector_type =
 468                                     object_connector_convert[con_obj_id];
 469                                 connector_object_id = con_obj_id;
 470                         }
 471
 472                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 473                                 continue;
 474
 475                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 476                              j++) {
 477                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 478
 479                                 enc_obj_id =
 480                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 481                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 482                                 enc_obj_num =
 483                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 484                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 485                                 enc_obj_type =
 486                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 487                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 488
 489                                 /* FIXME: add support for router objects */
 490                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 491                                         if (enc_obj_num == 2)
 492                                                 linkb = true;
 493                                         else
 494                                                 linkb = false;
 495
 496                                         radeon_add_atom_encoder(dev,
 497                                                                 enc_obj_id,
 498                                                                 le16_to_cpu
 499                                                                 (path->
 500                                                                  usDeviceTag));
 501
 502                                 }
 503                         }
 504
 505                         /* look up gpio for ddc, hpd */
 506                         if ((le16_to_cpu(path->usDeviceTag) &
 507                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 508                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 509                                         if (le16_to_cpu(path->usConnObjectId) ==
 510                                             le16_to_cpu(con_obj->asObjects[j].
 511                                                         usObjectID)) {
 512                                                 ATOM_COMMON_RECORD_HEADER
 513                                                     *record =
 514                                                     (ATOM_COMMON_RECORD_HEADER
 515                                                      *)
 516                                                     (ctx->bios + data_offset +
 517                                                      le16_to_cpu(con_obj->
 518                                                                  asObjects[j].
 519                                                                  usRecordOffset));
 520                                                 ATOM_I2C_RECORD *i2c_record;
 521                                                 ATOM_HPD_INT_RECORD *hpd_record;
 522                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 523                                                 hpd.hpd = RADEON_HPD_NONE;
 524
 525                                                 while (record->ucRecordType > 0
 526                                                        && record->
 527                                                        ucRecordType <=
 528                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 529                                                         switch (record->ucRecordType) {
 530                                                         case ATOM_I2C_RECORD_TYPE:
 531                                                                 i2c_record =
 532                                                                     (ATOM_I2C_RECORD *)
 533                                                                         record;
 534                                                                 i2c_config =
 535                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 536                                                                         &i2c_record->sucI2cId;
 537                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 538                                                                                                  i2c_config->
 539                                                                                                  ucAccess);
 540                                                                 break;
 541                                                         case ATOM_HPD_INT_RECORD_TYPE:
 542                                                                 hpd_record =
 543                                                                         (ATOM_HPD_INT_RECORD *)
 544                                                                         record;
 545                                                                 gpio = radeon_lookup_gpio(rdev,
 546                                                                                           hpd_record->ucHPDIntGPIOID);
 547                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 548                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 549                                                                 break;
 550                                                         }
 551                                                         record =
 552                                                             (ATOM_COMMON_RECORD_HEADER
 553                                                              *) ((char *)record
 554                                                                  +
 555                                                                  record->
 556                                                                  ucRecordSize);
 557                                                 }
 558                                                 break;
 559                                         }
 560                                 }
 561                         } else {
 562                                 hpd.hpd = RADEON_HPD_NONE;
 563                                 ddc_bus.valid = false;
 564                         }
 565
 566                         /* needed for aux chan transactions */
 567                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 568
 569                         conn_id = le16_to_cpu(path->usConnObjectId);
 570
 571                         if (!radeon_atom_apply_quirks
 572                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 573                              &ddc_bus, &conn_id, &hpd))
 574                                 continue;
 575
 576                         radeon_add_atom_connector(dev,
 577                                                   conn_id,
 578                                                   le16_to_cpu(path->
 579                                                               usDeviceTag),
 580                                                   connector_type, &ddc_bus,
 581                                                   linkb, igp_lane_info,
 582                                                   connector_object_id,
 583                                                   &hpd);
 584
 585                 }
 586         }
 587
 588         radeon_link_encoder_connector(dev);
 589
 590         return true;
 591 }
 592
 593 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 594                                                  int connector_type,
 595                                                  uint16_t devices)
 596 {
 597         struct radeon_device *rdev = dev->dev_private;
 598
 599         if (rdev->flags & RADEON_IS_IGP) {
 600                 return supported_devices_connector_object_id_convert
 601                         [connector_type];
 602         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 603                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 604                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 605                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 606                 struct atom_context *ctx = mode_info->atom_context;
 607                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 608                 uint16_t size, data_offset;
 609                 uint8_t frev, crev;
 610                 ATOM_XTMDS_INFO *xtmds;
 611
 612                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 613                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 614
 615                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 616                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 617                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 618                         else
 619                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 620                 } else {
 621                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 622                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 623                         else
 624                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 625                 }
 626         } else {
 627                 return supported_devices_connector_object_id_convert
 628                         [connector_type];
 629         }
 630 }
 631
 632 struct bios_connector {
 633         bool valid;
 634         uint16_t line_mux;
 635         uint16_t devices;
 636         int connector_type;
 637         struct radeon_i2c_bus_rec ddc_bus;
 638         struct radeon_hpd hpd;
 639 };
 640
 641 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 642                                                                  drm_device
 643                                                                  *dev)
 644 {
 645         struct radeon_device *rdev = dev->dev_private;
 646         struct radeon_mode_info *mode_info = &rdev->mode_info;
 647         struct atom_context *ctx = mode_info->atom_context;
 648         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 649         uint16_t size, data_offset;
 650         uint8_t frev, crev;
 651         uint16_t device_support;
 652         uint8_t dac;
 653         union atom_supported_devices *supported_devices;
 654         int i, j, max_device;
 655         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 656
 657         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 658
 659         supported_devices =
 660             (union atom_supported_devices *)(ctx->bios + data_offset);
 661
 662         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 663
 664         if (frev > 1)
 665                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 666         else
 667                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 668
 669         for (i = 0; i < max_device; i++) {
 670                 ATOM_CONNECTOR_INFO_I2C ci =
 671                     supported_devices->info.asConnInfo[i];
 672
 673                 bios_connectors[i].valid = false;
 674
 675                 if (!(device_support & (1 << i))) {
 676                         continue;
 677                 }
 678
 679                 if (i == ATOM_DEVICE_CV_INDEX) {
 680                         DRM_DEBUG("Skipping Component Video\n");
 681                         continue;
 682                 }
 683
 684                 bios_connectors[i].connector_type =
 685                     supported_devices_connector_convert[ci.sucConnectorInfo.
 686                                                         sbfAccess.
 687                                                         bfConnectorType];
 688
 689                 if (bios_connectors[i].connector_type ==
 690                     DRM_MODE_CONNECTOR_Unknown)
 691                         continue;
 692
 693                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 694
 695                 bios_connectors[i].line_mux =
 696                         ci.sucI2cId.ucAccess;
 697
 698                 /* give tv unique connector ids */
 699                 if (i == ATOM_DEVICE_TV1_INDEX) {
 700                         bios_connectors[i].ddc_bus.valid = false;
 701                         bios_connectors[i].line_mux = 50;
 702                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 703                         bios_connectors[i].ddc_bus.valid = false;
 704                         bios_connectors[i].line_mux = 51;
 705                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 706                         bios_connectors[i].ddc_bus.valid = false;
 707                         bios_connectors[i].line_mux = 52;
 708                 } else
 709                         bios_connectors[i].ddc_bus =
 710                             radeon_lookup_i2c_gpio(rdev,
 711                                                    bios_connectors[i].line_mux);
 712
 713                 if ((crev > 1) && (frev > 1)) {
 714                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 715                         switch (isb) {
 716                         case 0x4:
 717                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 718                                 break;
 719                         case 0xa:
 720                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 721                                 break;
 722                         default:
 723                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 724                                 break;
 725                         }
 726                 } else {
 727                         if (i == ATOM_DEVICE_DFP1_INDEX)
 728                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 729                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 730                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 731                         else
 732                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 733                 }
 734
 735                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 736                  * shared with a DVI port, we'll pick up the DVI connector when we
 737                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 738                  */
 739                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 740                         bios_connectors[i].connector_type =
 741                             DRM_MODE_CONNECTOR_VGA;
 742
 743                 if (!radeon_atom_apply_quirks
 744                     (dev, (1 << i), &bios_connectors[i].connector_type,
 745                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 746                      &bios_connectors[i].hpd))
 747                         continue;
 748
 749                 bios_connectors[i].valid = true;
 750                 bios_connectors[i].devices = (1 << i);
 751
 752                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 753                         radeon_add_atom_encoder(dev,
 754                                                 radeon_get_encoder_id(dev,
 755                                                                       (1 << i),
 756                                                                       dac),
 757                                                 (1 << i));
 758                 else
 759                         radeon_add_legacy_encoder(dev,
 760                                                   radeon_get_encoder_id(dev,
 761                                                                         (1 << i),
 762                                                                         dac),
 763                                                   (1 << i));
 764         }
 765
 766         /* combine shared connectors */
 767         for (i = 0; i < max_device; i++) {
 768                 if (bios_connectors[i].valid) {
 769                         for (j = 0; j < max_device; j++) {
 770                                 if (bios_connectors[j].valid && (i != j)) {
 771                                         if (bios_connectors[i].line_mux ==
 772                                             bios_connectors[j].line_mux) {
 773                                                 /* make sure not to combine LVDS */
 774                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 775                                                         bios_connectors[i].line_mux = 53;
 776                                                         bios_connectors[i].ddc_bus.valid = false;
 777                                                         continue;
 778                                                 }
 779                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 780                                                         bios_connectors[j].line_mux = 53;
 781                                                         bios_connectors[j].ddc_bus.valid = false;
 782                                                         continue;
 783                                                 }
 784                                                 /* combine analog and digital for DVI-I */
 785                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 786                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 787                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 788                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 789                                                         bios_connectors[i].devices |=
 790                                                                 bios_connectors[j].devices;
 791                                                         bios_connectors[i].connector_type =
 792                                                                 DRM_MODE_CONNECTOR_DVII;
 793                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 794                                                                 bios_connectors[i].hpd =
 795                                                                         bios_connectors[j].hpd;
 796                                                         bios_connectors[j].valid = false;
 797                                                 }
 798                                         }
 799                                 }
 800                         }
 801                 }
 802         }
 803
 804         /* add the connectors */
 805         for (i = 0; i < max_device; i++) {
 806                 if (bios_connectors[i].valid) {
 807                         uint16_t connector_object_id =
 808                                 atombios_get_connector_object_id(dev,
 809                                                       bios_connectors[i].connector_type,
 810                                                       bios_connectors[i].devices);
 811                         radeon_add_atom_connector(dev,
 812                                                   bios_connectors[i].line_mux,
 813                                                   bios_connectors[i].devices,
 814                                                   bios_connectors[i].
 815                                                   connector_type,
 816                                                   &bios_connectors[i].ddc_bus,
 817                                                   false, 0,
 818                                                   connector_object_id,
 819                                                   &bios_connectors[i].hpd);
 820                 }
 821         }
 822
 823         radeon_link_encoder_connector(dev);
 824
 825         return true;
 826 }
 827
 828 union firmware_info {
 829         ATOM_FIRMWARE_INFO info;
 830         ATOM_FIRMWARE_INFO_V1_2 info_12;
 831         ATOM_FIRMWARE_INFO_V1_3 info_13;
 832         ATOM_FIRMWARE_INFO_V1_4 info_14;
 833         ATOM_FIRMWARE_INFO_V2_1 info_21;
 834 };
 835
 836 bool radeon_atom_get_clock_info(struct drm_device *dev)
 837 {
 838         struct radeon_device *rdev = dev->dev_private;
 839         struct radeon_mode_info *mode_info = &rdev->mode_info;
 840         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 841         union firmware_info *firmware_info;
 842         uint8_t frev, crev;
 843         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 844         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 845         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 846         struct radeon_pll *spll = &rdev->clock.spll;
 847         struct radeon_pll *mpll = &rdev->clock.mpll;
 848         uint16_t data_offset;
 849
 850         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 851                                &crev, &data_offset);
 852
 853         firmware_info =
 854             (union firmware_info *)(mode_info->atom_context->bios +
 855                                     data_offset);
 856
 857         if (firmware_info) {
 858                 /* pixel clocks */
 859                 p1pll->reference_freq =
 860                     le16_to_cpu(firmware_info->info.usReferenceClock);
 861                 p1pll->reference_div = 0;
 862
 863                 if (crev < 2)
 864                         p1pll->pll_out_min =
 865                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 866                 else
 867                         p1pll->pll_out_min =
 868                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 869                 p1pll->pll_out_max =
 870                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 871
 872                 if (p1pll->pll_out_min == 0) {
 873                         if (ASIC_IS_AVIVO(rdev))
 874                                 p1pll->pll_out_min = 64800;
 875                         else
 876                                 p1pll->pll_out_min = 20000;
 877                 } else if (p1pll->pll_out_min > 64800) {
 878                         /* Limiting the pll output range is a good thing generally as
 879                          * it limits the number of possible pll combinations for a given
 880                          * frequency presumably to the ones that work best on each card.
 881                          * However, certain duallink DVI monitors seem to like
 882                          * pll combinations that would be limited by this at least on
 883                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 884                          * family.
 885                          */
 886                         if (!radeon_new_pll)
 887                                 p1pll->pll_out_min = 64800;
 888                 }
 889
 890                 p1pll->pll_in_min =
 891                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 892                 p1pll->pll_in_max =
 893                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 894
 895                 *p2pll = *p1pll;
 896
 897                 /* system clock */
 898                 spll->reference_freq =
 899                     le16_to_cpu(firmware_info->info.usReferenceClock);
 900                 spll->reference_div = 0;
 901
 902                 spll->pll_out_min =
 903                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 904                 spll->pll_out_max =
 905                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 906
 907                 /* ??? */
 908                 if (spll->pll_out_min == 0) {
 909                         if (ASIC_IS_AVIVO(rdev))
 910                                 spll->pll_out_min = 64800;
 911                         else
 912                                 spll->pll_out_min = 20000;
 913                 }
 914
 915                 spll->pll_in_min =
 916                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 917                 spll->pll_in_max =
 918                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 919
 920                 /* memory clock */
 921                 mpll->reference_freq =
 922                     le16_to_cpu(firmware_info->info.usReferenceClock);
 923                 mpll->reference_div = 0;
 924
 925                 mpll->pll_out_min =
 926                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 927                 mpll->pll_out_max =
 928                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 929
 930                 /* ??? */
 931                 if (mpll->pll_out_min == 0) {
 932                         if (ASIC_IS_AVIVO(rdev))
 933                                 mpll->pll_out_min = 64800;
 934                         else
 935                                 mpll->pll_out_min = 20000;
 936                 }
 937
 938                 mpll->pll_in_min =
 939                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 940                 mpll->pll_in_max =
 941                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 942
 943                 rdev->clock.default_sclk =
 944                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 945                 rdev->clock.default_mclk =
 946                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 947
 948                 if (ASIC_IS_DCE4(rdev)) {
 949                         rdev->clock.default_dispclk =
 950                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 951                         if (rdev->clock.default_dispclk == 0)
 952                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
 953                         rdev->clock.dp_extclk =
 954                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 955                 }
 956                 *dcpll = *p1pll;
 957
 958                 return true;
 959         }
 960
 961         return false;
 962 }
 963
 964 union igp_info {
 965         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 966         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 967 };
 968
 969 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
 970 {
 971         struct radeon_mode_info *mode_info = &rdev->mode_info;
 972         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 973         union igp_info *igp_info;
 974         u8 frev, crev;
 975         u16 data_offset;
 976
 977         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 978                                &crev, &data_offset);
 979
 980         igp_info = (union igp_info *)(mode_info->atom_context->bios +
 981                                       data_offset);
 982
 983         if (igp_info) {
 984                 switch (crev) {
 985                 case 1:
 986                         if (igp_info->info.ucMemoryType & 0xf0)
 987                                 return true;
 988                         break;
 989                 case 2:
 990                         if (igp_info->info_2.ucMemoryType & 0x0f)
 991                                 return true;
 992                         break;
 993                 default:
 994                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 995                         break;
 996                 }
 997         }
 998         return false;
 999 }
1000
1001 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1002                                    struct radeon_encoder_int_tmds *tmds)
1003 {
1004         struct drm_device *dev = encoder->base.dev;
1005         struct radeon_device *rdev = dev->dev_private;
1006         struct radeon_mode_info *mode_info = &rdev->mode_info;
1007         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1008         uint16_t data_offset;
1009         struct _ATOM_TMDS_INFO *tmds_info;
1010         uint8_t frev, crev;
1011         uint16_t maxfreq;
1012         int i;
1013
1014         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1015                                &crev, &data_offset);
1016
1017         tmds_info =
1018             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1019                                        data_offset);
1020
1021         if (tmds_info) {
1022                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1023                 for (i = 0; i < 4; i++) {
1024                         tmds->tmds_pll[i].freq =
1025                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1026                         tmds->tmds_pll[i].value =
1027                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1028                         tmds->tmds_pll[i].value |=
1029                             (tmds_info->asMiscInfo[i].
1030                              ucPLL_VCO_Gain & 0x3f) << 6;
1031                         tmds->tmds_pll[i].value |=
1032                             (tmds_info->asMiscInfo[i].
1033                              ucPLL_DutyCycle & 0xf) << 12;
1034                         tmds->tmds_pll[i].value |=
1035                             (tmds_info->asMiscInfo[i].
1036                              ucPLL_VoltageSwing & 0xf) << 16;
1037
1038                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1039                                   tmds->tmds_pll[i].freq,
1040                                   tmds->tmds_pll[i].value);
1041
1042                         if (maxfreq == tmds->tmds_pll[i].freq) {
1043                                 tmds->tmds_pll[i].freq = 0xffffffff;
1044                                 break;
1045                         }
1046                 }
1047                 return true;
1048         }
1049         return false;
1050 }
1051
1052 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1053                                                           radeon_encoder
1054                                                           *encoder,
1055                                                           int id)
1056 {
1057         struct drm_device *dev = encoder->base.dev;
1058         struct radeon_device *rdev = dev->dev_private;
1059         struct radeon_mode_info *mode_info = &rdev->mode_info;
1060         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1061         uint16_t data_offset;
1062         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1063         uint8_t frev, crev;
1064         struct radeon_atom_ss *ss = NULL;
1065         int i;
1066
1067         if (id > ATOM_MAX_SS_ENTRY)
1068                 return NULL;
1069
1070         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1071                                &crev, &data_offset);
1072
1073         ss_info =
1074             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1075
1076         if (ss_info) {
1077                 ss =
1078                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1079
1080                 if (!ss)
1081                         return NULL;
1082
1083                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1084                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1085                                 ss->percentage =
1086                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1087                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1088                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1089                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1090                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1091                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1092                                 break;
1093                         }
1094                 }
1095         }
1096         return ss;
1097 }
1098
1099 static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
1100                                           struct radeon_encoder_atom_dig *lvds)
1101 {
1102
1103         /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1104         if ((dev->pdev->device == 0x95c4) &&
1105             (dev->pdev->subsystem_vendor == 0x1179) &&
1106             (dev->pdev->subsystem_device == 0xff50)) {
1107                 if ((lvds->native_mode.hdisplay == 1280) &&
1108                     (lvds->native_mode.vdisplay == 800))
1109                         lvds->pll_algo = PLL_ALGO_LEGACY;
1110         }
1111
1112         /* Dell Studio 15 laptop panel doesn't like new pll divider algo */
1113         if ((dev->pdev->device == 0x95c4) &&
1114             (dev->pdev->subsystem_vendor == 0x1028) &&
1115             (dev->pdev->subsystem_device == 0x029f)) {
1116                 if ((lvds->native_mode.hdisplay == 1280) &&
1117                     (lvds->native_mode.vdisplay == 800))
1118                         lvds->pll_algo = PLL_ALGO_LEGACY;
1119         }
1120
1121 }
1122
1123 union lvds_info {
1124         struct _ATOM_LVDS_INFO info;
1125         struct _ATOM_LVDS_INFO_V12 info_12;
1126 };
1127
1128 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1129                                                               radeon_encoder
1130                                                               *encoder)
1131 {
1132         struct drm_device *dev = encoder->base.dev;
1133         struct radeon_device *rdev = dev->dev_private;
1134         struct radeon_mode_info *mode_info = &rdev->mode_info;
1135         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1136         uint16_t data_offset, misc;
1137         union lvds_info *lvds_info;
1138         uint8_t frev, crev;
1139         struct radeon_encoder_atom_dig *lvds = NULL;
1140
1141         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1142                                &crev, &data_offset);
1143
1144         lvds_info =
1145             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1146
1147         if (lvds_info) {
1148                 lvds =
1149                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1150
1151                 if (!lvds)
1152                         return NULL;
1153
1154                 lvds->native_mode.clock =
1155                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1156                 lvds->native_mode.hdisplay =
1157                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1158                 lvds->native_mode.vdisplay =
1159                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1160                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1161                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1162                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1163                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1164                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1165                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1166                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1167                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1168                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1169                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1170                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1171                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1172                 lvds->panel_pwr_delay =
1173                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1174                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1175
1176                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1177                 if (misc & ATOM_VSYNC_POLARITY)
1178                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1179                 if (misc & ATOM_HSYNC_POLARITY)
1180                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1181                 if (misc & ATOM_COMPOSITESYNC)
1182                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1183                 if (misc & ATOM_INTERLACE)
1184                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1185                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1186                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1187
1188                 /* set crtc values */
1189                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1190
1191                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1192
1193                 if (ASIC_IS_AVIVO(rdev)) {
1194                         if (radeon_new_pll == 0)
1195                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1196                         else
1197                                 lvds->pll_algo = PLL_ALGO_NEW;
1198                 } else {
1199                         if (radeon_new_pll == 1)
1200                                 lvds->pll_algo = PLL_ALGO_NEW;
1201                         else
1202                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1203                 }
1204
1205                 /* LVDS quirks */
1206                 radeon_atom_apply_lvds_quirks(dev, lvds);
1207
1208                 encoder->native_mode = lvds->native_mode;
1209         }
1210         return lvds;
1211 }
1212
1213 struct radeon_encoder_primary_dac *
1214 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1215 {
1216         struct drm_device *dev = encoder->base.dev;
1217         struct radeon_device *rdev = dev->dev_private;
1218         struct radeon_mode_info *mode_info = &rdev->mode_info;
1219         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1220         uint16_t data_offset;
1221         struct _COMPASSIONATE_DATA *dac_info;
1222         uint8_t frev, crev;
1223         uint8_t bg, dac;
1224         struct radeon_encoder_primary_dac *p_dac = NULL;
1225
1226         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1227
1228         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1229
1230         if (dac_info) {
1231                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1232
1233                 if (!p_dac)
1234                         return NULL;
1235
1236                 bg = dac_info->ucDAC1_BG_Adjustment;
1237                 dac = dac_info->ucDAC1_DAC_Adjustment;
1238                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1239
1240         }
1241         return p_dac;
1242 }
1243
1244 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1245                                 struct drm_display_mode *mode)
1246 {
1247         struct radeon_mode_info *mode_info = &rdev->mode_info;
1248         ATOM_ANALOG_TV_INFO *tv_info;
1249         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1250         ATOM_DTD_FORMAT *dtd_timings;
1251         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1252         u8 frev, crev;
1253         u16 data_offset, misc;
1254
1255         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1256
1257         switch (crev) {
1258         case 1:
1259                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1260                 if (index > MAX_SUPPORTED_TV_TIMING)
1261                         return false;
1262
1263                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1264                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1265                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1266                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1267                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1268
1269                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1270                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1271                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1272                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1273                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1274
1275                 mode->flags = 0;
1276                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1277                 if (misc & ATOM_VSYNC_POLARITY)
1278                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1279                 if (misc & ATOM_HSYNC_POLARITY)
1280                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1281                 if (misc & ATOM_COMPOSITESYNC)
1282                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1283                 if (misc & ATOM_INTERLACE)
1284                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1285                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1286                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1287
1288                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1289
1290                 if (index == 1) {
1291                         /* PAL timings appear to have wrong values for totals */
1292                         mode->crtc_htotal -= 1;
1293                         mode->crtc_vtotal -= 1;
1294                 }
1295                 break;
1296         case 2:
1297                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1298                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1299                         return false;
1300
1301                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1302                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1303                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1304                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1305                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1306                         le16_to_cpu(dtd_timings->usHSyncOffset);
1307                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1308                         le16_to_cpu(dtd_timings->usHSyncWidth);
1309
1310                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1311                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1312                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1313                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1314                         le16_to_cpu(dtd_timings->usVSyncOffset);
1315                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1316                         le16_to_cpu(dtd_timings->usVSyncWidth);
1317
1318                 mode->flags = 0;
1319                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1320                 if (misc & ATOM_VSYNC_POLARITY)
1321                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1322                 if (misc & ATOM_HSYNC_POLARITY)
1323                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1324                 if (misc & ATOM_COMPOSITESYNC)
1325                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1326                 if (misc & ATOM_INTERLACE)
1327                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1328                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1329                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1330
1331                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1332                 break;
1333         }
1334         return true;
1335 }
1336
1337 enum radeon_tv_std
1338 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1339 {
1340         struct radeon_mode_info *mode_info = &rdev->mode_info;
1341         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1342         uint16_t data_offset;
1343         uint8_t frev, crev;
1344         struct _ATOM_ANALOG_TV_INFO *tv_info;
1345         enum radeon_tv_std tv_std = TV_STD_NTSC;
1346
1347         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1348
1349         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1350
1351         switch (tv_info->ucTV_BootUpDefaultStandard) {
1352         case ATOM_TV_NTSC:
1353                 tv_std = TV_STD_NTSC;
1354                 DRM_INFO("Default TV standard: NTSC\n");
1355                 break;
1356         case ATOM_TV_NTSCJ:
1357                 tv_std = TV_STD_NTSC_J;
1358                 DRM_INFO("Default TV standard: NTSC-J\n");
1359                 break;
1360         case ATOM_TV_PAL:
1361                 tv_std = TV_STD_PAL;
1362                 DRM_INFO("Default TV standard: PAL\n");
1363                 break;
1364         case ATOM_TV_PALM:
1365                 tv_std = TV_STD_PAL_M;
1366                 DRM_INFO("Default TV standard: PAL-M\n");
1367                 break;
1368         case ATOM_TV_PALN:
1369                 tv_std = TV_STD_PAL_N;
1370                 DRM_INFO("Default TV standard: PAL-N\n");
1371                 break;
1372         case ATOM_TV_PALCN:
1373                 tv_std = TV_STD_PAL_CN;
1374                 DRM_INFO("Default TV standard: PAL-CN\n");
1375                 break;
1376         case ATOM_TV_PAL60:
1377                 tv_std = TV_STD_PAL_60;
1378                 DRM_INFO("Default TV standard: PAL-60\n");
1379                 break;
1380         case ATOM_TV_SECAM:
1381                 tv_std = TV_STD_SECAM;
1382                 DRM_INFO("Default TV standard: SECAM\n");
1383                 break;
1384         default:
1385                 tv_std = TV_STD_NTSC;
1386                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1387                 break;
1388         }
1389         return tv_std;
1390 }
1391
1392 struct radeon_encoder_tv_dac *
1393 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1394 {
1395         struct drm_device *dev = encoder->base.dev;
1396         struct radeon_device *rdev = dev->dev_private;
1397         struct radeon_mode_info *mode_info = &rdev->mode_info;
1398         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1399         uint16_t data_offset;
1400         struct _COMPASSIONATE_DATA *dac_info;
1401         uint8_t frev, crev;
1402         uint8_t bg, dac;
1403         struct radeon_encoder_tv_dac *tv_dac = NULL;
1404
1405         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1406
1407         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1408
1409         if (dac_info) {
1410                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1411
1412                 if (!tv_dac)
1413                         return NULL;
1414
1415                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1416                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1417                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1418
1419                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1420                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1421                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1422
1423                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1424                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1425                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1426
1427                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1428         }
1429         return tv_dac;
1430 }
1431
1432 union power_info {
1433         struct _ATOM_POWERPLAY_INFO info;
1434         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1435         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1436         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1437 };
1438
1439 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1440 {
1441         struct radeon_mode_info *mode_info = &rdev->mode_info;
1442         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1443         u16 data_offset;
1444         u8 frev, crev;
1445         u32 misc, misc2 = 0, sclk, mclk;
1446         union power_info *power_info;
1447         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1448         struct _ATOM_PPLIB_STATE *power_state;
1449         int num_modes = 0, i, j;
1450         int state_index = 0, mode_index = 0;
1451
1452         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1453
1454         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1455
1456         rdev->pm.default_power_state = NULL;
1457
1458         if (power_info) {
1459                 if (frev < 4) {
1460                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1461                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1462                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1463                         for (i = 0; i < num_modes; i++) {
1464                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1465                                 switch (frev) {
1466                                 case 1:
1467                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1468                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1469                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1470                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1471                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1472                                         /* skip invalid modes */
1473                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1474                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1475                                                 continue;
1476                                         /* skip overclock modes for now */
1477                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1478                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1479                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1480                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1481                                                 continue;
1482                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1483                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1484                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1485                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1486                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1487                                                         VOLTAGE_GPIO;
1488                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1489                                                         radeon_lookup_gpio(rdev,
1490                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1491                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1492                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1493                                                                 true;
1494                                                 else
1495                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1496                                                                 false;
1497                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1498                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1499                                                         VOLTAGE_VDDC;
1500                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1501                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1502                                         }
1503                                         /* order matters! */
1504                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1505                                                 rdev->pm.power_state[state_index].type =
1506                                                         POWER_STATE_TYPE_POWERSAVE;
1507                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1508                                                 rdev->pm.power_state[state_index].type =
1509                                                         POWER_STATE_TYPE_BATTERY;
1510                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1511                                                 rdev->pm.power_state[state_index].type =
1512                                                         POWER_STATE_TYPE_BATTERY;
1513                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1514                                                 rdev->pm.power_state[state_index].type =
1515                                                         POWER_STATE_TYPE_BALANCED;
1516                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1517                                                 rdev->pm.power_state[state_index].type =
1518                                                         POWER_STATE_TYPE_PERFORMANCE;
1519                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1520                                                 rdev->pm.power_state[state_index].type =
1521                                                         POWER_STATE_TYPE_DEFAULT;
1522                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1523                                                 rdev->pm.power_state[state_index].default_clock_mode =
1524                                                         &rdev->pm.power_state[state_index].clock_info[0];
1525                                         }
1526                                         state_index++;
1527                                         break;
1528                                 case 2:
1529                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1530                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1531                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1532                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1533                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1534                                         /* skip invalid modes */
1535                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1536                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1537                                                 continue;
1538                                         /* skip overclock modes for now */
1539                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1540                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1541                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1542                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1543                                                 continue;
1544                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1545                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1546                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1547                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1548                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1549                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1550                                                         VOLTAGE_GPIO;
1551                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1552                                                         radeon_lookup_gpio(rdev,
1553                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1554                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1555                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1556                                                                 true;
1557                                                 else
1558                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1559                                                                 false;
1560                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1561                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1562                                                         VOLTAGE_VDDC;
1563                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1564                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1565                                         }
1566                                         /* order matters! */
1567                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1568                                                 rdev->pm.power_state[state_index].type =
1569                                                         POWER_STATE_TYPE_POWERSAVE;
1570                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1571                                                 rdev->pm.power_state[state_index].type =
1572                                                         POWER_STATE_TYPE_BATTERY;
1573                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1574                                                 rdev->pm.power_state[state_index].type =
1575                                                         POWER_STATE_TYPE_BATTERY;
1576                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1577                                                 rdev->pm.power_state[state_index].type =
1578                                                         POWER_STATE_TYPE_BALANCED;
1579                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1580                                                 rdev->pm.power_state[state_index].type =
1581                                                         POWER_STATE_TYPE_PERFORMANCE;
1582                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1583                                                 rdev->pm.power_state[state_index].type =
1584                                                         POWER_STATE_TYPE_BALANCED;
1585                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1586                                                 rdev->pm.power_state[state_index].type =
1587                                                         POWER_STATE_TYPE_DEFAULT;
1588                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1589                                                 rdev->pm.power_state[state_index].default_clock_mode =
1590                                                         &rdev->pm.power_state[state_index].clock_info[0];
1591                                         }
1592                                         state_index++;
1593                                         break;
1594                                 case 3:
1595                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1596                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1597                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1598                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1599                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1600                                         /* skip invalid modes */
1601                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1602                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1603                                                 continue;
1604                                         /* skip overclock modes for now */
1605                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1606                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1607                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1608                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1609                                                 continue;
1610                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1611                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1612                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1613                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1614                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1615                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1616                                                         VOLTAGE_GPIO;
1617                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1618                                                         radeon_lookup_gpio(rdev,
1619                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1620                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1621                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1622                                                                 true;
1623                                                 else
1624                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1625                                                                 false;
1626                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1627                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1628                                                         VOLTAGE_VDDC;
1629                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1630                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1631                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1632                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1633                                                                 true;
1634                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1635                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1636                                                 }
1637                                         }
1638                                         /* order matters! */
1639                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1640                                                 rdev->pm.power_state[state_index].type =
1641                                                         POWER_STATE_TYPE_POWERSAVE;
1642                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1643                                                 rdev->pm.power_state[state_index].type =
1644                                                         POWER_STATE_TYPE_BATTERY;
1645                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1646                                                 rdev->pm.power_state[state_index].type =
1647                                                         POWER_STATE_TYPE_BATTERY;
1648                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1649                                                 rdev->pm.power_state[state_index].type =
1650                                                         POWER_STATE_TYPE_BALANCED;
1651                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1652                                                 rdev->pm.power_state[state_index].type =
1653                                                         POWER_STATE_TYPE_PERFORMANCE;
1654                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1655                                                 rdev->pm.power_state[state_index].type =
1656                                                         POWER_STATE_TYPE_BALANCED;
1657                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1658                                                 rdev->pm.power_state[state_index].type =
1659                                                         POWER_STATE_TYPE_DEFAULT;
1660                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1661                                                 rdev->pm.power_state[state_index].default_clock_mode =
1662                                                         &rdev->pm.power_state[state_index].clock_info[0];
1663                                         }
1664                                         state_index++;
1665                                         break;
1666                                 }
1667                         }
1668                 } else if (frev == 4) {
1669                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1670                                 mode_index = 0;
1671                                 power_state = (struct _ATOM_PPLIB_STATE *)
1672                                         (mode_info->atom_context->bios +
1673                                          data_offset +
1674                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1675                                          i * power_info->info_4.ucStateEntrySize);
1676                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1677                                         (mode_info->atom_context->bios +
1678                                          data_offset +
1679                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1680                                          (power_state->ucNonClockStateIndex *
1681                                           power_info->info_4.ucNonClockSize));
1682                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1683                                         if (rdev->flags & RADEON_IS_IGP) {
1684                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1685                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1686                                                         (mode_info->atom_context->bios +
1687                                                          data_offset +
1688                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1689                                                          (power_state->ucClockStateIndices[j] *
1690                                                           power_info->info_4.ucClockInfoSize));
1691                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1692                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1693                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1694                                                 /* skip invalid modes */
1695                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1696                                                         continue;
1697                                                 /* skip overclock modes for now */
1698                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1699                                                     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1700                                                         continue;
1701                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1702                                                         VOLTAGE_SW;
1703                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1704                                                         clock_info->usVDDC;
1705                                                 mode_index++;
1706                                         } else {
1707                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1708                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1709                                                         (mode_info->atom_context->bios +
1710                                                          data_offset +
1711                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1712                                                          (power_state->ucClockStateIndices[j] *
1713                                                           power_info->info_4.ucClockInfoSize));
1714                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1715                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1716                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1717                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1718                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1719                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1720                                                 /* skip invalid modes */
1721                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1722                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1723                                                         continue;
1724                                                 /* skip overclock modes for now */
1725                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1726                                                      rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1727                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1728                                                      rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1729                                                         continue;
1730                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1731                                                         VOLTAGE_SW;
1732                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1733                                                         clock_info->usVDDC;
1734                                                 mode_index++;
1735                                         }
1736                                 }
1737                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1738                                 if (mode_index) {
1739                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1740                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1741                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1742                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1743                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1744                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1745                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1746                                                 rdev->pm.power_state[state_index].type =
1747                                                         POWER_STATE_TYPE_BATTERY;
1748                                                 break;
1749                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1750                                                 rdev->pm.power_state[state_index].type =
1751                                                         POWER_STATE_TYPE_BALANCED;
1752                                                 break;
1753                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1754                                                 rdev->pm.power_state[state_index].type =
1755                                                         POWER_STATE_TYPE_PERFORMANCE;
1756                                                 break;
1757                                         }
1758                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1759                                                 rdev->pm.power_state[state_index].type =
1760                                                         POWER_STATE_TYPE_DEFAULT;
1761                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1762                                                 rdev->pm.power_state[state_index].default_clock_mode =
1763                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1764                                         }
1765                                         state_index++;
1766                                 }
1767                         }
1768                 }
1769         } else {
1770                 /* XXX figure out some good default low power mode for cards w/out power tables */
1771         }
1772
1773         if (rdev->pm.default_power_state == NULL) {
1774                 /* add the default mode */
1775                 rdev->pm.power_state[state_index].type =
1776                         POWER_STATE_TYPE_DEFAULT;
1777                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1778                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1779                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1780                 rdev->pm.power_state[state_index].default_clock_mode =
1781                         &rdev->pm.power_state[state_index].clock_info[0];
1782                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1783                 if (rdev->asic->get_pcie_lanes)
1784                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1785                 else
1786                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1787                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1788                 state_index++;
1789         }
1790         rdev->pm.num_power_states = state_index;
1791
1792         rdev->pm.current_power_state = rdev->pm.default_power_state;
1793         rdev->pm.current_clock_mode =
1794                 rdev->pm.default_power_state->default_clock_mode;
1795 }
1796
1797 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1798 {
1799         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1800         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1801
1802         args.ucEnable = enable;
1803
1804         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1805 }
1806
1807 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1808 {
1809         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1810         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1811
1812         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1813         return args.ulReturnEngineClock;
1814 }
1815
1816 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1817 {
1818         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1819         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1820
1821         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1822         return args.ulReturnMemoryClock;
1823 }
1824
1825 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1826                                   uint32_t eng_clock)
1827 {
1828         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1829         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1830
1831         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1832
1833         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1834 }
1835
1836 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1837                                   uint32_t mem_clock)
1838 {
1839         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1840         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1841
1842         if (rdev->flags & RADEON_IS_IGP)
1843                 return;
1844
1845         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1846
1847         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1848 }
1849
1850 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1851 {
1852         struct radeon_device *rdev = dev->dev_private;
1853         uint32_t bios_2_scratch, bios_6_scratch;
1854
1855         if (rdev->family >= CHIP_R600) {
1856                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1857                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1858         } else {
1859                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1860                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1861         }
1862
1863         /* let the bios control the backlight */
1864         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1865
1866         /* tell the bios not to handle mode switching */
1867         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1868
1869         if (rdev->family >= CHIP_R600) {
1870                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1871                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1872         } else {
1873                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1874                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1875         }
1876
1877 }
1878
1879 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1880 {
1881         uint32_t scratch_reg;
1882         int i;
1883
1884         if (rdev->family >= CHIP_R600)
1885                 scratch_reg = R600_BIOS_0_SCRATCH;
1886         else
1887                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1888
1889         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1890                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1891 }
1892
1893 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1894 {
1895         uint32_t scratch_reg;
1896         int i;
1897
1898         if (rdev->family >= CHIP_R600)
1899                 scratch_reg = R600_BIOS_0_SCRATCH;
1900         else
1901                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1902
1903         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1904                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1905 }
1906
1907 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1908 {
1909         struct drm_device *dev = encoder->dev;
1910         struct radeon_device *rdev = dev->dev_private;
1911         uint32_t bios_6_scratch;
1912
1913         if (rdev->family >= CHIP_R600)
1914                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1915         else
1916                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1917
1918         if (lock)
1919                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1920         else
1921                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1922
1923         if (rdev->family >= CHIP_R600)
1924                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1925         else
1926                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1927 }
1928
1929 /* at some point we may want to break this out into individual functions */
1930 void
1931 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1932                                        struct drm_encoder *encoder,
1933                                        bool connected)
1934 {
1935         struct drm_device *dev = connector->dev;
1936         struct radeon_device *rdev = dev->dev_private;
1937         struct radeon_connector *radeon_connector =
1938             to_radeon_connector(connector);
1939         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1940         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1941
1942         if (rdev->family >= CHIP_R600) {
1943                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1944                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1945                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1946         } else {
1947                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1948                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1949                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1950         }
1951
1952         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1953             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1954                 if (connected) {
1955                         DRM_DEBUG("TV1 connected\n");
1956                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1957                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1958                 } else {
1959                         DRM_DEBUG("TV1 disconnected\n");
1960                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1961                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1962                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1963                 }
1964         }
1965         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1966             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1967                 if (connected) {
1968                         DRM_DEBUG("CV connected\n");
1969                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1970                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1971                 } else {
1972                         DRM_DEBUG("CV disconnected\n");
1973                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1974                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1975                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1976                 }
1977         }
1978         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1979             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1980                 if (connected) {
1981                         DRM_DEBUG("LCD1 connected\n");
1982                         bios_0_scratch |= ATOM_S0_LCD1;
1983                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1984                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1985                 } else {
1986                         DRM_DEBUG("LCD1 disconnected\n");
1987                         bios_0_scratch &= ~ATOM_S0_LCD1;
1988                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1989                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1990                 }
1991         }
1992         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1993             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1994                 if (connected) {
1995                         DRM_DEBUG("CRT1 connected\n");
1996                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1997                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1998                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1999                 } else {
2000                         DRM_DEBUG("CRT1 disconnected\n");
2001                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2002                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2003                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2004                 }
2005         }
2006         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2007             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2008                 if (connected) {
2009                         DRM_DEBUG("CRT2 connected\n");
2010                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2011                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2012                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2013                 } else {
2014                         DRM_DEBUG("CRT2 disconnected\n");
2015                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2016                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2017                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2018                 }
2019         }
2020         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2021             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2022                 if (connected) {
2023                         DRM_DEBUG("DFP1 connected\n");
2024                         bios_0_scratch |= ATOM_S0_DFP1;
2025                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2026                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2027                 } else {
2028                         DRM_DEBUG("DFP1 disconnected\n");
2029                         bios_0_scratch &= ~ATOM_S0_DFP1;
2030                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2031                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2032                 }
2033         }
2034         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2035             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2036                 if (connected) {
2037                         DRM_DEBUG("DFP2 connected\n");
2038                         bios_0_scratch |= ATOM_S0_DFP2;
2039                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2040                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2041                 } else {
2042                         DRM_DEBUG("DFP2 disconnected\n");
2043                         bios_0_scratch &= ~ATOM_S0_DFP2;
2044                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2045                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2046                 }
2047         }
2048         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2049             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2050                 if (connected) {
2051                         DRM_DEBUG("DFP3 connected\n");
2052                         bios_0_scratch |= ATOM_S0_DFP3;
2053                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2054                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2055                 } else {
2056                         DRM_DEBUG("DFP3 disconnected\n");
2057                         bios_0_scratch &= ~ATOM_S0_DFP3;
2058                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2059                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2060                 }
2061         }
2062         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2063             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2064                 if (connected) {
2065                         DRM_DEBUG("DFP4 connected\n");
2066                         bios_0_scratch |= ATOM_S0_DFP4;
2067                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2068                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2069                 } else {
2070                         DRM_DEBUG("DFP4 disconnected\n");
2071                         bios_0_scratch &= ~ATOM_S0_DFP4;
2072                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2073                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2074                 }
2075         }
2076         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2077             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2078                 if (connected) {
2079                         DRM_DEBUG("DFP5 connected\n");
2080                         bios_0_scratch |= ATOM_S0_DFP5;
2081                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2082                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2083                 } else {
2084                         DRM_DEBUG("DFP5 disconnected\n");
2085                         bios_0_scratch &= ~ATOM_S0_DFP5;
2086                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2087                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2088                 }
2089         }
2090
2091         if (rdev->family >= CHIP_R600) {
2092                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2093                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2094                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2095         } else {
2096                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2097                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2098                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2099         }
2100 }
2101
2102 void
2103 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2104 {
2105         struct drm_device *dev = encoder->dev;
2106         struct radeon_device *rdev = dev->dev_private;
2107         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2108         uint32_t bios_3_scratch;
2109
2110         if (rdev->family >= CHIP_R600)
2111                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2112         else
2113                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2114
2115         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2116                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2117                 bios_3_scratch |= (crtc << 18);
2118         }
2119         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2120                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2121                 bios_3_scratch |= (crtc << 24);
2122         }
2123         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2124                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2125                 bios_3_scratch |= (crtc << 16);
2126         }
2127         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2128                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2129                 bios_3_scratch |= (crtc << 20);
2130         }
2131         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2132                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2133                 bios_3_scratch |= (crtc << 17);
2134         }
2135         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2136                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2137                 bios_3_scratch |= (crtc << 19);
2138         }
2139         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2140                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2141                 bios_3_scratch |= (crtc << 23);
2142         }
2143         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2144                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2145                 bios_3_scratch |= (crtc << 25);
2146         }
2147
2148         if (rdev->family >= CHIP_R600)
2149                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2150         else
2151                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2152 }
2153
2154 void
2155 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2156 {
2157         struct drm_device *dev = encoder->dev;
2158         struct radeon_device *rdev = dev->dev_private;
2159         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2160         uint32_t bios_2_scratch;
2161
2162         if (rdev->family >= CHIP_R600)
2163                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2164         else
2165                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2166
2167         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2168                 if (on)
2169                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2170                 else
2171                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2172         }
2173         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2174                 if (on)
2175                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2176                 else
2177                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2178         }
2179         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2180                 if (on)
2181                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2182                 else
2183                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2184         }
2185         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2186                 if (on)
2187                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2188                 else
2189                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2190         }
2191         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2192                 if (on)
2193                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2194                 else
2195                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2196         }
2197         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2198                 if (on)
2199                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2200                 else
2201                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2202         }
2203         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2204                 if (on)
2205                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2206                 else
2207                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2208         }
2209         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2210                 if (on)
2211                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2212                 else
2213                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2214         }
2215         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2216                 if (on)
2217                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2218                 else
2219                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2220         }
2221         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2222                 if (on)
2223                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2224                 else
2225                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2226         }
2227
2228         if (rdev->family >= CHIP_R600)
2229                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2230         else
2231                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2232 }