SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info);
  50
  51 /* from radeon_legacy_encoder.c */
  52 extern void
  53 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  54                           uint32_t supported_device);
  55
  56 union atom_supported_devices {
  57         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  58         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  59         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  60 };
  61
  62 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
  63                                                            *dev, uint8_t id)
  64 {
  65         struct radeon_device *rdev = dev->dev_private;
  66         struct atom_context *ctx = rdev->mode_info.atom_context;
  67         ATOM_GPIO_I2C_ASSIGMENT gpio;
  68         struct radeon_i2c_bus_rec i2c;
  69         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  70         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  71         uint16_t data_offset;
  72
  73         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  74         i2c.valid = false;
  75
  76         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  77
  78         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  79
  80         gpio = i2c_info->asGPIO_Info[id];
  81
  82         i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  83         i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  84         i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  85         i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  86         i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  87         i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  88         i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
  89         i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
  90         i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  91         i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  92         i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  93         i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  94         i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  95         i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
  96         i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
  97         i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
  98         i2c.valid = true;
  99
 100         return i2c;
 101 }
 102
 103 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 104                                      uint32_t supported_device,
 105                                      int *connector_type,
 106                                      struct radeon_i2c_bus_rec *i2c_bus,
 107                                      uint8_t *line_mux)
 108 {
 109
 110         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 111         if ((dev->pdev->device == 0x791e) &&
 112             (dev->pdev->subsystem_vendor == 0x1043) &&
 113             (dev->pdev->subsystem_device == 0x826d)) {
 114                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 115                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 116                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 117         }
 118
 119         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 120         if ((dev->pdev->device == 0x7941) &&
 121             (dev->pdev->subsystem_vendor == 0x147b) &&
 122             (dev->pdev->subsystem_device == 0x2412)) {
 123                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 124                         return false;
 125         }
 126
 127         /* Falcon NW laptop lists vga ddc line for LVDS */
 128         if ((dev->pdev->device == 0x5653) &&
 129             (dev->pdev->subsystem_vendor == 0x1462) &&
 130             (dev->pdev->subsystem_device == 0x0291)) {
 131                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 132                         i2c_bus->valid = false;
 133                         *line_mux = 53;
 134                 }
 135         }
 136
 137         /* Funky macbooks */
 138         if ((dev->pdev->device == 0x71C5) &&
 139             (dev->pdev->subsystem_vendor == 0x106b) &&
 140             (dev->pdev->subsystem_device == 0x0080)) {
 141                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 142                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 143                         return false;
 144         }
 145
 146         /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
 147         if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
 148             (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
 149                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 150                         return false;
 151                 }
 152         }
 153
 154         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 155         if ((dev->pdev->device == 0x9598) &&
 156             (dev->pdev->subsystem_vendor == 0x1043) &&
 157             (dev->pdev->subsystem_device == 0x01da)) {
 158                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
 159                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 160                 }
 161         }
 162
 163         return true;
 164 }
 165
 166 const int supported_devices_connector_convert[] = {
 167         DRM_MODE_CONNECTOR_Unknown,
 168         DRM_MODE_CONNECTOR_VGA,
 169         DRM_MODE_CONNECTOR_DVII,
 170         DRM_MODE_CONNECTOR_DVID,
 171         DRM_MODE_CONNECTOR_DVIA,
 172         DRM_MODE_CONNECTOR_SVIDEO,
 173         DRM_MODE_CONNECTOR_Composite,
 174         DRM_MODE_CONNECTOR_LVDS,
 175         DRM_MODE_CONNECTOR_Unknown,
 176         DRM_MODE_CONNECTOR_Unknown,
 177         DRM_MODE_CONNECTOR_HDMIA,
 178         DRM_MODE_CONNECTOR_HDMIB,
 179         DRM_MODE_CONNECTOR_Unknown,
 180         DRM_MODE_CONNECTOR_Unknown,
 181         DRM_MODE_CONNECTOR_9PinDIN,
 182         DRM_MODE_CONNECTOR_DisplayPort
 183 };
 184
 185 const int object_connector_convert[] = {
 186         DRM_MODE_CONNECTOR_Unknown,
 187         DRM_MODE_CONNECTOR_DVII,
 188         DRM_MODE_CONNECTOR_DVII,
 189         DRM_MODE_CONNECTOR_DVID,
 190         DRM_MODE_CONNECTOR_DVID,
 191         DRM_MODE_CONNECTOR_VGA,
 192         DRM_MODE_CONNECTOR_Composite,
 193         DRM_MODE_CONNECTOR_SVIDEO,
 194         DRM_MODE_CONNECTOR_Unknown,
 195         DRM_MODE_CONNECTOR_9PinDIN,
 196         DRM_MODE_CONNECTOR_Unknown,
 197         DRM_MODE_CONNECTOR_HDMIA,
 198         DRM_MODE_CONNECTOR_HDMIB,
 199         DRM_MODE_CONNECTOR_HDMIB,
 200         DRM_MODE_CONNECTOR_LVDS,
 201         DRM_MODE_CONNECTOR_9PinDIN,
 202         DRM_MODE_CONNECTOR_Unknown,
 203         DRM_MODE_CONNECTOR_Unknown,
 204         DRM_MODE_CONNECTOR_Unknown,
 205         DRM_MODE_CONNECTOR_DisplayPort
 206 };
 207
 208 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 209 {
 210         struct radeon_device *rdev = dev->dev_private;
 211         struct radeon_mode_info *mode_info = &rdev->mode_info;
 212         struct atom_context *ctx = mode_info->atom_context;
 213         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 214         uint16_t size, data_offset;
 215         uint8_t frev, crev, line_mux = 0;
 216         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 217         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 218         ATOM_OBJECT_HEADER *obj_header;
 219         int i, j, path_size, device_support;
 220         int connector_type;
 221         uint16_t igp_lane_info;
 222         bool linkb;
 223         struct radeon_i2c_bus_rec ddc_bus;
 224
 225         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 226
 227         if (data_offset == 0)
 228                 return false;
 229
 230         if (crev < 2)
 231                 return false;
 232
 233         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 234         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 235             (ctx->bios + data_offset +
 236              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 237         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 238             (ctx->bios + data_offset +
 239              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 240         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 241
 242         path_size = 0;
 243         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 244                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 245                 ATOM_DISPLAY_OBJECT_PATH *path;
 246                 addr += path_size;
 247                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 248                 path_size += le16_to_cpu(path->usSize);
 249                 linkb = false;
 250
 251                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 252                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 253
 254                         con_obj_id =
 255                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 256                             >> OBJECT_ID_SHIFT;
 257                         con_obj_num =
 258                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 259                             >> ENUM_ID_SHIFT;
 260                         con_obj_type =
 261                             (le16_to_cpu(path->usConnObjectId) &
 262                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 263
 264                         if ((le16_to_cpu(path->usDeviceTag) ==
 265                              ATOM_DEVICE_TV1_SUPPORT)
 266                             || (le16_to_cpu(path->usDeviceTag) ==
 267                                 ATOM_DEVICE_TV2_SUPPORT)
 268                             || (le16_to_cpu(path->usDeviceTag) ==
 269                                 ATOM_DEVICE_CV_SUPPORT))
 270                                 continue;
 271
 272                         if ((rdev->family == CHIP_RS780) &&
 273                             (con_obj_id ==
 274                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 275                                 uint16_t igp_offset = 0;
 276                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 277
 278                                 index =
 279                                     GetIndexIntoMasterTable(DATA,
 280                                                             IntegratedSystemInfo);
 281
 282                                 atom_parse_data_header(ctx, index, &size, &frev,
 283                                                        &crev, &igp_offset);
 284
 285                                 if (crev >= 2) {
 286                                         igp_obj =
 287                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 288                                              *) (ctx->bios + igp_offset);
 289
 290                                         if (igp_obj) {
 291                                                 uint32_t slot_config, ct;
 292
 293                                                 if (con_obj_num == 1)
 294                                                         slot_config =
 295                                                             igp_obj->
 296                                                             ulDDISlot1Config;
 297                                                 else
 298                                                         slot_config =
 299                                                             igp_obj->
 300                                                             ulDDISlot2Config;
 301
 302                                                 ct = (slot_config >> 16) & 0xff;
 303                                                 connector_type =
 304                                                     object_connector_convert
 305                                                     [ct];
 306                                                 igp_lane_info =
 307                                                     slot_config & 0xffff;
 308                                         } else
 309                                                 continue;
 310                                 } else
 311                                         continue;
 312                         } else {
 313                                 igp_lane_info = 0;
 314                                 connector_type =
 315                                     object_connector_convert[con_obj_id];
 316                         }
 317
 318                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 319                                 continue;
 320
 321                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 322                              j++) {
 323                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 324
 325                                 enc_obj_id =
 326                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 327                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 328                                 enc_obj_num =
 329                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 330                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 331                                 enc_obj_type =
 332                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 333                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 334
 335                                 /* FIXME: add support for router objects */
 336                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 337                                         if (enc_obj_num == 2)
 338                                                 linkb = true;
 339                                         else
 340                                                 linkb = false;
 341
 342                                         radeon_add_atom_encoder(dev,
 343                                                                 enc_obj_id,
 344                                                                 le16_to_cpu
 345                                                                 (path->
 346                                                                  usDeviceTag));
 347
 348                                 }
 349                         }
 350
 351                         /* look up gpio for ddc */
 352                         if ((le16_to_cpu(path->usDeviceTag) &
 353                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
 354                             == 0) {
 355                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 356                                         if (le16_to_cpu(path->usConnObjectId) ==
 357                                             le16_to_cpu(con_obj->asObjects[j].
 358                                                         usObjectID)) {
 359                                                 ATOM_COMMON_RECORD_HEADER
 360                                                     *record =
 361                                                     (ATOM_COMMON_RECORD_HEADER
 362                                                      *)
 363                                                     (ctx->bios + data_offset +
 364                                                      le16_to_cpu(con_obj->
 365                                                                  asObjects[j].
 366                                                                  usRecordOffset));
 367                                                 ATOM_I2C_RECORD *i2c_record;
 368
 369                                                 while (record->ucRecordType > 0
 370                                                        && record->
 371                                                        ucRecordType <=
 372                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 373                                                         DRM_ERROR
 374                                                             ("record type %d\n",
 375                                                              record->
 376                                                              ucRecordType);
 377                                                         switch (record->
 378                                                                 ucRecordType) {
 379                                                         case ATOM_I2C_RECORD_TYPE:
 380                                                                 i2c_record =
 381                                                                     (ATOM_I2C_RECORD
 382                                                                      *) record;
 383                                                                 line_mux =
 384                                                                     i2c_record->
 385                                                                     sucI2cId.
 386                                                                     bfI2C_LineMux;
 387                                                                 break;
 388                                                         }
 389                                                         record =
 390                                                             (ATOM_COMMON_RECORD_HEADER
 391                                                              *) ((char *)record
 392                                                                  +
 393                                                                  record->
 394                                                                  ucRecordSize);
 395                                                 }
 396                                                 break;
 397                                         }
 398                                 }
 399                         } else
 400                                 line_mux = 0;
 401
 402                         if ((le16_to_cpu(path->usDeviceTag) ==
 403                              ATOM_DEVICE_TV1_SUPPORT)
 404                             || (le16_to_cpu(path->usDeviceTag) ==
 405                                 ATOM_DEVICE_TV2_SUPPORT)
 406                             || (le16_to_cpu(path->usDeviceTag) ==
 407                                 ATOM_DEVICE_CV_SUPPORT))
 408                                 ddc_bus.valid = false;
 409                         else
 410                                 ddc_bus = radeon_lookup_gpio(dev, line_mux);
 411
 412                         radeon_add_atom_connector(dev,
 413                                                   le16_to_cpu(path->
 414                                                               usConnObjectId),
 415                                                   le16_to_cpu(path->
 416                                                               usDeviceTag),
 417                                                   connector_type, &ddc_bus,
 418                                                   linkb, igp_lane_info);
 419
 420                 }
 421         }
 422
 423         radeon_link_encoder_connector(dev);
 424
 425         return true;
 426 }
 427
 428 struct bios_connector {
 429         bool valid;
 430         uint8_t line_mux;
 431         uint16_t devices;
 432         int connector_type;
 433         struct radeon_i2c_bus_rec ddc_bus;
 434 };
 435
 436 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 437                                                                  drm_device
 438                                                                  *dev)
 439 {
 440         struct radeon_device *rdev = dev->dev_private;
 441         struct radeon_mode_info *mode_info = &rdev->mode_info;
 442         struct atom_context *ctx = mode_info->atom_context;
 443         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 444         uint16_t size, data_offset;
 445         uint8_t frev, crev;
 446         uint16_t device_support;
 447         uint8_t dac;
 448         union atom_supported_devices *supported_devices;
 449         int i, j;
 450         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 451
 452         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 453
 454         supported_devices =
 455             (union atom_supported_devices *)(ctx->bios + data_offset);
 456
 457         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 458
 459         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 460                 ATOM_CONNECTOR_INFO_I2C ci =
 461                     supported_devices->info.asConnInfo[i];
 462
 463                 bios_connectors[i].valid = false;
 464
 465                 if (!(device_support & (1 << i))) {
 466                         continue;
 467                 }
 468
 469                 if (i == ATOM_DEVICE_CV_INDEX) {
 470                         DRM_DEBUG("Skipping Component Video\n");
 471                         continue;
 472                 }
 473
 474                 bios_connectors[i].connector_type =
 475                     supported_devices_connector_convert[ci.sucConnectorInfo.
 476                                                         sbfAccess.
 477                                                         bfConnectorType];
 478
 479                 if (bios_connectors[i].connector_type ==
 480                     DRM_MODE_CONNECTOR_Unknown)
 481                         continue;
 482
 483                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 484
 485                 if ((rdev->family == CHIP_RS690) ||
 486                     (rdev->family == CHIP_RS740)) {
 487                         if ((i == ATOM_DEVICE_DFP2_INDEX)
 488                             && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
 489                                 bios_connectors[i].line_mux =
 490                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 491                         else if ((i == ATOM_DEVICE_DFP3_INDEX)
 492                                  && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
 493                                 bios_connectors[i].line_mux =
 494                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 495                         else
 496                                 bios_connectors[i].line_mux =
 497                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 498                 } else
 499                         bios_connectors[i].line_mux =
 500                             ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 501
 502                 /* give tv unique connector ids */
 503                 if (i == ATOM_DEVICE_TV1_INDEX) {
 504                         bios_connectors[i].ddc_bus.valid = false;
 505                         bios_connectors[i].line_mux = 50;
 506                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 507                         bios_connectors[i].ddc_bus.valid = false;
 508                         bios_connectors[i].line_mux = 51;
 509                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 510                         bios_connectors[i].ddc_bus.valid = false;
 511                         bios_connectors[i].line_mux = 52;
 512                 } else
 513                         bios_connectors[i].ddc_bus =
 514                             radeon_lookup_gpio(dev,
 515                                                bios_connectors[i].line_mux);
 516
 517                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 518                  * shared with a DVI port, we'll pick up the DVI connector when we
 519                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 520                  */
 521                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 522                         bios_connectors[i].connector_type =
 523                             DRM_MODE_CONNECTOR_VGA;
 524
 525                 if (!radeon_atom_apply_quirks
 526                     (dev, (1 << i), &bios_connectors[i].connector_type,
 527                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
 528                         continue;
 529
 530                 bios_connectors[i].valid = true;
 531                 bios_connectors[i].devices = (1 << i);
 532
 533                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 534                         radeon_add_atom_encoder(dev,
 535                                                 radeon_get_encoder_id(dev,
 536                                                                       (1 << i),
 537                                                                       dac),
 538                                                 (1 << i));
 539                 else
 540                         radeon_add_legacy_encoder(dev,
 541                                                   radeon_get_encoder_id(dev,
 542                                                                         (1 <<
 543                                                                          i),
 544                                                                         dac),
 545                                                   (1 << i));
 546         }
 547
 548         /* combine shared connectors */
 549         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 550                 if (bios_connectors[i].valid) {
 551                         for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
 552                                 if (bios_connectors[j].valid && (i != j)) {
 553                                         if (bios_connectors[i].line_mux ==
 554                                             bios_connectors[j].line_mux) {
 555                                                 if (((bios_connectors[i].
 556                                                       devices &
 557                                                       (ATOM_DEVICE_DFP_SUPPORT))
 558                                                      && (bios_connectors[j].
 559                                                          devices &
 560                                                          (ATOM_DEVICE_CRT_SUPPORT)))
 561                                                     ||
 562                                                     ((bios_connectors[j].
 563                                                       devices &
 564                                                       (ATOM_DEVICE_DFP_SUPPORT))
 565                                                      && (bios_connectors[i].
 566                                                          devices &
 567                                                          (ATOM_DEVICE_CRT_SUPPORT)))) {
 568                                                         bios_connectors[i].
 569                                                             devices |=
 570                                                             bios_connectors[j].
 571                                                             devices;
 572                                                         bios_connectors[i].
 573                                                             connector_type =
 574                                                             DRM_MODE_CONNECTOR_DVII;
 575                                                         bios_connectors[j].
 576                                                             valid = false;
 577                                                 }
 578                                         }
 579                                 }
 580                         }
 581                 }
 582         }
 583
 584         /* add the connectors */
 585         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 586                 if (bios_connectors[i].valid)
 587                         radeon_add_atom_connector(dev,
 588                                                   bios_connectors[i].line_mux,
 589                                                   bios_connectors[i].devices,
 590                                                   bios_connectors[i].
 591                                                   connector_type,
 592                                                   &bios_connectors[i].ddc_bus,
 593                                                   false, 0);
 594         }
 595
 596         radeon_link_encoder_connector(dev);
 597
 598         return true;
 599 }
 600
 601 union firmware_info {
 602         ATOM_FIRMWARE_INFO info;
 603         ATOM_FIRMWARE_INFO_V1_2 info_12;
 604         ATOM_FIRMWARE_INFO_V1_3 info_13;
 605         ATOM_FIRMWARE_INFO_V1_4 info_14;
 606 };
 607
 608 bool radeon_atom_get_clock_info(struct drm_device *dev)
 609 {
 610         struct radeon_device *rdev = dev->dev_private;
 611         struct radeon_mode_info *mode_info = &rdev->mode_info;
 612         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 613         union firmware_info *firmware_info;
 614         uint8_t frev, crev;
 615         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 616         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 617         struct radeon_pll *spll = &rdev->clock.spll;
 618         struct radeon_pll *mpll = &rdev->clock.mpll;
 619         uint16_t data_offset;
 620
 621         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 622                                &crev, &data_offset);
 623
 624         firmware_info =
 625             (union firmware_info *)(mode_info->atom_context->bios +
 626                                     data_offset);
 627
 628         if (firmware_info) {
 629                 /* pixel clocks */
 630                 p1pll->reference_freq =
 631                     le16_to_cpu(firmware_info->info.usReferenceClock);
 632                 p1pll->reference_div = 0;
 633
 634                 p1pll->pll_out_min =
 635                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 636                 p1pll->pll_out_max =
 637                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 638
 639                 if (p1pll->pll_out_min == 0) {
 640                         if (ASIC_IS_AVIVO(rdev))
 641                                 p1pll->pll_out_min = 64800;
 642                         else
 643                                 p1pll->pll_out_min = 20000;
 644                 }
 645
 646                 p1pll->pll_in_min =
 647                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 648                 p1pll->pll_in_max =
 649                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 650
 651                 *p2pll = *p1pll;
 652
 653                 /* system clock */
 654                 spll->reference_freq =
 655                     le16_to_cpu(firmware_info->info.usReferenceClock);
 656                 spll->reference_div = 0;
 657
 658                 spll->pll_out_min =
 659                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 660                 spll->pll_out_max =
 661                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 662
 663                 /* ??? */
 664                 if (spll->pll_out_min == 0) {
 665                         if (ASIC_IS_AVIVO(rdev))
 666                                 spll->pll_out_min = 64800;
 667                         else
 668                                 spll->pll_out_min = 20000;
 669                 }
 670
 671                 spll->pll_in_min =
 672                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 673                 spll->pll_in_max =
 674                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 675
 676                 /* memory clock */
 677                 mpll->reference_freq =
 678                     le16_to_cpu(firmware_info->info.usReferenceClock);
 679                 mpll->reference_div = 0;
 680
 681                 mpll->pll_out_min =
 682                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 683                 mpll->pll_out_max =
 684                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 685
 686                 /* ??? */
 687                 if (mpll->pll_out_min == 0) {
 688                         if (ASIC_IS_AVIVO(rdev))
 689                                 mpll->pll_out_min = 64800;
 690                         else
 691                                 mpll->pll_out_min = 20000;
 692                 }
 693
 694                 mpll->pll_in_min =
 695                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 696                 mpll->pll_in_max =
 697                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 698
 699                 rdev->clock.default_sclk =
 700                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 701                 rdev->clock.default_mclk =
 702                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 703
 704                 return true;
 705         }
 706         return false;
 707 }
 708
 709 struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
 710                                                               radeon_encoder
 711                                                               *encoder)
 712 {
 713         struct drm_device *dev = encoder->base.dev;
 714         struct radeon_device *rdev = dev->dev_private;
 715         struct radeon_mode_info *mode_info = &rdev->mode_info;
 716         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 717         uint16_t data_offset;
 718         struct _ATOM_TMDS_INFO *tmds_info;
 719         uint8_t frev, crev;
 720         uint16_t maxfreq;
 721         int i;
 722         struct radeon_encoder_int_tmds *tmds = NULL;
 723
 724         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 725                                &crev, &data_offset);
 726
 727         tmds_info =
 728             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 729                                        data_offset);
 730
 731         if (tmds_info) {
 732                 tmds =
 733                     kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
 734
 735                 if (!tmds)
 736                         return NULL;
 737
 738                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 739                 for (i = 0; i < 4; i++) {
 740                         tmds->tmds_pll[i].freq =
 741                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
 742                         tmds->tmds_pll[i].value =
 743                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
 744                         tmds->tmds_pll[i].value |=
 745                             (tmds_info->asMiscInfo[i].
 746                              ucPLL_VCO_Gain & 0x3f) << 6;
 747                         tmds->tmds_pll[i].value |=
 748                             (tmds_info->asMiscInfo[i].
 749                              ucPLL_DutyCycle & 0xf) << 12;
 750                         tmds->tmds_pll[i].value |=
 751                             (tmds_info->asMiscInfo[i].
 752                              ucPLL_VoltageSwing & 0xf) << 16;
 753
 754                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
 755                                   tmds->tmds_pll[i].freq,
 756                                   tmds->tmds_pll[i].value);
 757
 758                         if (maxfreq == tmds->tmds_pll[i].freq) {
 759                                 tmds->tmds_pll[i].freq = 0xffffffff;
 760                                 break;
 761                         }
 762                 }
 763         }
 764         return tmds;
 765 }
 766
 767 union lvds_info {
 768         struct _ATOM_LVDS_INFO info;
 769         struct _ATOM_LVDS_INFO_V12 info_12;
 770 };
 771
 772 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
 773                                                               radeon_encoder
 774                                                               *encoder)
 775 {
 776         struct drm_device *dev = encoder->base.dev;
 777         struct radeon_device *rdev = dev->dev_private;
 778         struct radeon_mode_info *mode_info = &rdev->mode_info;
 779         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
 780         uint16_t data_offset;
 781         union lvds_info *lvds_info;
 782         uint8_t frev, crev;
 783         struct radeon_encoder_atom_dig *lvds = NULL;
 784
 785         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 786                                &crev, &data_offset);
 787
 788         lvds_info =
 789             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
 790
 791         if (lvds_info) {
 792                 lvds =
 793                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 794
 795                 if (!lvds)
 796                         return NULL;
 797
 798                 lvds->native_mode.dotclock =
 799                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
 800                 lvds->native_mode.panel_xres =
 801                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
 802                 lvds->native_mode.panel_yres =
 803                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
 804                 lvds->native_mode.hblank =
 805                     le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
 806                 lvds->native_mode.hoverplus =
 807                     le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
 808                 lvds->native_mode.hsync_width =
 809                     le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
 810                 lvds->native_mode.vblank =
 811                     le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
 812                 lvds->native_mode.voverplus =
 813                     le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
 814                 lvds->native_mode.vsync_width =
 815                     le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
 816                 lvds->panel_pwr_delay =
 817                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
 818                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
 819
 820                 encoder->native_mode = lvds->native_mode;
 821         }
 822         return lvds;
 823 }
 824
 825 struct radeon_encoder_primary_dac *
 826 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
 827 {
 828         struct drm_device *dev = encoder->base.dev;
 829         struct radeon_device *rdev = dev->dev_private;
 830         struct radeon_mode_info *mode_info = &rdev->mode_info;
 831         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
 832         uint16_t data_offset;
 833         struct _COMPASSIONATE_DATA *dac_info;
 834         uint8_t frev, crev;
 835         uint8_t bg, dac;
 836         struct radeon_encoder_primary_dac *p_dac = NULL;
 837
 838         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 839
 840         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
 841
 842         if (dac_info) {
 843                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
 844
 845                 if (!p_dac)
 846                         return NULL;
 847
 848                 bg = dac_info->ucDAC1_BG_Adjustment;
 849                 dac = dac_info->ucDAC1_DAC_Adjustment;
 850                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 851
 852         }
 853         return p_dac;
 854 }
 855
 856 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 857                                 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
 858                                 int32_t *pixel_clock)
 859 {
 860         struct radeon_mode_info *mode_info = &rdev->mode_info;
 861         ATOM_ANALOG_TV_INFO *tv_info;
 862         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
 863         ATOM_DTD_FORMAT *dtd_timings;
 864         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
 865         u8 frev, crev;
 866         uint16_t data_offset;
 867
 868         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
 869
 870         switch (crev) {
 871         case 1:
 872                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
 873                 if (index > MAX_SUPPORTED_TV_TIMING)
 874                         return false;
 875
 876                 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
 877                 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
 878                 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
 879                 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
 880
 881                 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
 882                 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
 883                 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
 884                 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
 885
 886                 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
 887
 888                 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
 889                 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
 890                 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
 891                 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
 892                 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
 893
 894                 if (index == 1) {
 895                         /* PAL timings appear to have wrong values for totals */
 896                         crtc_timing->usH_Total -= 1;
 897                         crtc_timing->usV_Total -= 1;
 898                 }
 899                 break;
 900         case 2:
 901                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
 902                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
 903                         return false;
 904
 905                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
 906                 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
 907                 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
 908                 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
 909                 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
 910                 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
 911                 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
 912                 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
 913                 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
 914
 915                 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
 916                 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
 917                 break;
 918         }
 919         return true;
 920 }
 921
 922 struct radeon_encoder_tv_dac *
 923 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
 924 {
 925         struct drm_device *dev = encoder->base.dev;
 926         struct radeon_device *rdev = dev->dev_private;
 927         struct radeon_mode_info *mode_info = &rdev->mode_info;
 928         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
 929         uint16_t data_offset;
 930         struct _COMPASSIONATE_DATA *dac_info;
 931         uint8_t frev, crev;
 932         uint8_t bg, dac;
 933         struct radeon_encoder_tv_dac *tv_dac = NULL;
 934
 935         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 936
 937         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
 938
 939         if (dac_info) {
 940                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 941
 942                 if (!tv_dac)
 943                         return NULL;
 944
 945                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
 946                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
 947                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 948
 949                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
 950                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
 951                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 952
 953                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
 954                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
 955                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 956
 957         }
 958         return tv_dac;
 959 }
 960
 961 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
 962 {
 963         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
 964         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
 965
 966         args.ucEnable = enable;
 967
 968         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 969 }
 970
 971 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
 972 {
 973         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
 974         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
 975
 976         args.ucEnable = enable;
 977
 978         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 979 }
 980
 981 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
 982                                   uint32_t eng_clock)
 983 {
 984         SET_ENGINE_CLOCK_PS_ALLOCATION args;
 985         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
 986
 987         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
 988
 989         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 990 }
 991
 992 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
 993                                   uint32_t mem_clock)
 994 {
 995         SET_MEMORY_CLOCK_PS_ALLOCATION args;
 996         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
 997
 998         if (rdev->flags & RADEON_IS_IGP)
 999                 return;
1000
1001         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1002
1003         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1004 }
1005
1006 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1007 {
1008         struct radeon_device *rdev = dev->dev_private;
1009         uint32_t bios_2_scratch, bios_6_scratch;
1010
1011         if (rdev->family >= CHIP_R600) {
1012                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1013                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1014         } else {
1015                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1016                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1017         }
1018
1019         /* let the bios control the backlight */
1020         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1021
1022         /* tell the bios not to handle mode switching */
1023         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1024
1025         if (rdev->family >= CHIP_R600) {
1026                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1027                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1028         } else {
1029                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1030                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1031         }
1032
1033 }
1034
1035 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1036 {
1037         struct drm_device *dev = encoder->dev;
1038         struct radeon_device *rdev = dev->dev_private;
1039         uint32_t bios_6_scratch;
1040
1041         if (rdev->family >= CHIP_R600)
1042                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1043         else
1044                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1045
1046         if (lock)
1047                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1048         else
1049                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1050
1051         if (rdev->family >= CHIP_R600)
1052                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1053         else
1054                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1055 }
1056
1057 /* at some point we may want to break this out into individual functions */
1058 void
1059 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1060                                        struct drm_encoder *encoder,
1061                                        bool connected)
1062 {
1063         struct drm_device *dev = connector->dev;
1064         struct radeon_device *rdev = dev->dev_private;
1065         struct radeon_connector *radeon_connector =
1066             to_radeon_connector(connector);
1067         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1068         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1069
1070         if (rdev->family >= CHIP_R600) {
1071                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1072                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1073                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1074         } else {
1075                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1076                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1077                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1078         }
1079
1080         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1081             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1082                 if (connected) {
1083                         DRM_DEBUG("TV1 connected\n");
1084                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1085                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1086                 } else {
1087                         DRM_DEBUG("TV1 disconnected\n");
1088                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1089                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1090                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1091                 }
1092         }
1093         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1094             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1095                 if (connected) {
1096                         DRM_DEBUG("CV connected\n");
1097                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1098                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1099                 } else {
1100                         DRM_DEBUG("CV disconnected\n");
1101                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1102                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1103                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1104                 }
1105         }
1106         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1107             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1108                 if (connected) {
1109                         DRM_DEBUG("LCD1 connected\n");
1110                         bios_0_scratch |= ATOM_S0_LCD1;
1111                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1112                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1113                 } else {
1114                         DRM_DEBUG("LCD1 disconnected\n");
1115                         bios_0_scratch &= ~ATOM_S0_LCD1;
1116                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1117                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1118                 }
1119         }
1120         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1121             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1122                 if (connected) {
1123                         DRM_DEBUG("CRT1 connected\n");
1124                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1125                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1126                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1127                 } else {
1128                         DRM_DEBUG("CRT1 disconnected\n");
1129                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1130                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1131                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1132                 }
1133         }
1134         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1135             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1136                 if (connected) {
1137                         DRM_DEBUG("CRT2 connected\n");
1138                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1139                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1140                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1141                 } else {
1142                         DRM_DEBUG("CRT2 disconnected\n");
1143                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1144                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1145                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1146                 }
1147         }
1148         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1149             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1150                 if (connected) {
1151                         DRM_DEBUG("DFP1 connected\n");
1152                         bios_0_scratch |= ATOM_S0_DFP1;
1153                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1154                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1155                 } else {
1156                         DRM_DEBUG("DFP1 disconnected\n");
1157                         bios_0_scratch &= ~ATOM_S0_DFP1;
1158                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1159                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1160                 }
1161         }
1162         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1163             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1164                 if (connected) {
1165                         DRM_DEBUG("DFP2 connected\n");
1166                         bios_0_scratch |= ATOM_S0_DFP2;
1167                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1168                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1169                 } else {
1170                         DRM_DEBUG("DFP2 disconnected\n");
1171                         bios_0_scratch &= ~ATOM_S0_DFP2;
1172                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1173                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1174                 }
1175         }
1176         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1177             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1178                 if (connected) {
1179                         DRM_DEBUG("DFP3 connected\n");
1180                         bios_0_scratch |= ATOM_S0_DFP3;
1181                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1182                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1183                 } else {
1184                         DRM_DEBUG("DFP3 disconnected\n");
1185                         bios_0_scratch &= ~ATOM_S0_DFP3;
1186                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1187                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1188                 }
1189         }
1190         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1191             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1192                 if (connected) {
1193                         DRM_DEBUG("DFP4 connected\n");
1194                         bios_0_scratch |= ATOM_S0_DFP4;
1195                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1196                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1197                 } else {
1198                         DRM_DEBUG("DFP4 disconnected\n");
1199                         bios_0_scratch &= ~ATOM_S0_DFP4;
1200                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1201                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1202                 }
1203         }
1204         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1205             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1206                 if (connected) {
1207                         DRM_DEBUG("DFP5 connected\n");
1208                         bios_0_scratch |= ATOM_S0_DFP5;
1209                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1210                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1211                 } else {
1212                         DRM_DEBUG("DFP5 disconnected\n");
1213                         bios_0_scratch &= ~ATOM_S0_DFP5;
1214                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1215                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1216                 }
1217         }
1218
1219         if (rdev->family >= CHIP_R600) {
1220                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1221                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1222                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1223         } else {
1224                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1225                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1226                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1227         }
1228 }
1229
1230 void
1231 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1232 {
1233         struct drm_device *dev = encoder->dev;
1234         struct radeon_device *rdev = dev->dev_private;
1235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1236         uint32_t bios_3_scratch;
1237
1238         if (rdev->family >= CHIP_R600)
1239                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1240         else
1241                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1242
1243         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1244                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1245                 bios_3_scratch |= (crtc << 18);
1246         }
1247         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1248                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1249                 bios_3_scratch |= (crtc << 24);
1250         }
1251         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1252                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1253                 bios_3_scratch |= (crtc << 16);
1254         }
1255         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1256                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1257                 bios_3_scratch |= (crtc << 20);
1258         }
1259         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1260                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1261                 bios_3_scratch |= (crtc << 17);
1262         }
1263         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1264                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1265                 bios_3_scratch |= (crtc << 19);
1266         }
1267         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1268                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1269                 bios_3_scratch |= (crtc << 23);
1270         }
1271         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1272                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1273                 bios_3_scratch |= (crtc << 25);
1274         }
1275
1276         if (rdev->family >= CHIP_R600)
1277                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1278         else
1279                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1280 }
1281
1282 void
1283 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1284 {
1285         struct drm_device *dev = encoder->dev;
1286         struct radeon_device *rdev = dev->dev_private;
1287         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1288         uint32_t bios_2_scratch;
1289
1290         if (rdev->family >= CHIP_R600)
1291                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1292         else
1293                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1294
1295         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1296                 if (on)
1297                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1298                 else
1299                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1300         }
1301         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1302                 if (on)
1303                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1304                 else
1305                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1306         }
1307         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1308                 if (on)
1309                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1310                 else
1311                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1312         }
1313         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1314                 if (on)
1315                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1316                 else
1317                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1318         }
1319         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1320                 if (on)
1321                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1322                 else
1323                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1324         }
1325         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1326                 if (on)
1327                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1328                 else
1329                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1330         }
1331         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1332                 if (on)
1333                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1334                 else
1335                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1336         }
1337         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1338                 if (on)
1339                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1340                 else
1341                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1342         }
1343         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1344                 if (on)
1345                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1346                 else
1347                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1348         }
1349         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1350                 if (on)
1351                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1352                 else
1353                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1354         }
1355
1356         if (rdev->family >= CHIP_R600)
1357                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1358         else
1359                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1360 }