2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
83 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
84 gpio = &i2c_info->asGPIO_Info[i];
86 if (gpio->sucI2cId.ucAccess == id) {
87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
98 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
105 i2c.hw_capable = true;
107 i2c.hw_capable = false;
109 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.i2c_id = gpio->sucI2cId.ucAccess;
124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 struct atom_context *ctx = rdev->mode_info.atom_context;
128 struct radeon_gpio_rec gpio;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
130 struct _ATOM_GPIO_PIN_LUT *gpio_info;
131 ATOM_GPIO_PIN_ASSIGNMENT *pin;
132 u16 data_offset, size;
135 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
138 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
140 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
142 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
144 for (i = 0; i < num_indices; i++) {
145 pin = &gpio_info->asGPIO_Pin[i];
146 if (id == pin->ucGPIO_ID) {
147 gpio.id = pin->ucGPIO_ID;
148 gpio.reg = pin->usGpioPin_AIndex * 4;
149 gpio.mask = (1 << pin->ucGpioPinBitShift);
158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
161 struct radeon_hpd hpd;
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
167 reg = AVIVO_DC_GPIO_HPD_A;
170 if (gpio->reg == reg) {
173 hpd.hpd = RADEON_HPD_1;
176 hpd.hpd = RADEON_HPD_2;
179 hpd.hpd = RADEON_HPD_3;
182 hpd.hpd = RADEON_HPD_4;
185 hpd.hpd = RADEON_HPD_5;
188 hpd.hpd = RADEON_HPD_6;
191 hpd.hpd = RADEON_HPD_NONE;
195 hpd.hpd = RADEON_HPD_NONE;
199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
202 struct radeon_i2c_bus_rec *i2c_bus,
204 struct radeon_hpd *hpd)
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
216 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x147b) &&
219 (dev->pdev->subsystem_device == 0x2412)) {
220 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
224 /* Falcon NW laptop lists vga ddc line for LVDS */
225 if ((dev->pdev->device == 0x5653) &&
226 (dev->pdev->subsystem_vendor == 0x1462) &&
227 (dev->pdev->subsystem_device == 0x0291)) {
228 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
229 i2c_bus->valid = false;
234 /* HIS X1300 is DVI+VGA, not DVI+DVI */
235 if ((dev->pdev->device == 0x7146) &&
236 (dev->pdev->subsystem_vendor == 0x17af) &&
237 (dev->pdev->subsystem_device == 0x2058)) {
238 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
242 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
243 if ((dev->pdev->device == 0x7142) &&
244 (dev->pdev->subsystem_vendor == 0x1458) &&
245 (dev->pdev->subsystem_device == 0x2134)) {
246 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
252 if ((dev->pdev->device == 0x71C5) &&
253 (dev->pdev->subsystem_vendor == 0x106b) &&
254 (dev->pdev->subsystem_device == 0x0080)) {
255 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
256 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
260 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
261 if ((dev->pdev->device == 0x9598) &&
262 (dev->pdev->subsystem_vendor == 0x1043) &&
263 (dev->pdev->subsystem_device == 0x01da)) {
264 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
265 *connector_type = DRM_MODE_CONNECTOR_DVII;
269 /* ASUS HD 3450 board lists the DVI port as HDMI */
270 if ((dev->pdev->device == 0x95C5) &&
271 (dev->pdev->subsystem_vendor == 0x1043) &&
272 (dev->pdev->subsystem_device == 0x01e2)) {
273 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
274 *connector_type = DRM_MODE_CONNECTOR_DVII;
278 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
279 * HDMI + VGA reporting as HDMI
281 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
282 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
283 *connector_type = DRM_MODE_CONNECTOR_VGA;
288 /* Acer laptop reports DVI-D as DVI-I */
289 if ((dev->pdev->device == 0x95c4) &&
290 (dev->pdev->subsystem_vendor == 0x1025) &&
291 (dev->pdev->subsystem_device == 0x013c)) {
292 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
293 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
294 *connector_type = DRM_MODE_CONNECTOR_DVID;
300 const int supported_devices_connector_convert[] = {
301 DRM_MODE_CONNECTOR_Unknown,
302 DRM_MODE_CONNECTOR_VGA,
303 DRM_MODE_CONNECTOR_DVII,
304 DRM_MODE_CONNECTOR_DVID,
305 DRM_MODE_CONNECTOR_DVIA,
306 DRM_MODE_CONNECTOR_SVIDEO,
307 DRM_MODE_CONNECTOR_Composite,
308 DRM_MODE_CONNECTOR_LVDS,
309 DRM_MODE_CONNECTOR_Unknown,
310 DRM_MODE_CONNECTOR_Unknown,
311 DRM_MODE_CONNECTOR_HDMIA,
312 DRM_MODE_CONNECTOR_HDMIB,
313 DRM_MODE_CONNECTOR_Unknown,
314 DRM_MODE_CONNECTOR_Unknown,
315 DRM_MODE_CONNECTOR_9PinDIN,
316 DRM_MODE_CONNECTOR_DisplayPort
319 const uint16_t supported_devices_connector_object_id_convert[] = {
320 CONNECTOR_OBJECT_ID_NONE,
321 CONNECTOR_OBJECT_ID_VGA,
322 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
323 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
324 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
325 CONNECTOR_OBJECT_ID_COMPOSITE,
326 CONNECTOR_OBJECT_ID_SVIDEO,
327 CONNECTOR_OBJECT_ID_LVDS,
328 CONNECTOR_OBJECT_ID_9PIN_DIN,
329 CONNECTOR_OBJECT_ID_9PIN_DIN,
330 CONNECTOR_OBJECT_ID_DISPLAYPORT,
331 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
332 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
333 CONNECTOR_OBJECT_ID_SVIDEO
336 const int object_connector_convert[] = {
337 DRM_MODE_CONNECTOR_Unknown,
338 DRM_MODE_CONNECTOR_DVII,
339 DRM_MODE_CONNECTOR_DVII,
340 DRM_MODE_CONNECTOR_DVID,
341 DRM_MODE_CONNECTOR_DVID,
342 DRM_MODE_CONNECTOR_VGA,
343 DRM_MODE_CONNECTOR_Composite,
344 DRM_MODE_CONNECTOR_SVIDEO,
345 DRM_MODE_CONNECTOR_Unknown,
346 DRM_MODE_CONNECTOR_Unknown,
347 DRM_MODE_CONNECTOR_9PinDIN,
348 DRM_MODE_CONNECTOR_Unknown,
349 DRM_MODE_CONNECTOR_HDMIA,
350 DRM_MODE_CONNECTOR_HDMIB,
351 DRM_MODE_CONNECTOR_LVDS,
352 DRM_MODE_CONNECTOR_9PinDIN,
353 DRM_MODE_CONNECTOR_Unknown,
354 DRM_MODE_CONNECTOR_Unknown,
355 DRM_MODE_CONNECTOR_Unknown,
356 DRM_MODE_CONNECTOR_DisplayPort,
357 DRM_MODE_CONNECTOR_eDP,
358 DRM_MODE_CONNECTOR_Unknown
361 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
363 struct radeon_device *rdev = dev->dev_private;
364 struct radeon_mode_info *mode_info = &rdev->mode_info;
365 struct atom_context *ctx = mode_info->atom_context;
366 int index = GetIndexIntoMasterTable(DATA, Object_Header);
367 u16 size, data_offset;
369 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
370 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
371 ATOM_OBJECT_HEADER *obj_header;
372 int i, j, path_size, device_support;
374 u16 igp_lane_info, conn_id, connector_object_id;
376 struct radeon_i2c_bus_rec ddc_bus;
377 struct radeon_gpio_rec gpio;
378 struct radeon_hpd hpd;
380 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
382 if (data_offset == 0)
388 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
389 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
390 (ctx->bios + data_offset +
391 le16_to_cpu(obj_header->usDisplayPathTableOffset));
392 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
393 (ctx->bios + data_offset +
394 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
395 device_support = le16_to_cpu(obj_header->usDeviceSupport);
398 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
399 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
400 ATOM_DISPLAY_OBJECT_PATH *path;
402 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
403 path_size += le16_to_cpu(path->usSize);
405 if (device_support & le16_to_cpu(path->usDeviceTag)) {
406 uint8_t con_obj_id, con_obj_num, con_obj_type;
409 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
412 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
415 (le16_to_cpu(path->usConnObjectId) &
416 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
418 /* TODO CV support */
419 if (le16_to_cpu(path->usDeviceTag) ==
420 ATOM_DEVICE_CV_SUPPORT)
424 if ((rdev->flags & RADEON_IS_IGP) &&
426 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
427 uint16_t igp_offset = 0;
428 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
431 GetIndexIntoMasterTable(DATA,
432 IntegratedSystemInfo);
434 atom_parse_data_header(ctx, index, &size, &frev,
439 (ATOM_INTEGRATED_SYSTEM_INFO_V2
440 *) (ctx->bios + igp_offset);
443 uint32_t slot_config, ct;
445 if (con_obj_num == 1)
454 ct = (slot_config >> 16) & 0xff;
456 object_connector_convert
458 connector_object_id = ct;
460 slot_config & 0xffff;
468 object_connector_convert[con_obj_id];
469 connector_object_id = con_obj_id;
472 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
475 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
477 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
480 (le16_to_cpu(path->usGraphicObjIds[j]) &
481 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
483 (le16_to_cpu(path->usGraphicObjIds[j]) &
484 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
486 (le16_to_cpu(path->usGraphicObjIds[j]) &
487 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
489 /* FIXME: add support for router objects */
490 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
491 if (enc_obj_num == 2)
496 radeon_add_atom_encoder(dev,
505 /* look up gpio for ddc, hpd */
506 if ((le16_to_cpu(path->usDeviceTag) &
507 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
508 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
509 if (le16_to_cpu(path->usConnObjectId) ==
510 le16_to_cpu(con_obj->asObjects[j].
512 ATOM_COMMON_RECORD_HEADER
514 (ATOM_COMMON_RECORD_HEADER
516 (ctx->bios + data_offset +
517 le16_to_cpu(con_obj->
520 ATOM_I2C_RECORD *i2c_record;
521 ATOM_HPD_INT_RECORD *hpd_record;
522 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
523 hpd.hpd = RADEON_HPD_NONE;
525 while (record->ucRecordType > 0
528 ATOM_MAX_OBJECT_RECORD_NUMBER) {
529 switch (record->ucRecordType) {
530 case ATOM_I2C_RECORD_TYPE:
535 (ATOM_I2C_ID_CONFIG_ACCESS *)
536 &i2c_record->sucI2cId;
537 ddc_bus = radeon_lookup_i2c_gpio(rdev,
541 case ATOM_HPD_INT_RECORD_TYPE:
543 (ATOM_HPD_INT_RECORD *)
545 gpio = radeon_lookup_gpio(rdev,
546 hpd_record->ucHPDIntGPIOID);
547 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
548 hpd.plugged_state = hpd_record->ucPlugged_PinState;
552 (ATOM_COMMON_RECORD_HEADER
562 hpd.hpd = RADEON_HPD_NONE;
563 ddc_bus.valid = false;
566 /* needed for aux chan transactions */
567 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
569 conn_id = le16_to_cpu(path->usConnObjectId);
571 if (!radeon_atom_apply_quirks
572 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
573 &ddc_bus, &conn_id, &hpd))
576 radeon_add_atom_connector(dev,
580 connector_type, &ddc_bus,
581 linkb, igp_lane_info,
588 radeon_link_encoder_connector(dev);
593 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
597 struct radeon_device *rdev = dev->dev_private;
599 if (rdev->flags & RADEON_IS_IGP) {
600 return supported_devices_connector_object_id_convert
602 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
603 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
604 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
605 struct radeon_mode_info *mode_info = &rdev->mode_info;
606 struct atom_context *ctx = mode_info->atom_context;
607 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
608 uint16_t size, data_offset;
610 ATOM_XTMDS_INFO *xtmds;
612 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
613 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
615 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
616 if (connector_type == DRM_MODE_CONNECTOR_DVII)
617 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
619 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
621 if (connector_type == DRM_MODE_CONNECTOR_DVII)
622 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
624 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
627 return supported_devices_connector_object_id_convert
632 struct bios_connector {
637 struct radeon_i2c_bus_rec ddc_bus;
638 struct radeon_hpd hpd;
641 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
645 struct radeon_device *rdev = dev->dev_private;
646 struct radeon_mode_info *mode_info = &rdev->mode_info;
647 struct atom_context *ctx = mode_info->atom_context;
648 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
649 uint16_t size, data_offset;
651 uint16_t device_support;
653 union atom_supported_devices *supported_devices;
654 int i, j, max_device;
655 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
657 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
660 (union atom_supported_devices *)(ctx->bios + data_offset);
662 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
665 max_device = ATOM_MAX_SUPPORTED_DEVICE;
667 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
669 for (i = 0; i < max_device; i++) {
670 ATOM_CONNECTOR_INFO_I2C ci =
671 supported_devices->info.asConnInfo[i];
673 bios_connectors[i].valid = false;
675 if (!(device_support & (1 << i))) {
679 if (i == ATOM_DEVICE_CV_INDEX) {
680 DRM_DEBUG("Skipping Component Video\n");
684 bios_connectors[i].connector_type =
685 supported_devices_connector_convert[ci.sucConnectorInfo.
689 if (bios_connectors[i].connector_type ==
690 DRM_MODE_CONNECTOR_Unknown)
693 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
695 bios_connectors[i].line_mux =
696 ci.sucI2cId.ucAccess;
698 /* give tv unique connector ids */
699 if (i == ATOM_DEVICE_TV1_INDEX) {
700 bios_connectors[i].ddc_bus.valid = false;
701 bios_connectors[i].line_mux = 50;
702 } else if (i == ATOM_DEVICE_TV2_INDEX) {
703 bios_connectors[i].ddc_bus.valid = false;
704 bios_connectors[i].line_mux = 51;
705 } else if (i == ATOM_DEVICE_CV_INDEX) {
706 bios_connectors[i].ddc_bus.valid = false;
707 bios_connectors[i].line_mux = 52;
709 bios_connectors[i].ddc_bus =
710 radeon_lookup_i2c_gpio(rdev,
711 bios_connectors[i].line_mux);
713 if ((crev > 1) && (frev > 1)) {
714 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
717 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
720 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
723 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
727 if (i == ATOM_DEVICE_DFP1_INDEX)
728 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
729 else if (i == ATOM_DEVICE_DFP2_INDEX)
730 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
732 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
735 /* Always set the connector type to VGA for CRT1/CRT2. if they are
736 * shared with a DVI port, we'll pick up the DVI connector when we
737 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
739 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
740 bios_connectors[i].connector_type =
741 DRM_MODE_CONNECTOR_VGA;
743 if (!radeon_atom_apply_quirks
744 (dev, (1 << i), &bios_connectors[i].connector_type,
745 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
746 &bios_connectors[i].hpd))
749 bios_connectors[i].valid = true;
750 bios_connectors[i].devices = (1 << i);
752 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
753 radeon_add_atom_encoder(dev,
754 radeon_get_encoder_id(dev,
759 radeon_add_legacy_encoder(dev,
760 radeon_get_encoder_id(dev,
766 /* combine shared connectors */
767 for (i = 0; i < max_device; i++) {
768 if (bios_connectors[i].valid) {
769 for (j = 0; j < max_device; j++) {
770 if (bios_connectors[j].valid && (i != j)) {
771 if (bios_connectors[i].line_mux ==
772 bios_connectors[j].line_mux) {
773 /* make sure not to combine LVDS */
774 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
775 bios_connectors[i].line_mux = 53;
776 bios_connectors[i].ddc_bus.valid = false;
779 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
780 bios_connectors[j].line_mux = 53;
781 bios_connectors[j].ddc_bus.valid = false;
784 /* combine analog and digital for DVI-I */
785 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
786 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
787 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
788 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
789 bios_connectors[i].devices |=
790 bios_connectors[j].devices;
791 bios_connectors[i].connector_type =
792 DRM_MODE_CONNECTOR_DVII;
793 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
794 bios_connectors[i].hpd =
795 bios_connectors[j].hpd;
796 bios_connectors[j].valid = false;
804 /* add the connectors */
805 for (i = 0; i < max_device; i++) {
806 if (bios_connectors[i].valid) {
807 uint16_t connector_object_id =
808 atombios_get_connector_object_id(dev,
809 bios_connectors[i].connector_type,
810 bios_connectors[i].devices);
811 radeon_add_atom_connector(dev,
812 bios_connectors[i].line_mux,
813 bios_connectors[i].devices,
816 &bios_connectors[i].ddc_bus,
819 &bios_connectors[i].hpd);
823 radeon_link_encoder_connector(dev);
828 union firmware_info {
829 ATOM_FIRMWARE_INFO info;
830 ATOM_FIRMWARE_INFO_V1_2 info_12;
831 ATOM_FIRMWARE_INFO_V1_3 info_13;
832 ATOM_FIRMWARE_INFO_V1_4 info_14;
833 ATOM_FIRMWARE_INFO_V2_1 info_21;
836 bool radeon_atom_get_clock_info(struct drm_device *dev)
838 struct radeon_device *rdev = dev->dev_private;
839 struct radeon_mode_info *mode_info = &rdev->mode_info;
840 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
841 union firmware_info *firmware_info;
843 struct radeon_pll *p1pll = &rdev->clock.p1pll;
844 struct radeon_pll *p2pll = &rdev->clock.p2pll;
845 struct radeon_pll *dcpll = &rdev->clock.dcpll;
846 struct radeon_pll *spll = &rdev->clock.spll;
847 struct radeon_pll *mpll = &rdev->clock.mpll;
848 uint16_t data_offset;
850 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
851 &crev, &data_offset);
854 (union firmware_info *)(mode_info->atom_context->bios +
859 p1pll->reference_freq =
860 le16_to_cpu(firmware_info->info.usReferenceClock);
861 p1pll->reference_div = 0;
865 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
868 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
870 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
872 if (p1pll->pll_out_min == 0) {
873 if (ASIC_IS_AVIVO(rdev))
874 p1pll->pll_out_min = 64800;
876 p1pll->pll_out_min = 20000;
877 } else if (p1pll->pll_out_min > 64800) {
878 /* Limiting the pll output range is a good thing generally as
879 * it limits the number of possible pll combinations for a given
880 * frequency presumably to the ones that work best on each card.
881 * However, certain duallink DVI monitors seem to like
882 * pll combinations that would be limited by this at least on
883 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
887 p1pll->pll_out_min = 64800;
891 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
893 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
898 spll->reference_freq =
899 le16_to_cpu(firmware_info->info.usReferenceClock);
900 spll->reference_div = 0;
903 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
905 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
908 if (spll->pll_out_min == 0) {
909 if (ASIC_IS_AVIVO(rdev))
910 spll->pll_out_min = 64800;
912 spll->pll_out_min = 20000;
916 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
918 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
921 mpll->reference_freq =
922 le16_to_cpu(firmware_info->info.usReferenceClock);
923 mpll->reference_div = 0;
926 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
928 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
931 if (mpll->pll_out_min == 0) {
932 if (ASIC_IS_AVIVO(rdev))
933 mpll->pll_out_min = 64800;
935 mpll->pll_out_min = 20000;
939 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
941 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
943 rdev->clock.default_sclk =
944 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
945 rdev->clock.default_mclk =
946 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
948 if (ASIC_IS_DCE4(rdev)) {
949 rdev->clock.default_dispclk =
950 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
951 if (rdev->clock.default_dispclk == 0)
952 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
953 rdev->clock.dp_extclk =
954 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
965 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
966 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
969 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
971 struct radeon_mode_info *mode_info = &rdev->mode_info;
972 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
973 union igp_info *igp_info;
977 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
978 &crev, &data_offset);
980 igp_info = (union igp_info *)(mode_info->atom_context->bios +
986 if (igp_info->info.ucMemoryType & 0xf0)
990 if (igp_info->info_2.ucMemoryType & 0x0f)
994 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1001 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1002 struct radeon_encoder_int_tmds *tmds)
1004 struct drm_device *dev = encoder->base.dev;
1005 struct radeon_device *rdev = dev->dev_private;
1006 struct radeon_mode_info *mode_info = &rdev->mode_info;
1007 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1008 uint16_t data_offset;
1009 struct _ATOM_TMDS_INFO *tmds_info;
1014 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1015 &crev, &data_offset);
1018 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1022 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1023 for (i = 0; i < 4; i++) {
1024 tmds->tmds_pll[i].freq =
1025 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1026 tmds->tmds_pll[i].value =
1027 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1028 tmds->tmds_pll[i].value |=
1029 (tmds_info->asMiscInfo[i].
1030 ucPLL_VCO_Gain & 0x3f) << 6;
1031 tmds->tmds_pll[i].value |=
1032 (tmds_info->asMiscInfo[i].
1033 ucPLL_DutyCycle & 0xf) << 12;
1034 tmds->tmds_pll[i].value |=
1035 (tmds_info->asMiscInfo[i].
1036 ucPLL_VoltageSwing & 0xf) << 16;
1038 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1039 tmds->tmds_pll[i].freq,
1040 tmds->tmds_pll[i].value);
1042 if (maxfreq == tmds->tmds_pll[i].freq) {
1043 tmds->tmds_pll[i].freq = 0xffffffff;
1052 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1057 struct drm_device *dev = encoder->base.dev;
1058 struct radeon_device *rdev = dev->dev_private;
1059 struct radeon_mode_info *mode_info = &rdev->mode_info;
1060 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1061 uint16_t data_offset;
1062 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1064 struct radeon_atom_ss *ss = NULL;
1067 if (id > ATOM_MAX_SS_ENTRY)
1070 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1071 &crev, &data_offset);
1074 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1078 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1083 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1084 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1086 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1087 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1088 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1089 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1090 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1091 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1099 static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
1100 struct radeon_encoder_atom_dig *lvds)
1103 /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1104 if ((dev->pdev->device == 0x95c4) &&
1105 (dev->pdev->subsystem_vendor == 0x1179) &&
1106 (dev->pdev->subsystem_device == 0xff50)) {
1107 if ((lvds->native_mode.hdisplay == 1280) &&
1108 (lvds->native_mode.vdisplay == 800))
1109 lvds->pll_algo = PLL_ALGO_LEGACY;
1112 /* Dell Studio 15 laptop panel doesn't like new pll divider algo */
1113 if ((dev->pdev->device == 0x95c4) &&
1114 (dev->pdev->subsystem_vendor == 0x1028) &&
1115 (dev->pdev->subsystem_device == 0x029f)) {
1116 if ((lvds->native_mode.hdisplay == 1280) &&
1117 (lvds->native_mode.vdisplay == 800))
1118 lvds->pll_algo = PLL_ALGO_LEGACY;
1124 struct _ATOM_LVDS_INFO info;
1125 struct _ATOM_LVDS_INFO_V12 info_12;
1128 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1132 struct drm_device *dev = encoder->base.dev;
1133 struct radeon_device *rdev = dev->dev_private;
1134 struct radeon_mode_info *mode_info = &rdev->mode_info;
1135 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1136 uint16_t data_offset, misc;
1137 union lvds_info *lvds_info;
1139 struct radeon_encoder_atom_dig *lvds = NULL;
1141 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1142 &crev, &data_offset);
1145 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1149 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1154 lvds->native_mode.clock =
1155 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1156 lvds->native_mode.hdisplay =
1157 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1158 lvds->native_mode.vdisplay =
1159 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1160 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1161 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1162 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1163 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1164 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1165 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1166 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1167 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1168 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1169 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1170 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1171 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1172 lvds->panel_pwr_delay =
1173 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1174 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1176 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1177 if (misc & ATOM_VSYNC_POLARITY)
1178 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1179 if (misc & ATOM_HSYNC_POLARITY)
1180 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1181 if (misc & ATOM_COMPOSITESYNC)
1182 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1183 if (misc & ATOM_INTERLACE)
1184 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1185 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1186 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1188 /* set crtc values */
1189 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1191 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1193 if (ASIC_IS_AVIVO(rdev)) {
1195 lvds->pll_algo = PLL_ALGO_AVIVO;
1197 lvds->pll_algo = PLL_ALGO_LEGACY;
1199 lvds->pll_algo = PLL_ALGO_LEGACY;
1202 radeon_atom_apply_lvds_quirks(dev, lvds);
1204 encoder->native_mode = lvds->native_mode;
1209 struct radeon_encoder_primary_dac *
1210 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1212 struct drm_device *dev = encoder->base.dev;
1213 struct radeon_device *rdev = dev->dev_private;
1214 struct radeon_mode_info *mode_info = &rdev->mode_info;
1215 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1216 uint16_t data_offset;
1217 struct _COMPASSIONATE_DATA *dac_info;
1220 struct radeon_encoder_primary_dac *p_dac = NULL;
1222 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1224 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1227 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1232 bg = dac_info->ucDAC1_BG_Adjustment;
1233 dac = dac_info->ucDAC1_DAC_Adjustment;
1234 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1240 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1241 struct drm_display_mode *mode)
1243 struct radeon_mode_info *mode_info = &rdev->mode_info;
1244 ATOM_ANALOG_TV_INFO *tv_info;
1245 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1246 ATOM_DTD_FORMAT *dtd_timings;
1247 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1249 u16 data_offset, misc;
1251 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1255 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1256 if (index > MAX_SUPPORTED_TV_TIMING)
1259 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1260 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1261 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1262 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1263 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1265 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1266 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1267 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1268 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1269 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1272 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1273 if (misc & ATOM_VSYNC_POLARITY)
1274 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1275 if (misc & ATOM_HSYNC_POLARITY)
1276 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1277 if (misc & ATOM_COMPOSITESYNC)
1278 mode->flags |= DRM_MODE_FLAG_CSYNC;
1279 if (misc & ATOM_INTERLACE)
1280 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1281 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1282 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1284 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1287 /* PAL timings appear to have wrong values for totals */
1288 mode->crtc_htotal -= 1;
1289 mode->crtc_vtotal -= 1;
1293 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1294 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1297 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1298 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1299 le16_to_cpu(dtd_timings->usHBlanking_Time);
1300 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1301 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1302 le16_to_cpu(dtd_timings->usHSyncOffset);
1303 mode->crtc_hsync_end = mode->crtc_hsync_start +
1304 le16_to_cpu(dtd_timings->usHSyncWidth);
1306 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1307 le16_to_cpu(dtd_timings->usVBlanking_Time);
1308 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1309 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1310 le16_to_cpu(dtd_timings->usVSyncOffset);
1311 mode->crtc_vsync_end = mode->crtc_vsync_start +
1312 le16_to_cpu(dtd_timings->usVSyncWidth);
1315 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1316 if (misc & ATOM_VSYNC_POLARITY)
1317 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1318 if (misc & ATOM_HSYNC_POLARITY)
1319 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1320 if (misc & ATOM_COMPOSITESYNC)
1321 mode->flags |= DRM_MODE_FLAG_CSYNC;
1322 if (misc & ATOM_INTERLACE)
1323 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1324 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1325 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1327 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1334 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1336 struct radeon_mode_info *mode_info = &rdev->mode_info;
1337 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1338 uint16_t data_offset;
1340 struct _ATOM_ANALOG_TV_INFO *tv_info;
1341 enum radeon_tv_std tv_std = TV_STD_NTSC;
1343 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1345 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1347 switch (tv_info->ucTV_BootUpDefaultStandard) {
1349 tv_std = TV_STD_NTSC;
1350 DRM_INFO("Default TV standard: NTSC\n");
1353 tv_std = TV_STD_NTSC_J;
1354 DRM_INFO("Default TV standard: NTSC-J\n");
1357 tv_std = TV_STD_PAL;
1358 DRM_INFO("Default TV standard: PAL\n");
1361 tv_std = TV_STD_PAL_M;
1362 DRM_INFO("Default TV standard: PAL-M\n");
1365 tv_std = TV_STD_PAL_N;
1366 DRM_INFO("Default TV standard: PAL-N\n");
1369 tv_std = TV_STD_PAL_CN;
1370 DRM_INFO("Default TV standard: PAL-CN\n");
1373 tv_std = TV_STD_PAL_60;
1374 DRM_INFO("Default TV standard: PAL-60\n");
1377 tv_std = TV_STD_SECAM;
1378 DRM_INFO("Default TV standard: SECAM\n");
1381 tv_std = TV_STD_NTSC;
1382 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1388 struct radeon_encoder_tv_dac *
1389 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1391 struct drm_device *dev = encoder->base.dev;
1392 struct radeon_device *rdev = dev->dev_private;
1393 struct radeon_mode_info *mode_info = &rdev->mode_info;
1394 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1395 uint16_t data_offset;
1396 struct _COMPASSIONATE_DATA *dac_info;
1399 struct radeon_encoder_tv_dac *tv_dac = NULL;
1401 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1403 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1406 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1411 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1412 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1413 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1415 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1416 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1417 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1419 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1420 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1421 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1423 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1429 struct _ATOM_POWERPLAY_INFO info;
1430 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1431 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1432 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1435 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1437 struct radeon_mode_info *mode_info = &rdev->mode_info;
1438 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1441 u32 misc, misc2 = 0, sclk, mclk;
1442 union power_info *power_info;
1443 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1444 struct _ATOM_PPLIB_STATE *power_state;
1445 int num_modes = 0, i, j;
1446 int state_index = 0, mode_index = 0;
1448 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1450 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1452 rdev->pm.default_power_state = NULL;
1453 rdev->pm.current_power_state = NULL;
1457 num_modes = power_info->info.ucNumOfPowerModeEntries;
1458 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1459 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1460 for (i = 0; i < num_modes; i++) {
1461 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1464 rdev->pm.power_state[state_index].num_clock_modes = 1;
1465 rdev->pm.power_state[state_index].clock_info[0].mclk =
1466 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1467 rdev->pm.power_state[state_index].clock_info[0].sclk =
1468 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1469 /* skip invalid modes */
1470 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1471 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1473 /* skip overclock modes for now */
1474 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1475 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1476 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1477 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1479 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1480 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1481 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1482 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1483 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1485 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1486 radeon_lookup_gpio(rdev,
1487 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1488 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1489 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1492 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1494 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1495 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1497 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1498 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1500 /* order matters! */
1501 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1502 rdev->pm.power_state[state_index].type =
1503 POWER_STATE_TYPE_POWERSAVE;
1504 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1505 rdev->pm.power_state[state_index].type =
1506 POWER_STATE_TYPE_BATTERY;
1507 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1508 rdev->pm.power_state[state_index].type =
1509 POWER_STATE_TYPE_BATTERY;
1510 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1511 rdev->pm.power_state[state_index].type =
1512 POWER_STATE_TYPE_BALANCED;
1513 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1514 rdev->pm.power_state[state_index].type =
1515 POWER_STATE_TYPE_PERFORMANCE;
1516 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1517 rdev->pm.power_state[state_index].type =
1518 POWER_STATE_TYPE_DEFAULT;
1519 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1520 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1521 rdev->pm.power_state[state_index].default_clock_mode =
1522 &rdev->pm.power_state[state_index].clock_info[0];
1523 rdev->pm.power_state[state_index].current_clock_mode =
1524 &rdev->pm.power_state[state_index].clock_info[0];
1529 rdev->pm.power_state[state_index].num_clock_modes = 1;
1530 rdev->pm.power_state[state_index].clock_info[0].mclk =
1531 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1532 rdev->pm.power_state[state_index].clock_info[0].sclk =
1533 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1534 /* skip invalid modes */
1535 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1536 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1538 /* skip overclock modes for now */
1539 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1540 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1541 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1542 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1544 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1545 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1546 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1547 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1548 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1549 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1551 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1552 radeon_lookup_gpio(rdev,
1553 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1554 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1555 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1558 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1560 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1561 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1563 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1564 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1566 /* order matters! */
1567 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1568 rdev->pm.power_state[state_index].type =
1569 POWER_STATE_TYPE_POWERSAVE;
1570 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1571 rdev->pm.power_state[state_index].type =
1572 POWER_STATE_TYPE_BATTERY;
1573 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1574 rdev->pm.power_state[state_index].type =
1575 POWER_STATE_TYPE_BATTERY;
1576 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1577 rdev->pm.power_state[state_index].type =
1578 POWER_STATE_TYPE_BALANCED;
1579 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1580 rdev->pm.power_state[state_index].type =
1581 POWER_STATE_TYPE_PERFORMANCE;
1582 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1583 rdev->pm.power_state[state_index].type =
1584 POWER_STATE_TYPE_BALANCED;
1585 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1586 rdev->pm.power_state[state_index].type =
1587 POWER_STATE_TYPE_DEFAULT;
1588 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1589 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1590 rdev->pm.power_state[state_index].default_clock_mode =
1591 &rdev->pm.power_state[state_index].clock_info[0];
1592 rdev->pm.power_state[state_index].current_clock_mode =
1593 &rdev->pm.power_state[state_index].clock_info[0];
1598 rdev->pm.power_state[state_index].num_clock_modes = 1;
1599 rdev->pm.power_state[state_index].clock_info[0].mclk =
1600 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1601 rdev->pm.power_state[state_index].clock_info[0].sclk =
1602 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1603 /* skip invalid modes */
1604 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1605 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1607 /* skip overclock modes for now */
1608 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1609 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1610 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1611 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1613 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1614 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1615 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1616 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1617 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1618 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1620 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1621 radeon_lookup_gpio(rdev,
1622 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1623 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1624 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1627 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1629 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1630 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1632 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1633 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1634 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1635 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1637 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1638 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1641 /* order matters! */
1642 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1643 rdev->pm.power_state[state_index].type =
1644 POWER_STATE_TYPE_POWERSAVE;
1645 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1646 rdev->pm.power_state[state_index].type =
1647 POWER_STATE_TYPE_BATTERY;
1648 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1649 rdev->pm.power_state[state_index].type =
1650 POWER_STATE_TYPE_BATTERY;
1651 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1652 rdev->pm.power_state[state_index].type =
1653 POWER_STATE_TYPE_BALANCED;
1654 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1655 rdev->pm.power_state[state_index].type =
1656 POWER_STATE_TYPE_PERFORMANCE;
1657 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1658 rdev->pm.power_state[state_index].type =
1659 POWER_STATE_TYPE_BALANCED;
1660 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1661 rdev->pm.power_state[state_index].type =
1662 POWER_STATE_TYPE_DEFAULT;
1663 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1664 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1665 rdev->pm.power_state[state_index].default_clock_mode =
1666 &rdev->pm.power_state[state_index].clock_info[0];
1667 rdev->pm.power_state[state_index].current_clock_mode =
1668 &rdev->pm.power_state[state_index].clock_info[0];
1674 } else if (frev == 4) {
1675 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1677 power_state = (struct _ATOM_PPLIB_STATE *)
1678 (mode_info->atom_context->bios +
1680 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1681 i * power_info->info_4.ucStateEntrySize);
1682 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1683 (mode_info->atom_context->bios +
1685 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1686 (power_state->ucNonClockStateIndex *
1687 power_info->info_4.ucNonClockSize));
1688 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1689 if (rdev->flags & RADEON_IS_IGP) {
1690 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1691 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1692 (mode_info->atom_context->bios +
1694 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1695 (power_state->ucClockStateIndices[j] *
1696 power_info->info_4.ucClockInfoSize));
1697 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1698 sclk |= clock_info->ucLowEngineClockHigh << 16;
1699 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1700 /* skip invalid modes */
1701 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1703 /* skip overclock modes for now */
1704 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1705 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1707 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1709 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1713 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1714 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1715 (mode_info->atom_context->bios +
1717 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1718 (power_state->ucClockStateIndices[j] *
1719 power_info->info_4.ucClockInfoSize));
1720 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1721 sclk |= clock_info->ucEngineClockHigh << 16;
1722 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1723 mclk |= clock_info->ucMemoryClockHigh << 16;
1724 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1725 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1726 /* skip invalid modes */
1727 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1728 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1730 /* skip overclock modes for now */
1731 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1732 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1733 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1734 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1736 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1738 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1743 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1745 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1746 misc2 = le16_to_cpu(non_clock_info->usClassification);
1747 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1748 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1749 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1750 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1751 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1752 rdev->pm.power_state[state_index].type =
1753 POWER_STATE_TYPE_BATTERY;
1755 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1756 rdev->pm.power_state[state_index].type =
1757 POWER_STATE_TYPE_BALANCED;
1759 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1760 rdev->pm.power_state[state_index].type =
1761 POWER_STATE_TYPE_PERFORMANCE;
1764 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1765 rdev->pm.power_state[state_index].type =
1766 POWER_STATE_TYPE_DEFAULT;
1767 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1768 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1769 rdev->pm.power_state[state_index].default_clock_mode =
1770 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1771 rdev->pm.power_state[state_index].current_clock_mode =
1772 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1779 /* XXX figure out some good default low power mode for cards w/out power tables */
1782 if (rdev->pm.default_power_state == NULL) {
1783 /* add the default mode */
1784 rdev->pm.power_state[state_index].type =
1785 POWER_STATE_TYPE_DEFAULT;
1786 rdev->pm.power_state[state_index].num_clock_modes = 1;
1787 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1788 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1789 rdev->pm.power_state[state_index].default_clock_mode =
1790 &rdev->pm.power_state[state_index].clock_info[0];
1791 rdev->pm.power_state[state_index].current_clock_mode =
1792 &rdev->pm.power_state[state_index].clock_info[0];
1793 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1794 if (rdev->asic->get_pcie_lanes)
1795 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1797 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1798 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1799 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1802 rdev->pm.num_power_states = state_index;
1805 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1807 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1808 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1810 args.ucEnable = enable;
1812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1815 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1817 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1818 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1820 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1821 return args.ulReturnEngineClock;
1824 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1826 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1827 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1829 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1830 return args.ulReturnMemoryClock;
1833 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1836 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1837 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1839 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1841 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1844 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1847 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1848 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1850 if (rdev->flags & RADEON_IS_IGP)
1853 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1855 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1858 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1860 struct radeon_device *rdev = dev->dev_private;
1861 uint32_t bios_2_scratch, bios_6_scratch;
1863 if (rdev->family >= CHIP_R600) {
1864 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1865 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1867 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1868 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1871 /* let the bios control the backlight */
1872 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1874 /* tell the bios not to handle mode switching */
1875 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1877 if (rdev->family >= CHIP_R600) {
1878 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1879 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1881 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1882 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1887 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1889 uint32_t scratch_reg;
1892 if (rdev->family >= CHIP_R600)
1893 scratch_reg = R600_BIOS_0_SCRATCH;
1895 scratch_reg = RADEON_BIOS_0_SCRATCH;
1897 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1898 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1901 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1903 uint32_t scratch_reg;
1906 if (rdev->family >= CHIP_R600)
1907 scratch_reg = R600_BIOS_0_SCRATCH;
1909 scratch_reg = RADEON_BIOS_0_SCRATCH;
1911 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1912 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1915 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1917 struct drm_device *dev = encoder->dev;
1918 struct radeon_device *rdev = dev->dev_private;
1919 uint32_t bios_6_scratch;
1921 if (rdev->family >= CHIP_R600)
1922 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1924 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1927 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1929 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1931 if (rdev->family >= CHIP_R600)
1932 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1934 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1937 /* at some point we may want to break this out into individual functions */
1939 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1940 struct drm_encoder *encoder,
1943 struct drm_device *dev = connector->dev;
1944 struct radeon_device *rdev = dev->dev_private;
1945 struct radeon_connector *radeon_connector =
1946 to_radeon_connector(connector);
1947 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1948 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1950 if (rdev->family >= CHIP_R600) {
1951 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1952 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1953 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1955 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1956 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1957 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1960 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1961 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1963 DRM_DEBUG("TV1 connected\n");
1964 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1965 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1967 DRM_DEBUG("TV1 disconnected\n");
1968 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1969 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1970 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1973 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1974 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1976 DRM_DEBUG("CV connected\n");
1977 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1978 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1980 DRM_DEBUG("CV disconnected\n");
1981 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1982 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1983 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1986 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1987 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1989 DRM_DEBUG("LCD1 connected\n");
1990 bios_0_scratch |= ATOM_S0_LCD1;
1991 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1992 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1994 DRM_DEBUG("LCD1 disconnected\n");
1995 bios_0_scratch &= ~ATOM_S0_LCD1;
1996 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1997 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2000 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2001 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2003 DRM_DEBUG("CRT1 connected\n");
2004 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2005 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2006 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2008 DRM_DEBUG("CRT1 disconnected\n");
2009 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2010 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2011 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2014 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2015 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2017 DRM_DEBUG("CRT2 connected\n");
2018 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2019 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2020 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2022 DRM_DEBUG("CRT2 disconnected\n");
2023 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2024 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2025 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2028 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2029 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2031 DRM_DEBUG("DFP1 connected\n");
2032 bios_0_scratch |= ATOM_S0_DFP1;
2033 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2034 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2036 DRM_DEBUG("DFP1 disconnected\n");
2037 bios_0_scratch &= ~ATOM_S0_DFP1;
2038 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2039 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2042 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2043 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2045 DRM_DEBUG("DFP2 connected\n");
2046 bios_0_scratch |= ATOM_S0_DFP2;
2047 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2048 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2050 DRM_DEBUG("DFP2 disconnected\n");
2051 bios_0_scratch &= ~ATOM_S0_DFP2;
2052 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2053 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2056 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2057 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2059 DRM_DEBUG("DFP3 connected\n");
2060 bios_0_scratch |= ATOM_S0_DFP3;
2061 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2062 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2064 DRM_DEBUG("DFP3 disconnected\n");
2065 bios_0_scratch &= ~ATOM_S0_DFP3;
2066 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2067 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2070 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2071 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2073 DRM_DEBUG("DFP4 connected\n");
2074 bios_0_scratch |= ATOM_S0_DFP4;
2075 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2076 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2078 DRM_DEBUG("DFP4 disconnected\n");
2079 bios_0_scratch &= ~ATOM_S0_DFP4;
2080 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2081 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2084 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2085 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2087 DRM_DEBUG("DFP5 connected\n");
2088 bios_0_scratch |= ATOM_S0_DFP5;
2089 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2090 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2092 DRM_DEBUG("DFP5 disconnected\n");
2093 bios_0_scratch &= ~ATOM_S0_DFP5;
2094 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2095 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2099 if (rdev->family >= CHIP_R600) {
2100 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2101 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2102 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2104 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2105 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2106 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2111 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2113 struct drm_device *dev = encoder->dev;
2114 struct radeon_device *rdev = dev->dev_private;
2115 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2116 uint32_t bios_3_scratch;
2118 if (rdev->family >= CHIP_R600)
2119 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2121 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2123 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2124 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2125 bios_3_scratch |= (crtc << 18);
2127 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2128 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2129 bios_3_scratch |= (crtc << 24);
2131 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2132 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2133 bios_3_scratch |= (crtc << 16);
2135 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2136 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2137 bios_3_scratch |= (crtc << 20);
2139 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2140 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2141 bios_3_scratch |= (crtc << 17);
2143 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2144 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2145 bios_3_scratch |= (crtc << 19);
2147 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2148 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2149 bios_3_scratch |= (crtc << 23);
2151 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2152 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2153 bios_3_scratch |= (crtc << 25);
2156 if (rdev->family >= CHIP_R600)
2157 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2159 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2163 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2165 struct drm_device *dev = encoder->dev;
2166 struct radeon_device *rdev = dev->dev_private;
2167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2168 uint32_t bios_2_scratch;
2170 if (rdev->family >= CHIP_R600)
2171 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2173 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2175 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2177 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2179 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2181 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2183 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2185 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2187 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2189 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2191 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2193 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2195 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2197 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2199 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2201 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2203 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2205 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2207 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2209 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2211 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2213 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2215 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2217 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2219 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2221 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2223 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2225 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2227 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2229 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2231 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2233 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2236 if (rdev->family >= CHIP_R600)
2237 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2239 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);