SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                         break;
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 125                                                         u8 id)
 126 {
 127         struct atom_context *ctx = rdev->mode_info.atom_context;
 128         struct radeon_gpio_rec gpio;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 130         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 131         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 132         u16 data_offset, size;
 133         int i, num_indices;
 134
 135         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 136         gpio.valid = false;
 137
 138         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 139
 140         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 141
 142         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 143
 144         for (i = 0; i < num_indices; i++) {
 145                 pin = &gpio_info->asGPIO_Pin[i];
 146                 if (id == pin->ucGPIO_ID) {
 147                         gpio.id = pin->ucGPIO_ID;
 148                         gpio.reg = pin->usGpioPin_AIndex * 4;
 149                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 150                         gpio.valid = true;
 151                         break;
 152                 }
 153         }
 154
 155         return gpio;
 156 }
 157
 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 159                                                             struct radeon_gpio_rec *gpio)
 160 {
 161         struct radeon_hpd hpd;
 162         hpd.gpio = *gpio;
 163         if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
 164                 switch(gpio->mask) {
 165                 case (1 << 0):
 166                         hpd.hpd = RADEON_HPD_1;
 167                         break;
 168                 case (1 << 8):
 169                         hpd.hpd = RADEON_HPD_2;
 170                         break;
 171                 case (1 << 16):
 172                         hpd.hpd = RADEON_HPD_3;
 173                         break;
 174                 case (1 << 24):
 175                         hpd.hpd = RADEON_HPD_4;
 176                         break;
 177                 case (1 << 26):
 178                         hpd.hpd = RADEON_HPD_5;
 179                         break;
 180                 case (1 << 28):
 181                         hpd.hpd = RADEON_HPD_6;
 182                         break;
 183                 default:
 184                         hpd.hpd = RADEON_HPD_NONE;
 185                         break;
 186                 }
 187         } else
 188                 hpd.hpd = RADEON_HPD_NONE;
 189         return hpd;
 190 }
 191
 192 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 193                                      uint32_t supported_device,
 194                                      int *connector_type,
 195                                      struct radeon_i2c_bus_rec *i2c_bus,
 196                                      uint16_t *line_mux,
 197                                      struct radeon_hpd *hpd)
 198 {
 199
 200         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 201         if ((dev->pdev->device == 0x791e) &&
 202             (dev->pdev->subsystem_vendor == 0x1043) &&
 203             (dev->pdev->subsystem_device == 0x826d)) {
 204                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 205                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 206                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 207         }
 208
 209         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 210         if ((dev->pdev->device == 0x7941) &&
 211             (dev->pdev->subsystem_vendor == 0x147b) &&
 212             (dev->pdev->subsystem_device == 0x2412)) {
 213                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 214                         return false;
 215         }
 216
 217         /* Falcon NW laptop lists vga ddc line for LVDS */
 218         if ((dev->pdev->device == 0x5653) &&
 219             (dev->pdev->subsystem_vendor == 0x1462) &&
 220             (dev->pdev->subsystem_device == 0x0291)) {
 221                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 222                         i2c_bus->valid = false;
 223                         *line_mux = 53;
 224                 }
 225         }
 226
 227         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 228         if ((dev->pdev->device == 0x7146) &&
 229             (dev->pdev->subsystem_vendor == 0x17af) &&
 230             (dev->pdev->subsystem_device == 0x2058)) {
 231                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 232                         return false;
 233         }
 234
 235         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 236         if ((dev->pdev->device == 0x7142) &&
 237             (dev->pdev->subsystem_vendor == 0x1458) &&
 238             (dev->pdev->subsystem_device == 0x2134)) {
 239                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 240                         return false;
 241         }
 242
 243
 244         /* Funky macbooks */
 245         if ((dev->pdev->device == 0x71C5) &&
 246             (dev->pdev->subsystem_vendor == 0x106b) &&
 247             (dev->pdev->subsystem_device == 0x0080)) {
 248                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 249                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 250                         return false;
 251         }
 252
 253         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 254         if ((dev->pdev->device == 0x9598) &&
 255             (dev->pdev->subsystem_vendor == 0x1043) &&
 256             (dev->pdev->subsystem_device == 0x01da)) {
 257                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 258                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 259                 }
 260         }
 261
 262         /* ASUS HD 3450 board lists the DVI port as HDMI */
 263         if ((dev->pdev->device == 0x95C5) &&
 264             (dev->pdev->subsystem_vendor == 0x1043) &&
 265             (dev->pdev->subsystem_device == 0x01e2)) {
 266                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 267                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 268                 }
 269         }
 270
 271         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 272          * HDMI + VGA reporting as HDMI
 273          */
 274         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 275                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 276                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 277                         *line_mux = 0;
 278                 }
 279         }
 280
 281         /* Acer laptop reports DVI-D as DVI-I */
 282         if ((dev->pdev->device == 0x95c4) &&
 283             (dev->pdev->subsystem_vendor == 0x1025) &&
 284             (dev->pdev->subsystem_device == 0x013c)) {
 285                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 286                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 287                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 288         }
 289
 290         return true;
 291 }
 292
 293 const int supported_devices_connector_convert[] = {
 294         DRM_MODE_CONNECTOR_Unknown,
 295         DRM_MODE_CONNECTOR_VGA,
 296         DRM_MODE_CONNECTOR_DVII,
 297         DRM_MODE_CONNECTOR_DVID,
 298         DRM_MODE_CONNECTOR_DVIA,
 299         DRM_MODE_CONNECTOR_SVIDEO,
 300         DRM_MODE_CONNECTOR_Composite,
 301         DRM_MODE_CONNECTOR_LVDS,
 302         DRM_MODE_CONNECTOR_Unknown,
 303         DRM_MODE_CONNECTOR_Unknown,
 304         DRM_MODE_CONNECTOR_HDMIA,
 305         DRM_MODE_CONNECTOR_HDMIB,
 306         DRM_MODE_CONNECTOR_Unknown,
 307         DRM_MODE_CONNECTOR_Unknown,
 308         DRM_MODE_CONNECTOR_9PinDIN,
 309         DRM_MODE_CONNECTOR_DisplayPort
 310 };
 311
 312 const uint16_t supported_devices_connector_object_id_convert[] = {
 313         CONNECTOR_OBJECT_ID_NONE,
 314         CONNECTOR_OBJECT_ID_VGA,
 315         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 316         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 317         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 318         CONNECTOR_OBJECT_ID_COMPOSITE,
 319         CONNECTOR_OBJECT_ID_SVIDEO,
 320         CONNECTOR_OBJECT_ID_LVDS,
 321         CONNECTOR_OBJECT_ID_9PIN_DIN,
 322         CONNECTOR_OBJECT_ID_9PIN_DIN,
 323         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 324         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 325         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 326         CONNECTOR_OBJECT_ID_SVIDEO
 327 };
 328
 329 const int object_connector_convert[] = {
 330         DRM_MODE_CONNECTOR_Unknown,
 331         DRM_MODE_CONNECTOR_DVII,
 332         DRM_MODE_CONNECTOR_DVII,
 333         DRM_MODE_CONNECTOR_DVID,
 334         DRM_MODE_CONNECTOR_DVID,
 335         DRM_MODE_CONNECTOR_VGA,
 336         DRM_MODE_CONNECTOR_Composite,
 337         DRM_MODE_CONNECTOR_SVIDEO,
 338         DRM_MODE_CONNECTOR_Unknown,
 339         DRM_MODE_CONNECTOR_Unknown,
 340         DRM_MODE_CONNECTOR_9PinDIN,
 341         DRM_MODE_CONNECTOR_Unknown,
 342         DRM_MODE_CONNECTOR_HDMIA,
 343         DRM_MODE_CONNECTOR_HDMIB,
 344         DRM_MODE_CONNECTOR_LVDS,
 345         DRM_MODE_CONNECTOR_9PinDIN,
 346         DRM_MODE_CONNECTOR_Unknown,
 347         DRM_MODE_CONNECTOR_Unknown,
 348         DRM_MODE_CONNECTOR_Unknown,
 349         DRM_MODE_CONNECTOR_DisplayPort,
 350         DRM_MODE_CONNECTOR_eDP,
 351         DRM_MODE_CONNECTOR_Unknown
 352 };
 353
 354 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 355 {
 356         struct radeon_device *rdev = dev->dev_private;
 357         struct radeon_mode_info *mode_info = &rdev->mode_info;
 358         struct atom_context *ctx = mode_info->atom_context;
 359         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 360         u16 size, data_offset;
 361         u8 frev, crev;
 362         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 363         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 364         ATOM_OBJECT_HEADER *obj_header;
 365         int i, j, path_size, device_support;
 366         int connector_type;
 367         u16 igp_lane_info, conn_id, connector_object_id;
 368         bool linkb;
 369         struct radeon_i2c_bus_rec ddc_bus;
 370         struct radeon_gpio_rec gpio;
 371         struct radeon_hpd hpd;
 372
 373         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 374
 375         if (data_offset == 0)
 376                 return false;
 377
 378         if (crev < 2)
 379                 return false;
 380
 381         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 382         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 383             (ctx->bios + data_offset +
 384              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 385         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 386             (ctx->bios + data_offset +
 387              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 388         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 389
 390         path_size = 0;
 391         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 392                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 393                 ATOM_DISPLAY_OBJECT_PATH *path;
 394                 addr += path_size;
 395                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 396                 path_size += le16_to_cpu(path->usSize);
 397                 linkb = false;
 398                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 399                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 400
 401                         con_obj_id =
 402                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 403                             >> OBJECT_ID_SHIFT;
 404                         con_obj_num =
 405                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 406                             >> ENUM_ID_SHIFT;
 407                         con_obj_type =
 408                             (le16_to_cpu(path->usConnObjectId) &
 409                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 410
 411                         /* TODO CV support */
 412                         if (le16_to_cpu(path->usDeviceTag) ==
 413                                 ATOM_DEVICE_CV_SUPPORT)
 414                                 continue;
 415
 416                         /* IGP chips */
 417                         if ((rdev->flags & RADEON_IS_IGP) &&
 418                             (con_obj_id ==
 419                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 420                                 uint16_t igp_offset = 0;
 421                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 422
 423                                 index =
 424                                     GetIndexIntoMasterTable(DATA,
 425                                                             IntegratedSystemInfo);
 426
 427                                 atom_parse_data_header(ctx, index, &size, &frev,
 428                                                        &crev, &igp_offset);
 429
 430                                 if (crev >= 2) {
 431                                         igp_obj =
 432                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 433                                              *) (ctx->bios + igp_offset);
 434
 435                                         if (igp_obj) {
 436                                                 uint32_t slot_config, ct;
 437
 438                                                 if (con_obj_num == 1)
 439                                                         slot_config =
 440                                                             igp_obj->
 441                                                             ulDDISlot1Config;
 442                                                 else
 443                                                         slot_config =
 444                                                             igp_obj->
 445                                                             ulDDISlot2Config;
 446
 447                                                 ct = (slot_config >> 16) & 0xff;
 448                                                 connector_type =
 449                                                     object_connector_convert
 450                                                     [ct];
 451                                                 connector_object_id = ct;
 452                                                 igp_lane_info =
 453                                                     slot_config & 0xffff;
 454                                         } else
 455                                                 continue;
 456                                 } else
 457                                         continue;
 458                         } else {
 459                                 igp_lane_info = 0;
 460                                 connector_type =
 461                                     object_connector_convert[con_obj_id];
 462                                 connector_object_id = con_obj_id;
 463                         }
 464
 465                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 466                                 continue;
 467
 468                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 469                              j++) {
 470                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 471
 472                                 enc_obj_id =
 473                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 474                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 475                                 enc_obj_num =
 476                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 477                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 478                                 enc_obj_type =
 479                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 480                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 481
 482                                 /* FIXME: add support for router objects */
 483                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 484                                         if (enc_obj_num == 2)
 485                                                 linkb = true;
 486                                         else
 487                                                 linkb = false;
 488
 489                                         radeon_add_atom_encoder(dev,
 490                                                                 enc_obj_id,
 491                                                                 le16_to_cpu
 492                                                                 (path->
 493                                                                  usDeviceTag));
 494
 495                                 }
 496                         }
 497
 498                         /* look up gpio for ddc, hpd */
 499                         if ((le16_to_cpu(path->usDeviceTag) &
 500                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 501                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 502                                         if (le16_to_cpu(path->usConnObjectId) ==
 503                                             le16_to_cpu(con_obj->asObjects[j].
 504                                                         usObjectID)) {
 505                                                 ATOM_COMMON_RECORD_HEADER
 506                                                     *record =
 507                                                     (ATOM_COMMON_RECORD_HEADER
 508                                                      *)
 509                                                     (ctx->bios + data_offset +
 510                                                      le16_to_cpu(con_obj->
 511                                                                  asObjects[j].
 512                                                                  usRecordOffset));
 513                                                 ATOM_I2C_RECORD *i2c_record;
 514                                                 ATOM_HPD_INT_RECORD *hpd_record;
 515                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 516                                                 hpd.hpd = RADEON_HPD_NONE;
 517
 518                                                 while (record->ucRecordType > 0
 519                                                        && record->
 520                                                        ucRecordType <=
 521                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 522                                                         switch (record->ucRecordType) {
 523                                                         case ATOM_I2C_RECORD_TYPE:
 524                                                                 i2c_record =
 525                                                                     (ATOM_I2C_RECORD *)
 526                                                                         record;
 527                                                                 i2c_config =
 528                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 529                                                                         &i2c_record->sucI2cId;
 530                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 531                                                                                                  i2c_config->
 532                                                                                                  ucAccess);
 533                                                                 break;
 534                                                         case ATOM_HPD_INT_RECORD_TYPE:
 535                                                                 hpd_record =
 536                                                                         (ATOM_HPD_INT_RECORD *)
 537                                                                         record;
 538                                                                 gpio = radeon_lookup_gpio(rdev,
 539                                                                                           hpd_record->ucHPDIntGPIOID);
 540                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 541                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 542                                                                 break;
 543                                                         }
 544                                                         record =
 545                                                             (ATOM_COMMON_RECORD_HEADER
 546                                                              *) ((char *)record
 547                                                                  +
 548                                                                  record->
 549                                                                  ucRecordSize);
 550                                                 }
 551                                                 break;
 552                                         }
 553                                 }
 554                         } else {
 555                                 hpd.hpd = RADEON_HPD_NONE;
 556                                 ddc_bus.valid = false;
 557                         }
 558
 559                         conn_id = le16_to_cpu(path->usConnObjectId);
 560
 561                         if (!radeon_atom_apply_quirks
 562                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 563                              &ddc_bus, &conn_id, &hpd))
 564                                 continue;
 565
 566                         radeon_add_atom_connector(dev,
 567                                                   conn_id,
 568                                                   le16_to_cpu(path->
 569                                                               usDeviceTag),
 570                                                   connector_type, &ddc_bus,
 571                                                   linkb, igp_lane_info,
 572                                                   connector_object_id,
 573                                                   &hpd);
 574
 575                 }
 576         }
 577
 578         radeon_link_encoder_connector(dev);
 579
 580         return true;
 581 }
 582
 583 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 584                                                  int connector_type,
 585                                                  uint16_t devices)
 586 {
 587         struct radeon_device *rdev = dev->dev_private;
 588
 589         if (rdev->flags & RADEON_IS_IGP) {
 590                 return supported_devices_connector_object_id_convert
 591                         [connector_type];
 592         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 593                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 594                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 595                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 596                 struct atom_context *ctx = mode_info->atom_context;
 597                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 598                 uint16_t size, data_offset;
 599                 uint8_t frev, crev;
 600                 ATOM_XTMDS_INFO *xtmds;
 601
 602                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 603                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 604
 605                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 606                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 607                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 608                         else
 609                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 610                 } else {
 611                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 612                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 613                         else
 614                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 615                 }
 616         } else {
 617                 return supported_devices_connector_object_id_convert
 618                         [connector_type];
 619         }
 620 }
 621
 622 struct bios_connector {
 623         bool valid;
 624         uint16_t line_mux;
 625         uint16_t devices;
 626         int connector_type;
 627         struct radeon_i2c_bus_rec ddc_bus;
 628         struct radeon_hpd hpd;
 629 };
 630
 631 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 632                                                                  drm_device
 633                                                                  *dev)
 634 {
 635         struct radeon_device *rdev = dev->dev_private;
 636         struct radeon_mode_info *mode_info = &rdev->mode_info;
 637         struct atom_context *ctx = mode_info->atom_context;
 638         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 639         uint16_t size, data_offset;
 640         uint8_t frev, crev;
 641         uint16_t device_support;
 642         uint8_t dac;
 643         union atom_supported_devices *supported_devices;
 644         int i, j, max_device;
 645         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 646
 647         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 648
 649         supported_devices =
 650             (union atom_supported_devices *)(ctx->bios + data_offset);
 651
 652         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 653
 654         if (frev > 1)
 655                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 656         else
 657                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 658
 659         for (i = 0; i < max_device; i++) {
 660                 ATOM_CONNECTOR_INFO_I2C ci =
 661                     supported_devices->info.asConnInfo[i];
 662
 663                 bios_connectors[i].valid = false;
 664
 665                 if (!(device_support & (1 << i))) {
 666                         continue;
 667                 }
 668
 669                 if (i == ATOM_DEVICE_CV_INDEX) {
 670                         DRM_DEBUG("Skipping Component Video\n");
 671                         continue;
 672                 }
 673
 674                 bios_connectors[i].connector_type =
 675                     supported_devices_connector_convert[ci.sucConnectorInfo.
 676                                                         sbfAccess.
 677                                                         bfConnectorType];
 678
 679                 if (bios_connectors[i].connector_type ==
 680                     DRM_MODE_CONNECTOR_Unknown)
 681                         continue;
 682
 683                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 684
 685                 bios_connectors[i].line_mux =
 686                         ci.sucI2cId.ucAccess;
 687
 688                 /* give tv unique connector ids */
 689                 if (i == ATOM_DEVICE_TV1_INDEX) {
 690                         bios_connectors[i].ddc_bus.valid = false;
 691                         bios_connectors[i].line_mux = 50;
 692                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 693                         bios_connectors[i].ddc_bus.valid = false;
 694                         bios_connectors[i].line_mux = 51;
 695                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 696                         bios_connectors[i].ddc_bus.valid = false;
 697                         bios_connectors[i].line_mux = 52;
 698                 } else
 699                         bios_connectors[i].ddc_bus =
 700                             radeon_lookup_i2c_gpio(rdev,
 701                                                    bios_connectors[i].line_mux);
 702
 703                 if ((crev > 1) && (frev > 1)) {
 704                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 705                         switch (isb) {
 706                         case 0x4:
 707                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 708                                 break;
 709                         case 0xa:
 710                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 711                                 break;
 712                         default:
 713                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 714                                 break;
 715                         }
 716                 } else {
 717                         if (i == ATOM_DEVICE_DFP1_INDEX)
 718                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 719                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 720                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 721                         else
 722                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 723                 }
 724
 725                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 726                  * shared with a DVI port, we'll pick up the DVI connector when we
 727                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 728                  */
 729                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 730                         bios_connectors[i].connector_type =
 731                             DRM_MODE_CONNECTOR_VGA;
 732
 733                 if (!radeon_atom_apply_quirks
 734                     (dev, (1 << i), &bios_connectors[i].connector_type,
 735                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 736                      &bios_connectors[i].hpd))
 737                         continue;
 738
 739                 bios_connectors[i].valid = true;
 740                 bios_connectors[i].devices = (1 << i);
 741
 742                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 743                         radeon_add_atom_encoder(dev,
 744                                                 radeon_get_encoder_id(dev,
 745                                                                       (1 << i),
 746                                                                       dac),
 747                                                 (1 << i));
 748                 else
 749                         radeon_add_legacy_encoder(dev,
 750                                                   radeon_get_encoder_id(dev,
 751                                                                         (1 << i),
 752                                                                         dac),
 753                                                   (1 << i));
 754         }
 755
 756         /* combine shared connectors */
 757         for (i = 0; i < max_device; i++) {
 758                 if (bios_connectors[i].valid) {
 759                         for (j = 0; j < max_device; j++) {
 760                                 if (bios_connectors[j].valid && (i != j)) {
 761                                         if (bios_connectors[i].line_mux ==
 762                                             bios_connectors[j].line_mux) {
 763                                                 /* make sure not to combine LVDS */
 764                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 765                                                         bios_connectors[i].line_mux = 53;
 766                                                         bios_connectors[i].ddc_bus.valid = false;
 767                                                         continue;
 768                                                 }
 769                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 770                                                         bios_connectors[j].line_mux = 53;
 771                                                         bios_connectors[j].ddc_bus.valid = false;
 772                                                         continue;
 773                                                 }
 774                                                 /* combine analog and digital for DVI-I */
 775                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 776                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 777                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 778                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 779                                                         bios_connectors[i].devices |=
 780                                                                 bios_connectors[j].devices;
 781                                                         bios_connectors[i].connector_type =
 782                                                                 DRM_MODE_CONNECTOR_DVII;
 783                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 784                                                                 bios_connectors[i].hpd =
 785                                                                         bios_connectors[j].hpd;
 786                                                         bios_connectors[j].valid = false;
 787                                                 }
 788                                         }
 789                                 }
 790                         }
 791                 }
 792         }
 793
 794         /* add the connectors */
 795         for (i = 0; i < max_device; i++) {
 796                 if (bios_connectors[i].valid) {
 797                         uint16_t connector_object_id =
 798                                 atombios_get_connector_object_id(dev,
 799                                                       bios_connectors[i].connector_type,
 800                                                       bios_connectors[i].devices);
 801                         radeon_add_atom_connector(dev,
 802                                                   bios_connectors[i].line_mux,
 803                                                   bios_connectors[i].devices,
 804                                                   bios_connectors[i].
 805                                                   connector_type,
 806                                                   &bios_connectors[i].ddc_bus,
 807                                                   false, 0,
 808                                                   connector_object_id,
 809                                                   &bios_connectors[i].hpd);
 810                 }
 811         }
 812
 813         radeon_link_encoder_connector(dev);
 814
 815         return true;
 816 }
 817
 818 union firmware_info {
 819         ATOM_FIRMWARE_INFO info;
 820         ATOM_FIRMWARE_INFO_V1_2 info_12;
 821         ATOM_FIRMWARE_INFO_V1_3 info_13;
 822         ATOM_FIRMWARE_INFO_V1_4 info_14;
 823 };
 824
 825 bool radeon_atom_get_clock_info(struct drm_device *dev)
 826 {
 827         struct radeon_device *rdev = dev->dev_private;
 828         struct radeon_mode_info *mode_info = &rdev->mode_info;
 829         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 830         union firmware_info *firmware_info;
 831         uint8_t frev, crev;
 832         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 833         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 834         struct radeon_pll *spll = &rdev->clock.spll;
 835         struct radeon_pll *mpll = &rdev->clock.mpll;
 836         uint16_t data_offset;
 837
 838         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 839                                &crev, &data_offset);
 840
 841         firmware_info =
 842             (union firmware_info *)(mode_info->atom_context->bios +
 843                                     data_offset);
 844
 845         if (firmware_info) {
 846                 /* pixel clocks */
 847                 p1pll->reference_freq =
 848                     le16_to_cpu(firmware_info->info.usReferenceClock);
 849                 p1pll->reference_div = 0;
 850
 851                 if (crev < 2)
 852                         p1pll->pll_out_min =
 853                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 854                 else
 855                         p1pll->pll_out_min =
 856                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 857                 p1pll->pll_out_max =
 858                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 859
 860                 if (p1pll->pll_out_min == 0) {
 861                         if (ASIC_IS_AVIVO(rdev))
 862                                 p1pll->pll_out_min = 64800;
 863                         else
 864                                 p1pll->pll_out_min = 20000;
 865                 } else if (p1pll->pll_out_min > 64800) {
 866                         /* Limiting the pll output range is a good thing generally as
 867                          * it limits the number of possible pll combinations for a given
 868                          * frequency presumably to the ones that work best on each card.
 869                          * However, certain duallink DVI monitors seem to like
 870                          * pll combinations that would be limited by this at least on
 871                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 872                          * family.
 873                          */
 874                         if (!radeon_new_pll)
 875                                 p1pll->pll_out_min = 64800;
 876                 }
 877
 878                 p1pll->pll_in_min =
 879                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 880                 p1pll->pll_in_max =
 881                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 882
 883                 *p2pll = *p1pll;
 884
 885                 /* system clock */
 886                 spll->reference_freq =
 887                     le16_to_cpu(firmware_info->info.usReferenceClock);
 888                 spll->reference_div = 0;
 889
 890                 spll->pll_out_min =
 891                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 892                 spll->pll_out_max =
 893                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 894
 895                 /* ??? */
 896                 if (spll->pll_out_min == 0) {
 897                         if (ASIC_IS_AVIVO(rdev))
 898                                 spll->pll_out_min = 64800;
 899                         else
 900                                 spll->pll_out_min = 20000;
 901                 }
 902
 903                 spll->pll_in_min =
 904                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 905                 spll->pll_in_max =
 906                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 907
 908                 /* memory clock */
 909                 mpll->reference_freq =
 910                     le16_to_cpu(firmware_info->info.usReferenceClock);
 911                 mpll->reference_div = 0;
 912
 913                 mpll->pll_out_min =
 914                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 915                 mpll->pll_out_max =
 916                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 917
 918                 /* ??? */
 919                 if (mpll->pll_out_min == 0) {
 920                         if (ASIC_IS_AVIVO(rdev))
 921                                 mpll->pll_out_min = 64800;
 922                         else
 923                                 mpll->pll_out_min = 20000;
 924                 }
 925
 926                 mpll->pll_in_min =
 927                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 928                 mpll->pll_in_max =
 929                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 930
 931                 rdev->clock.default_sclk =
 932                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 933                 rdev->clock.default_mclk =
 934                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 935
 936                 return true;
 937         }
 938         return false;
 939 }
 940
 941 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 942                                    struct radeon_encoder_int_tmds *tmds)
 943 {
 944         struct drm_device *dev = encoder->base.dev;
 945         struct radeon_device *rdev = dev->dev_private;
 946         struct radeon_mode_info *mode_info = &rdev->mode_info;
 947         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 948         uint16_t data_offset;
 949         struct _ATOM_TMDS_INFO *tmds_info;
 950         uint8_t frev, crev;
 951         uint16_t maxfreq;
 952         int i;
 953
 954         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 955                                &crev, &data_offset);
 956
 957         tmds_info =
 958             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 959                                        data_offset);
 960
 961         if (tmds_info) {
 962                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 963                 for (i = 0; i < 4; i++) {
 964                         tmds->tmds_pll[i].freq =
 965                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
 966                         tmds->tmds_pll[i].value =
 967                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
 968                         tmds->tmds_pll[i].value |=
 969                             (tmds_info->asMiscInfo[i].
 970                              ucPLL_VCO_Gain & 0x3f) << 6;
 971                         tmds->tmds_pll[i].value |=
 972                             (tmds_info->asMiscInfo[i].
 973                              ucPLL_DutyCycle & 0xf) << 12;
 974                         tmds->tmds_pll[i].value |=
 975                             (tmds_info->asMiscInfo[i].
 976                              ucPLL_VoltageSwing & 0xf) << 16;
 977
 978                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
 979                                   tmds->tmds_pll[i].freq,
 980                                   tmds->tmds_pll[i].value);
 981
 982                         if (maxfreq == tmds->tmds_pll[i].freq) {
 983                                 tmds->tmds_pll[i].freq = 0xffffffff;
 984                                 break;
 985                         }
 986                 }
 987                 return true;
 988         }
 989         return false;
 990 }
 991
 992 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
 993                                                           radeon_encoder
 994                                                           *encoder,
 995                                                           int id)
 996 {
 997         struct drm_device *dev = encoder->base.dev;
 998         struct radeon_device *rdev = dev->dev_private;
 999         struct radeon_mode_info *mode_info = &rdev->mode_info;
1000         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1001         uint16_t data_offset;
1002         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1003         uint8_t frev, crev;
1004         struct radeon_atom_ss *ss = NULL;
1005         int i;
1006
1007         if (id > ATOM_MAX_SS_ENTRY)
1008                 return NULL;
1009
1010         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1011                                &crev, &data_offset);
1012
1013         ss_info =
1014             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1015
1016         if (ss_info) {
1017                 ss =
1018                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1019
1020                 if (!ss)
1021                         return NULL;
1022
1023                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1024                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1025                                 ss->percentage =
1026                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1027                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1028                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1029                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1030                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1031                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1032                                 break;
1033                         }
1034                 }
1035         }
1036         return ss;
1037 }
1038
1039 union lvds_info {
1040         struct _ATOM_LVDS_INFO info;
1041         struct _ATOM_LVDS_INFO_V12 info_12;
1042 };
1043
1044 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1045                                                               radeon_encoder
1046                                                               *encoder)
1047 {
1048         struct drm_device *dev = encoder->base.dev;
1049         struct radeon_device *rdev = dev->dev_private;
1050         struct radeon_mode_info *mode_info = &rdev->mode_info;
1051         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1052         uint16_t data_offset, misc;
1053         union lvds_info *lvds_info;
1054         uint8_t frev, crev;
1055         struct radeon_encoder_atom_dig *lvds = NULL;
1056
1057         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1058                                &crev, &data_offset);
1059
1060         lvds_info =
1061             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1062
1063         if (lvds_info) {
1064                 lvds =
1065                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1066
1067                 if (!lvds)
1068                         return NULL;
1069
1070                 lvds->native_mode.clock =
1071                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1072                 lvds->native_mode.hdisplay =
1073                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1074                 lvds->native_mode.vdisplay =
1075                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1076                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1077                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1078                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1079                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1080                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1081                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1082                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1083                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1084                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1085                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1086                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1087                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1088                 lvds->panel_pwr_delay =
1089                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1090                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1091
1092                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1093                 if (misc & ATOM_VSYNC_POLARITY)
1094                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1095                 if (misc & ATOM_HSYNC_POLARITY)
1096                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1097                 if (misc & ATOM_COMPOSITESYNC)
1098                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1099                 if (misc & ATOM_INTERLACE)
1100                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1101                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1102                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1103
1104                 /* set crtc values */
1105                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1106
1107                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1108
1109                 encoder->native_mode = lvds->native_mode;
1110         }
1111         return lvds;
1112 }
1113
1114 struct radeon_encoder_primary_dac *
1115 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1116 {
1117         struct drm_device *dev = encoder->base.dev;
1118         struct radeon_device *rdev = dev->dev_private;
1119         struct radeon_mode_info *mode_info = &rdev->mode_info;
1120         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1121         uint16_t data_offset;
1122         struct _COMPASSIONATE_DATA *dac_info;
1123         uint8_t frev, crev;
1124         uint8_t bg, dac;
1125         struct radeon_encoder_primary_dac *p_dac = NULL;
1126
1127         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1128
1129         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1130
1131         if (dac_info) {
1132                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1133
1134                 if (!p_dac)
1135                         return NULL;
1136
1137                 bg = dac_info->ucDAC1_BG_Adjustment;
1138                 dac = dac_info->ucDAC1_DAC_Adjustment;
1139                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1140
1141         }
1142         return p_dac;
1143 }
1144
1145 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1146                                 struct drm_display_mode *mode)
1147 {
1148         struct radeon_mode_info *mode_info = &rdev->mode_info;
1149         ATOM_ANALOG_TV_INFO *tv_info;
1150         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1151         ATOM_DTD_FORMAT *dtd_timings;
1152         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1153         u8 frev, crev;
1154         u16 data_offset, misc;
1155
1156         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1157
1158         switch (crev) {
1159         case 1:
1160                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1161                 if (index > MAX_SUPPORTED_TV_TIMING)
1162                         return false;
1163
1164                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1165                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1166                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1167                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1168                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1169
1170                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1171                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1172                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1173                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1174                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1175
1176                 mode->flags = 0;
1177                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1178                 if (misc & ATOM_VSYNC_POLARITY)
1179                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1180                 if (misc & ATOM_HSYNC_POLARITY)
1181                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1182                 if (misc & ATOM_COMPOSITESYNC)
1183                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1184                 if (misc & ATOM_INTERLACE)
1185                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1186                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1187                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1188
1189                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1190
1191                 if (index == 1) {
1192                         /* PAL timings appear to have wrong values for totals */
1193                         mode->crtc_htotal -= 1;
1194                         mode->crtc_vtotal -= 1;
1195                 }
1196                 break;
1197         case 2:
1198                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1199                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1200                         return false;
1201
1202                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1203                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1204                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1205                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1206                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1207                         le16_to_cpu(dtd_timings->usHSyncOffset);
1208                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1209                         le16_to_cpu(dtd_timings->usHSyncWidth);
1210
1211                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1212                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1213                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1214                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1215                         le16_to_cpu(dtd_timings->usVSyncOffset);
1216                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1217                         le16_to_cpu(dtd_timings->usVSyncWidth);
1218
1219                 mode->flags = 0;
1220                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1221                 if (misc & ATOM_VSYNC_POLARITY)
1222                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1223                 if (misc & ATOM_HSYNC_POLARITY)
1224                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1225                 if (misc & ATOM_COMPOSITESYNC)
1226                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1227                 if (misc & ATOM_INTERLACE)
1228                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1229                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1230                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1231
1232                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1233                 break;
1234         }
1235         return true;
1236 }
1237
1238 enum radeon_tv_std
1239 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1240 {
1241         struct radeon_mode_info *mode_info = &rdev->mode_info;
1242         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1243         uint16_t data_offset;
1244         uint8_t frev, crev;
1245         struct _ATOM_ANALOG_TV_INFO *tv_info;
1246         enum radeon_tv_std tv_std = TV_STD_NTSC;
1247
1248         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1249
1250         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1251
1252         switch (tv_info->ucTV_BootUpDefaultStandard) {
1253         case ATOM_TV_NTSC:
1254                 tv_std = TV_STD_NTSC;
1255                 DRM_INFO("Default TV standard: NTSC\n");
1256                 break;
1257         case ATOM_TV_NTSCJ:
1258                 tv_std = TV_STD_NTSC_J;
1259                 DRM_INFO("Default TV standard: NTSC-J\n");
1260                 break;
1261         case ATOM_TV_PAL:
1262                 tv_std = TV_STD_PAL;
1263                 DRM_INFO("Default TV standard: PAL\n");
1264                 break;
1265         case ATOM_TV_PALM:
1266                 tv_std = TV_STD_PAL_M;
1267                 DRM_INFO("Default TV standard: PAL-M\n");
1268                 break;
1269         case ATOM_TV_PALN:
1270                 tv_std = TV_STD_PAL_N;
1271                 DRM_INFO("Default TV standard: PAL-N\n");
1272                 break;
1273         case ATOM_TV_PALCN:
1274                 tv_std = TV_STD_PAL_CN;
1275                 DRM_INFO("Default TV standard: PAL-CN\n");
1276                 break;
1277         case ATOM_TV_PAL60:
1278                 tv_std = TV_STD_PAL_60;
1279                 DRM_INFO("Default TV standard: PAL-60\n");
1280                 break;
1281         case ATOM_TV_SECAM:
1282                 tv_std = TV_STD_SECAM;
1283                 DRM_INFO("Default TV standard: SECAM\n");
1284                 break;
1285         default:
1286                 tv_std = TV_STD_NTSC;
1287                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1288                 break;
1289         }
1290         return tv_std;
1291 }
1292
1293 struct radeon_encoder_tv_dac *
1294 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1295 {
1296         struct drm_device *dev = encoder->base.dev;
1297         struct radeon_device *rdev = dev->dev_private;
1298         struct radeon_mode_info *mode_info = &rdev->mode_info;
1299         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1300         uint16_t data_offset;
1301         struct _COMPASSIONATE_DATA *dac_info;
1302         uint8_t frev, crev;
1303         uint8_t bg, dac;
1304         struct radeon_encoder_tv_dac *tv_dac = NULL;
1305
1306         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1307
1308         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1309
1310         if (dac_info) {
1311                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1312
1313                 if (!tv_dac)
1314                         return NULL;
1315
1316                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1317                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1318                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1319
1320                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1321                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1322                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1323
1324                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1325                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1326                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1327
1328                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1329         }
1330         return tv_dac;
1331 }
1332
1333 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1334 {
1335         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1336         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1337
1338         args.ucEnable = enable;
1339
1340         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1341 }
1342
1343 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1344 {
1345         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1346         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1347
1348         args.ucEnable = enable;
1349
1350         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1351 }
1352
1353 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1354 {
1355         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1356         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1357
1358         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1359         return args.ulReturnEngineClock;
1360 }
1361
1362 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1363 {
1364         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1365         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1366
1367         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1368         return args.ulReturnMemoryClock;
1369 }
1370
1371 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1372                                   uint32_t eng_clock)
1373 {
1374         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1375         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1376
1377         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1378
1379         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1380 }
1381
1382 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1383                                   uint32_t mem_clock)
1384 {
1385         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1386         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1387
1388         if (rdev->flags & RADEON_IS_IGP)
1389                 return;
1390
1391         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1392
1393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1394 }
1395
1396 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1397 {
1398         struct radeon_device *rdev = dev->dev_private;
1399         uint32_t bios_2_scratch, bios_6_scratch;
1400
1401         if (rdev->family >= CHIP_R600) {
1402                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1403                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1404         } else {
1405                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1406                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1407         }
1408
1409         /* let the bios control the backlight */
1410         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1411
1412         /* tell the bios not to handle mode switching */
1413         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1414
1415         if (rdev->family >= CHIP_R600) {
1416                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1417                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1418         } else {
1419                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1420                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1421         }
1422
1423 }
1424
1425 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1426 {
1427         uint32_t scratch_reg;
1428         int i;
1429
1430         if (rdev->family >= CHIP_R600)
1431                 scratch_reg = R600_BIOS_0_SCRATCH;
1432         else
1433                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1434
1435         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1436                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1437 }
1438
1439 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1440 {
1441         uint32_t scratch_reg;
1442         int i;
1443
1444         if (rdev->family >= CHIP_R600)
1445                 scratch_reg = R600_BIOS_0_SCRATCH;
1446         else
1447                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1448
1449         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1450                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1451 }
1452
1453 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1454 {
1455         struct drm_device *dev = encoder->dev;
1456         struct radeon_device *rdev = dev->dev_private;
1457         uint32_t bios_6_scratch;
1458
1459         if (rdev->family >= CHIP_R600)
1460                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1461         else
1462                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1463
1464         if (lock)
1465                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1466         else
1467                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1468
1469         if (rdev->family >= CHIP_R600)
1470                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1471         else
1472                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1473 }
1474
1475 /* at some point we may want to break this out into individual functions */
1476 void
1477 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1478                                        struct drm_encoder *encoder,
1479                                        bool connected)
1480 {
1481         struct drm_device *dev = connector->dev;
1482         struct radeon_device *rdev = dev->dev_private;
1483         struct radeon_connector *radeon_connector =
1484             to_radeon_connector(connector);
1485         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1486         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1487
1488         if (rdev->family >= CHIP_R600) {
1489                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1490                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1491                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1492         } else {
1493                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1494                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1495                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1496         }
1497
1498         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1499             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1500                 if (connected) {
1501                         DRM_DEBUG("TV1 connected\n");
1502                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1503                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1504                 } else {
1505                         DRM_DEBUG("TV1 disconnected\n");
1506                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1507                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1508                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1509                 }
1510         }
1511         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1512             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1513                 if (connected) {
1514                         DRM_DEBUG("CV connected\n");
1515                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1516                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1517                 } else {
1518                         DRM_DEBUG("CV disconnected\n");
1519                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1520                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1521                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1522                 }
1523         }
1524         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1525             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1526                 if (connected) {
1527                         DRM_DEBUG("LCD1 connected\n");
1528                         bios_0_scratch |= ATOM_S0_LCD1;
1529                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1530                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1531                 } else {
1532                         DRM_DEBUG("LCD1 disconnected\n");
1533                         bios_0_scratch &= ~ATOM_S0_LCD1;
1534                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1535                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1536                 }
1537         }
1538         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1539             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1540                 if (connected) {
1541                         DRM_DEBUG("CRT1 connected\n");
1542                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1543                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1544                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1545                 } else {
1546                         DRM_DEBUG("CRT1 disconnected\n");
1547                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1548                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1549                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1550                 }
1551         }
1552         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1553             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1554                 if (connected) {
1555                         DRM_DEBUG("CRT2 connected\n");
1556                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1557                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1558                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1559                 } else {
1560                         DRM_DEBUG("CRT2 disconnected\n");
1561                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1562                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1563                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1564                 }
1565         }
1566         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1567             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1568                 if (connected) {
1569                         DRM_DEBUG("DFP1 connected\n");
1570                         bios_0_scratch |= ATOM_S0_DFP1;
1571                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1572                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1573                 } else {
1574                         DRM_DEBUG("DFP1 disconnected\n");
1575                         bios_0_scratch &= ~ATOM_S0_DFP1;
1576                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1577                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1578                 }
1579         }
1580         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1581             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1582                 if (connected) {
1583                         DRM_DEBUG("DFP2 connected\n");
1584                         bios_0_scratch |= ATOM_S0_DFP2;
1585                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1586                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1587                 } else {
1588                         DRM_DEBUG("DFP2 disconnected\n");
1589                         bios_0_scratch &= ~ATOM_S0_DFP2;
1590                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1591                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1592                 }
1593         }
1594         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1595             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1596                 if (connected) {
1597                         DRM_DEBUG("DFP3 connected\n");
1598                         bios_0_scratch |= ATOM_S0_DFP3;
1599                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1600                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1601                 } else {
1602                         DRM_DEBUG("DFP3 disconnected\n");
1603                         bios_0_scratch &= ~ATOM_S0_DFP3;
1604                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1605                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1606                 }
1607         }
1608         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1609             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1610                 if (connected) {
1611                         DRM_DEBUG("DFP4 connected\n");
1612                         bios_0_scratch |= ATOM_S0_DFP4;
1613                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1614                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1615                 } else {
1616                         DRM_DEBUG("DFP4 disconnected\n");
1617                         bios_0_scratch &= ~ATOM_S0_DFP4;
1618                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1619                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1620                 }
1621         }
1622         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1623             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1624                 if (connected) {
1625                         DRM_DEBUG("DFP5 connected\n");
1626                         bios_0_scratch |= ATOM_S0_DFP5;
1627                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1628                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1629                 } else {
1630                         DRM_DEBUG("DFP5 disconnected\n");
1631                         bios_0_scratch &= ~ATOM_S0_DFP5;
1632                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1633                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1634                 }
1635         }
1636
1637         if (rdev->family >= CHIP_R600) {
1638                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1639                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1640                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1641         } else {
1642                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1643                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1644                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1645         }
1646 }
1647
1648 void
1649 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1650 {
1651         struct drm_device *dev = encoder->dev;
1652         struct radeon_device *rdev = dev->dev_private;
1653         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1654         uint32_t bios_3_scratch;
1655
1656         if (rdev->family >= CHIP_R600)
1657                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1658         else
1659                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1660
1661         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1662                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1663                 bios_3_scratch |= (crtc << 18);
1664         }
1665         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1666                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1667                 bios_3_scratch |= (crtc << 24);
1668         }
1669         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1670                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1671                 bios_3_scratch |= (crtc << 16);
1672         }
1673         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1674                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1675                 bios_3_scratch |= (crtc << 20);
1676         }
1677         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1678                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1679                 bios_3_scratch |= (crtc << 17);
1680         }
1681         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1682                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1683                 bios_3_scratch |= (crtc << 19);
1684         }
1685         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1686                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1687                 bios_3_scratch |= (crtc << 23);
1688         }
1689         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1690                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1691                 bios_3_scratch |= (crtc << 25);
1692         }
1693
1694         if (rdev->family >= CHIP_R600)
1695                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1696         else
1697                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1698 }
1699
1700 void
1701 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1702 {
1703         struct drm_device *dev = encoder->dev;
1704         struct radeon_device *rdev = dev->dev_private;
1705         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1706         uint32_t bios_2_scratch;
1707
1708         if (rdev->family >= CHIP_R600)
1709                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1710         else
1711                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1712
1713         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1714                 if (on)
1715                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1716                 else
1717                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1718         }
1719         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1720                 if (on)
1721                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1722                 else
1723                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1724         }
1725         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1726                 if (on)
1727                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1728                 else
1729                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1730         }
1731         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1732                 if (on)
1733                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1734                 else
1735                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1736         }
1737         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1738                 if (on)
1739                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1740                 else
1741                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1742         }
1743         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1744                 if (on)
1745                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1746                 else
1747                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1748         }
1749         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1750                 if (on)
1751                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1752                 else
1753                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1754         }
1755         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1756                 if (on)
1757                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1758                 else
1759                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1760         }
1761         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1762                 if (on)
1763                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1764                 else
1765                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1766         }
1767         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1768                 if (on)
1769                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1770                 else
1771                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1772         }
1773
1774         if (rdev->family >= CHIP_R600)
1775                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1776         else
1777                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1778 }