SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .cp_commit = &r100_cp_commit,
 142         .ring_start = &r100_ring_start,
 143         .ring_test = &r100_ring_test,
 144         .ring_ib_execute = &r100_ring_ib_execute,
 145         .irq_set = &r100_irq_set,
 146         .irq_process = &r100_irq_process,
 147         .get_vblank_counter = &r100_get_vblank_counter,
 148         .fence_ring_emit = &r100_fence_ring_emit,
 149         .cs_parse = &r100_cs_parse,
 150         .copy_blit = &r100_copy_blit,
 151         .copy_dma = NULL,
 152         .copy = &r100_copy_blit,
 153         .get_engine_clock = &radeon_legacy_get_engine_clock,
 154         .set_engine_clock = &radeon_legacy_set_engine_clock,
 155         .get_memory_clock = &radeon_legacy_get_memory_clock,
 156         .set_memory_clock = NULL,
 157         .get_pcie_lanes = NULL,
 158         .set_pcie_lanes = NULL,
 159         .set_clock_gating = &radeon_legacy_set_clock_gating,
 160         .set_surface_reg = r100_set_surface_reg,
 161         .clear_surface_reg = r100_clear_surface_reg,
 162         .bandwidth_update = &r100_bandwidth_update,
 163         .hpd_init = &r100_hpd_init,
 164         .hpd_fini = &r100_hpd_fini,
 165         .hpd_sense = &r100_hpd_sense,
 166         .hpd_set_polarity = &r100_hpd_set_polarity,
 167         .ioctl_wait_idle = NULL,
 168         .gui_idle = &r100_gui_idle,
 169         .set_power_state = &r100_set_power_state,
 170 };
 171
 172 static struct radeon_asic r200_asic = {
 173         .init = &r100_init,
 174         .fini = &r100_fini,
 175         .suspend = &r100_suspend,
 176         .resume = &r100_resume,
 177         .vga_set_state = &r100_vga_set_state,
 178         .gpu_is_lockup = &r100_gpu_is_lockup,
 179         .asic_reset = &r100_asic_reset,
 180         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 181         .gart_set_page = &r100_pci_gart_set_page,
 182         .cp_commit = &r100_cp_commit,
 183         .ring_start = &r100_ring_start,
 184         .ring_test = &r100_ring_test,
 185         .ring_ib_execute = &r100_ring_ib_execute,
 186         .irq_set = &r100_irq_set,
 187         .irq_process = &r100_irq_process,
 188         .get_vblank_counter = &r100_get_vblank_counter,
 189         .fence_ring_emit = &r100_fence_ring_emit,
 190         .cs_parse = &r100_cs_parse,
 191         .copy_blit = &r100_copy_blit,
 192         .copy_dma = &r200_copy_dma,
 193         .copy = &r100_copy_blit,
 194         .get_engine_clock = &radeon_legacy_get_engine_clock,
 195         .set_engine_clock = &radeon_legacy_set_engine_clock,
 196         .get_memory_clock = &radeon_legacy_get_memory_clock,
 197         .set_memory_clock = NULL,
 198         .set_pcie_lanes = NULL,
 199         .set_clock_gating = &radeon_legacy_set_clock_gating,
 200         .set_surface_reg = r100_set_surface_reg,
 201         .clear_surface_reg = r100_clear_surface_reg,
 202         .bandwidth_update = &r100_bandwidth_update,
 203         .hpd_init = &r100_hpd_init,
 204         .hpd_fini = &r100_hpd_fini,
 205         .hpd_sense = &r100_hpd_sense,
 206         .hpd_set_polarity = &r100_hpd_set_polarity,
 207         .ioctl_wait_idle = NULL,
 208         .gui_idle = &r100_gui_idle,
 209         .set_power_state = &r100_set_power_state,
 210 };
 211
 212 static struct radeon_asic r300_asic = {
 213         .init = &r300_init,
 214         .fini = &r300_fini,
 215         .suspend = &r300_suspend,
 216         .resume = &r300_resume,
 217         .vga_set_state = &r100_vga_set_state,
 218         .gpu_is_lockup = &r300_gpu_is_lockup,
 219         .asic_reset = &r300_asic_reset,
 220         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 221         .gart_set_page = &r100_pci_gart_set_page,
 222         .cp_commit = &r100_cp_commit,
 223         .ring_start = &r300_ring_start,
 224         .ring_test = &r100_ring_test,
 225         .ring_ib_execute = &r100_ring_ib_execute,
 226         .irq_set = &r100_irq_set,
 227         .irq_process = &r100_irq_process,
 228         .get_vblank_counter = &r100_get_vblank_counter,
 229         .fence_ring_emit = &r300_fence_ring_emit,
 230         .cs_parse = &r300_cs_parse,
 231         .copy_blit = &r100_copy_blit,
 232         .copy_dma = &r200_copy_dma,
 233         .copy = &r100_copy_blit,
 234         .get_engine_clock = &radeon_legacy_get_engine_clock,
 235         .set_engine_clock = &radeon_legacy_set_engine_clock,
 236         .get_memory_clock = &radeon_legacy_get_memory_clock,
 237         .set_memory_clock = NULL,
 238         .get_pcie_lanes = &rv370_get_pcie_lanes,
 239         .set_pcie_lanes = &rv370_set_pcie_lanes,
 240         .set_clock_gating = &radeon_legacy_set_clock_gating,
 241         .set_surface_reg = r100_set_surface_reg,
 242         .clear_surface_reg = r100_clear_surface_reg,
 243         .bandwidth_update = &r100_bandwidth_update,
 244         .hpd_init = &r100_hpd_init,
 245         .hpd_fini = &r100_hpd_fini,
 246         .hpd_sense = &r100_hpd_sense,
 247         .hpd_set_polarity = &r100_hpd_set_polarity,
 248         .ioctl_wait_idle = NULL,
 249         .gui_idle = &r100_gui_idle,
 250         .set_power_state = &r100_set_power_state,
 251 };
 252
 253 static struct radeon_asic r300_asic_pcie = {
 254         .init = &r300_init,
 255         .fini = &r300_fini,
 256         .suspend = &r300_suspend,
 257         .resume = &r300_resume,
 258         .vga_set_state = &r100_vga_set_state,
 259         .gpu_is_lockup = &r300_gpu_is_lockup,
 260         .asic_reset = &r300_asic_reset,
 261         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 262         .gart_set_page = &rv370_pcie_gart_set_page,
 263         .cp_commit = &r100_cp_commit,
 264         .ring_start = &r300_ring_start,
 265         .ring_test = &r100_ring_test,
 266         .ring_ib_execute = &r100_ring_ib_execute,
 267         .irq_set = &r100_irq_set,
 268         .irq_process = &r100_irq_process,
 269         .get_vblank_counter = &r100_get_vblank_counter,
 270         .fence_ring_emit = &r300_fence_ring_emit,
 271         .cs_parse = &r300_cs_parse,
 272         .copy_blit = &r100_copy_blit,
 273         .copy_dma = &r200_copy_dma,
 274         .copy = &r100_copy_blit,
 275         .get_engine_clock = &radeon_legacy_get_engine_clock,
 276         .set_engine_clock = &radeon_legacy_set_engine_clock,
 277         .get_memory_clock = &radeon_legacy_get_memory_clock,
 278         .set_memory_clock = NULL,
 279         .set_pcie_lanes = &rv370_set_pcie_lanes,
 280         .set_clock_gating = &radeon_legacy_set_clock_gating,
 281         .set_surface_reg = r100_set_surface_reg,
 282         .clear_surface_reg = r100_clear_surface_reg,
 283         .bandwidth_update = &r100_bandwidth_update,
 284         .hpd_init = &r100_hpd_init,
 285         .hpd_fini = &r100_hpd_fini,
 286         .hpd_sense = &r100_hpd_sense,
 287         .hpd_set_polarity = &r100_hpd_set_polarity,
 288         .ioctl_wait_idle = NULL,
 289         .gui_idle = &r100_gui_idle,
 290         .set_power_state = &r100_set_power_state,
 291 };
 292
 293 static struct radeon_asic r420_asic = {
 294         .init = &r420_init,
 295         .fini = &r420_fini,
 296         .suspend = &r420_suspend,
 297         .resume = &r420_resume,
 298         .vga_set_state = &r100_vga_set_state,
 299         .gpu_is_lockup = &r300_gpu_is_lockup,
 300         .asic_reset = &r300_asic_reset,
 301         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 302         .gart_set_page = &rv370_pcie_gart_set_page,
 303         .cp_commit = &r100_cp_commit,
 304         .ring_start = &r300_ring_start,
 305         .ring_test = &r100_ring_test,
 306         .ring_ib_execute = &r100_ring_ib_execute,
 307         .irq_set = &r100_irq_set,
 308         .irq_process = &r100_irq_process,
 309         .get_vblank_counter = &r100_get_vblank_counter,
 310         .fence_ring_emit = &r300_fence_ring_emit,
 311         .cs_parse = &r300_cs_parse,
 312         .copy_blit = &r100_copy_blit,
 313         .copy_dma = &r200_copy_dma,
 314         .copy = &r100_copy_blit,
 315         .get_engine_clock = &radeon_atom_get_engine_clock,
 316         .set_engine_clock = &radeon_atom_set_engine_clock,
 317         .get_memory_clock = &radeon_atom_get_memory_clock,
 318         .set_memory_clock = &radeon_atom_set_memory_clock,
 319         .get_pcie_lanes = &rv370_get_pcie_lanes,
 320         .set_pcie_lanes = &rv370_set_pcie_lanes,
 321         .set_clock_gating = &radeon_atom_set_clock_gating,
 322         .set_surface_reg = r100_set_surface_reg,
 323         .clear_surface_reg = r100_clear_surface_reg,
 324         .bandwidth_update = &r100_bandwidth_update,
 325         .hpd_init = &r100_hpd_init,
 326         .hpd_fini = &r100_hpd_fini,
 327         .hpd_sense = &r100_hpd_sense,
 328         .hpd_set_polarity = &r100_hpd_set_polarity,
 329         .ioctl_wait_idle = NULL,
 330         .gui_idle = &r100_gui_idle,
 331         .set_power_state = &r100_set_power_state,
 332 };
 333
 334 static struct radeon_asic rs400_asic = {
 335         .init = &rs400_init,
 336         .fini = &rs400_fini,
 337         .suspend = &rs400_suspend,
 338         .resume = &rs400_resume,
 339         .vga_set_state = &r100_vga_set_state,
 340         .gpu_is_lockup = &r300_gpu_is_lockup,
 341         .asic_reset = &r300_asic_reset,
 342         .gart_tlb_flush = &rs400_gart_tlb_flush,
 343         .gart_set_page = &rs400_gart_set_page,
 344         .cp_commit = &r100_cp_commit,
 345         .ring_start = &r300_ring_start,
 346         .ring_test = &r100_ring_test,
 347         .ring_ib_execute = &r100_ring_ib_execute,
 348         .irq_set = &r100_irq_set,
 349         .irq_process = &r100_irq_process,
 350         .get_vblank_counter = &r100_get_vblank_counter,
 351         .fence_ring_emit = &r300_fence_ring_emit,
 352         .cs_parse = &r300_cs_parse,
 353         .copy_blit = &r100_copy_blit,
 354         .copy_dma = &r200_copy_dma,
 355         .copy = &r100_copy_blit,
 356         .get_engine_clock = &radeon_legacy_get_engine_clock,
 357         .set_engine_clock = &radeon_legacy_set_engine_clock,
 358         .get_memory_clock = &radeon_legacy_get_memory_clock,
 359         .set_memory_clock = NULL,
 360         .get_pcie_lanes = NULL,
 361         .set_pcie_lanes = NULL,
 362         .set_clock_gating = &radeon_legacy_set_clock_gating,
 363         .set_surface_reg = r100_set_surface_reg,
 364         .clear_surface_reg = r100_clear_surface_reg,
 365         .bandwidth_update = &r100_bandwidth_update,
 366         .hpd_init = &r100_hpd_init,
 367         .hpd_fini = &r100_hpd_fini,
 368         .hpd_sense = &r100_hpd_sense,
 369         .hpd_set_polarity = &r100_hpd_set_polarity,
 370         .ioctl_wait_idle = NULL,
 371         .gui_idle = &r100_gui_idle,
 372         .set_power_state = &r100_set_power_state,
 373 };
 374
 375 static struct radeon_asic rs600_asic = {
 376         .init = &rs600_init,
 377         .fini = &rs600_fini,
 378         .suspend = &rs600_suspend,
 379         .resume = &rs600_resume,
 380         .vga_set_state = &r100_vga_set_state,
 381         .gpu_is_lockup = &r300_gpu_is_lockup,
 382         .asic_reset = &rs600_asic_reset,
 383         .gart_tlb_flush = &rs600_gart_tlb_flush,
 384         .gart_set_page = &rs600_gart_set_page,
 385         .cp_commit = &r100_cp_commit,
 386         .ring_start = &r300_ring_start,
 387         .ring_test = &r100_ring_test,
 388         .ring_ib_execute = &r100_ring_ib_execute,
 389         .irq_set = &rs600_irq_set,
 390         .irq_process = &rs600_irq_process,
 391         .get_vblank_counter = &rs600_get_vblank_counter,
 392         .fence_ring_emit = &r300_fence_ring_emit,
 393         .cs_parse = &r300_cs_parse,
 394         .copy_blit = &r100_copy_blit,
 395         .copy_dma = &r200_copy_dma,
 396         .copy = &r100_copy_blit,
 397         .get_engine_clock = &radeon_atom_get_engine_clock,
 398         .set_engine_clock = &radeon_atom_set_engine_clock,
 399         .get_memory_clock = &radeon_atom_get_memory_clock,
 400         .set_memory_clock = &radeon_atom_set_memory_clock,
 401         .get_pcie_lanes = NULL,
 402         .set_pcie_lanes = NULL,
 403         .set_clock_gating = &radeon_atom_set_clock_gating,
 404         .set_surface_reg = r100_set_surface_reg,
 405         .clear_surface_reg = r100_clear_surface_reg,
 406         .bandwidth_update = &rs600_bandwidth_update,
 407         .hpd_init = &rs600_hpd_init,
 408         .hpd_fini = &rs600_hpd_fini,
 409         .hpd_sense = &rs600_hpd_sense,
 410         .hpd_set_polarity = &rs600_hpd_set_polarity,
 411         .ioctl_wait_idle = NULL,
 412         .gui_idle = &r100_gui_idle,
 413         .set_power_state = &r100_set_power_state,
 414 };
 415
 416 static struct radeon_asic rs690_asic = {
 417         .init = &rs690_init,
 418         .fini = &rs690_fini,
 419         .suspend = &rs690_suspend,
 420         .resume = &rs690_resume,
 421         .vga_set_state = &r100_vga_set_state,
 422         .gpu_is_lockup = &r300_gpu_is_lockup,
 423         .asic_reset = &rs600_asic_reset,
 424         .gart_tlb_flush = &rs400_gart_tlb_flush,
 425         .gart_set_page = &rs400_gart_set_page,
 426         .cp_commit = &r100_cp_commit,
 427         .ring_start = &r300_ring_start,
 428         .ring_test = &r100_ring_test,
 429         .ring_ib_execute = &r100_ring_ib_execute,
 430         .irq_set = &rs600_irq_set,
 431         .irq_process = &rs600_irq_process,
 432         .get_vblank_counter = &rs600_get_vblank_counter,
 433         .fence_ring_emit = &r300_fence_ring_emit,
 434         .cs_parse = &r300_cs_parse,
 435         .copy_blit = &r100_copy_blit,
 436         .copy_dma = &r200_copy_dma,
 437         .copy = &r200_copy_dma,
 438         .get_engine_clock = &radeon_atom_get_engine_clock,
 439         .set_engine_clock = &radeon_atom_set_engine_clock,
 440         .get_memory_clock = &radeon_atom_get_memory_clock,
 441         .set_memory_clock = &radeon_atom_set_memory_clock,
 442         .get_pcie_lanes = NULL,
 443         .set_pcie_lanes = NULL,
 444         .set_clock_gating = &radeon_atom_set_clock_gating,
 445         .set_surface_reg = r100_set_surface_reg,
 446         .clear_surface_reg = r100_clear_surface_reg,
 447         .bandwidth_update = &rs690_bandwidth_update,
 448         .hpd_init = &rs600_hpd_init,
 449         .hpd_fini = &rs600_hpd_fini,
 450         .hpd_sense = &rs600_hpd_sense,
 451         .hpd_set_polarity = &rs600_hpd_set_polarity,
 452         .ioctl_wait_idle = NULL,
 453         .gui_idle = &r100_gui_idle,
 454         .set_power_state = &r100_set_power_state,
 455 };
 456
 457 static struct radeon_asic rv515_asic = {
 458         .init = &rv515_init,
 459         .fini = &rv515_fini,
 460         .suspend = &rv515_suspend,
 461         .resume = &rv515_resume,
 462         .vga_set_state = &r100_vga_set_state,
 463         .gpu_is_lockup = &r300_gpu_is_lockup,
 464         .asic_reset = &rs600_asic_reset,
 465         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 466         .gart_set_page = &rv370_pcie_gart_set_page,
 467         .cp_commit = &r100_cp_commit,
 468         .ring_start = &rv515_ring_start,
 469         .ring_test = &r100_ring_test,
 470         .ring_ib_execute = &r100_ring_ib_execute,
 471         .irq_set = &rs600_irq_set,
 472         .irq_process = &rs600_irq_process,
 473         .get_vblank_counter = &rs600_get_vblank_counter,
 474         .fence_ring_emit = &r300_fence_ring_emit,
 475         .cs_parse = &r300_cs_parse,
 476         .copy_blit = &r100_copy_blit,
 477         .copy_dma = &r200_copy_dma,
 478         .copy = &r100_copy_blit,
 479         .get_engine_clock = &radeon_atom_get_engine_clock,
 480         .set_engine_clock = &radeon_atom_set_engine_clock,
 481         .get_memory_clock = &radeon_atom_get_memory_clock,
 482         .set_memory_clock = &radeon_atom_set_memory_clock,
 483         .get_pcie_lanes = &rv370_get_pcie_lanes,
 484         .set_pcie_lanes = &rv370_set_pcie_lanes,
 485         .set_clock_gating = &radeon_atom_set_clock_gating,
 486         .set_surface_reg = r100_set_surface_reg,
 487         .clear_surface_reg = r100_clear_surface_reg,
 488         .bandwidth_update = &rv515_bandwidth_update,
 489         .hpd_init = &rs600_hpd_init,
 490         .hpd_fini = &rs600_hpd_fini,
 491         .hpd_sense = &rs600_hpd_sense,
 492         .hpd_set_polarity = &rs600_hpd_set_polarity,
 493         .ioctl_wait_idle = NULL,
 494         .gui_idle = &r100_gui_idle,
 495         .set_power_state = &r100_set_power_state,
 496 };
 497
 498 static struct radeon_asic r520_asic = {
 499         .init = &r520_init,
 500         .fini = &rv515_fini,
 501         .suspend = &rv515_suspend,
 502         .resume = &r520_resume,
 503         .vga_set_state = &r100_vga_set_state,
 504         .gpu_is_lockup = &r300_gpu_is_lockup,
 505         .asic_reset = &rs600_asic_reset,
 506         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 507         .gart_set_page = &rv370_pcie_gart_set_page,
 508         .cp_commit = &r100_cp_commit,
 509         .ring_start = &rv515_ring_start,
 510         .ring_test = &r100_ring_test,
 511         .ring_ib_execute = &r100_ring_ib_execute,
 512         .irq_set = &rs600_irq_set,
 513         .irq_process = &rs600_irq_process,
 514         .get_vblank_counter = &rs600_get_vblank_counter,
 515         .fence_ring_emit = &r300_fence_ring_emit,
 516         .cs_parse = &r300_cs_parse,
 517         .copy_blit = &r100_copy_blit,
 518         .copy_dma = &r200_copy_dma,
 519         .copy = &r100_copy_blit,
 520         .get_engine_clock = &radeon_atom_get_engine_clock,
 521         .set_engine_clock = &radeon_atom_set_engine_clock,
 522         .get_memory_clock = &radeon_atom_get_memory_clock,
 523         .set_memory_clock = &radeon_atom_set_memory_clock,
 524         .get_pcie_lanes = &rv370_get_pcie_lanes,
 525         .set_pcie_lanes = &rv370_set_pcie_lanes,
 526         .set_clock_gating = &radeon_atom_set_clock_gating,
 527         .set_surface_reg = r100_set_surface_reg,
 528         .clear_surface_reg = r100_clear_surface_reg,
 529         .bandwidth_update = &rv515_bandwidth_update,
 530         .hpd_init = &rs600_hpd_init,
 531         .hpd_fini = &rs600_hpd_fini,
 532         .hpd_sense = &rs600_hpd_sense,
 533         .hpd_set_polarity = &rs600_hpd_set_polarity,
 534         .ioctl_wait_idle = NULL,
 535         .gui_idle = &r100_gui_idle,
 536         .set_power_state = &r100_set_power_state,
 537 };
 538
 539 static struct radeon_asic r600_asic = {
 540         .init = &r600_init,
 541         .fini = &r600_fini,
 542         .suspend = &r600_suspend,
 543         .resume = &r600_resume,
 544         .cp_commit = &r600_cp_commit,
 545         .vga_set_state = &r600_vga_set_state,
 546         .gpu_is_lockup = &r600_gpu_is_lockup,
 547         .asic_reset = &r600_asic_reset,
 548         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 549         .gart_set_page = &rs600_gart_set_page,
 550         .ring_test = &r600_ring_test,
 551         .ring_ib_execute = &r600_ring_ib_execute,
 552         .irq_set = &r600_irq_set,
 553         .irq_process = &r600_irq_process,
 554         .get_vblank_counter = &rs600_get_vblank_counter,
 555         .fence_ring_emit = &r600_fence_ring_emit,
 556         .cs_parse = &r600_cs_parse,
 557         .copy_blit = &r600_copy_blit,
 558         .copy_dma = &r600_copy_blit,
 559         .copy = &r600_copy_blit,
 560         .get_engine_clock = &radeon_atom_get_engine_clock,
 561         .set_engine_clock = &radeon_atom_set_engine_clock,
 562         .get_memory_clock = &radeon_atom_get_memory_clock,
 563         .set_memory_clock = &radeon_atom_set_memory_clock,
 564         .get_pcie_lanes = &rv370_get_pcie_lanes,
 565         .set_pcie_lanes = NULL,
 566         .set_clock_gating = NULL,
 567         .set_surface_reg = r600_set_surface_reg,
 568         .clear_surface_reg = r600_clear_surface_reg,
 569         .bandwidth_update = &rv515_bandwidth_update,
 570         .hpd_init = &r600_hpd_init,
 571         .hpd_fini = &r600_hpd_fini,
 572         .hpd_sense = &r600_hpd_sense,
 573         .hpd_set_polarity = &r600_hpd_set_polarity,
 574         .ioctl_wait_idle = r600_ioctl_wait_idle,
 575         .gui_idle = &r600_gui_idle,
 576         .set_power_state = &r600_set_power_state,
 577 };
 578
 579 static struct radeon_asic rs780_asic = {
 580         .init = &r600_init,
 581         .fini = &r600_fini,
 582         .suspend = &r600_suspend,
 583         .resume = &r600_resume,
 584         .cp_commit = &r600_cp_commit,
 585         .gpu_is_lockup = &r600_gpu_is_lockup,
 586         .vga_set_state = &r600_vga_set_state,
 587         .asic_reset = &r600_asic_reset,
 588         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 589         .gart_set_page = &rs600_gart_set_page,
 590         .ring_test = &r600_ring_test,
 591         .ring_ib_execute = &r600_ring_ib_execute,
 592         .irq_set = &r600_irq_set,
 593         .irq_process = &r600_irq_process,
 594         .get_vblank_counter = &rs600_get_vblank_counter,
 595         .fence_ring_emit = &r600_fence_ring_emit,
 596         .cs_parse = &r600_cs_parse,
 597         .copy_blit = &r600_copy_blit,
 598         .copy_dma = &r600_copy_blit,
 599         .copy = &r600_copy_blit,
 600         .get_engine_clock = &radeon_atom_get_engine_clock,
 601         .set_engine_clock = &radeon_atom_set_engine_clock,
 602         .get_memory_clock = NULL,
 603         .set_memory_clock = NULL,
 604         .get_pcie_lanes = NULL,
 605         .set_pcie_lanes = NULL,
 606         .set_clock_gating = NULL,
 607         .set_surface_reg = r600_set_surface_reg,
 608         .clear_surface_reg = r600_clear_surface_reg,
 609         .bandwidth_update = &rs690_bandwidth_update,
 610         .hpd_init = &r600_hpd_init,
 611         .hpd_fini = &r600_hpd_fini,
 612         .hpd_sense = &r600_hpd_sense,
 613         .hpd_set_polarity = &r600_hpd_set_polarity,
 614         .ioctl_wait_idle = r600_ioctl_wait_idle,
 615         .gui_idle = &r600_gui_idle,
 616         .set_power_state = &r600_set_power_state,
 617 };
 618
 619 static struct radeon_asic rv770_asic = {
 620         .init = &rv770_init,
 621         .fini = &rv770_fini,
 622         .suspend = &rv770_suspend,
 623         .resume = &rv770_resume,
 624         .cp_commit = &r600_cp_commit,
 625         .asic_reset = &r600_asic_reset,
 626         .gpu_is_lockup = &r600_gpu_is_lockup,
 627         .vga_set_state = &r600_vga_set_state,
 628         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 629         .gart_set_page = &rs600_gart_set_page,
 630         .ring_test = &r600_ring_test,
 631         .ring_ib_execute = &r600_ring_ib_execute,
 632         .irq_set = &r600_irq_set,
 633         .irq_process = &r600_irq_process,
 634         .get_vblank_counter = &rs600_get_vblank_counter,
 635         .fence_ring_emit = &r600_fence_ring_emit,
 636         .cs_parse = &r600_cs_parse,
 637         .copy_blit = &r600_copy_blit,
 638         .copy_dma = &r600_copy_blit,
 639         .copy = &r600_copy_blit,
 640         .get_engine_clock = &radeon_atom_get_engine_clock,
 641         .set_engine_clock = &radeon_atom_set_engine_clock,
 642         .get_memory_clock = &radeon_atom_get_memory_clock,
 643         .set_memory_clock = &radeon_atom_set_memory_clock,
 644         .get_pcie_lanes = &rv370_get_pcie_lanes,
 645         .set_pcie_lanes = NULL,
 646         .set_clock_gating = &radeon_atom_set_clock_gating,
 647         .set_surface_reg = r600_set_surface_reg,
 648         .clear_surface_reg = r600_clear_surface_reg,
 649         .bandwidth_update = &rv515_bandwidth_update,
 650         .hpd_init = &r600_hpd_init,
 651         .hpd_fini = &r600_hpd_fini,
 652         .hpd_sense = &r600_hpd_sense,
 653         .hpd_set_polarity = &r600_hpd_set_polarity,
 654         .ioctl_wait_idle = r600_ioctl_wait_idle,
 655         .gui_idle = &r600_gui_idle,
 656         .set_power_state = &r600_set_power_state,
 657 };
 658
 659 static struct radeon_asic evergreen_asic = {
 660         .init = &evergreen_init,
 661         .fini = &evergreen_fini,
 662         .suspend = &evergreen_suspend,
 663         .resume = &evergreen_resume,
 664         .cp_commit = &r600_cp_commit,
 665         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 666         .asic_reset = &evergreen_asic_reset,
 667         .vga_set_state = &r600_vga_set_state,
 668         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 669         .gart_set_page = &rs600_gart_set_page,
 670         .ring_test = &r600_ring_test,
 671         .ring_ib_execute = &r600_ring_ib_execute,
 672         .irq_set = &evergreen_irq_set,
 673         .irq_process = &evergreen_irq_process,
 674         .get_vblank_counter = &evergreen_get_vblank_counter,
 675         .fence_ring_emit = NULL,
 676         .cs_parse = NULL,
 677         .copy_blit = NULL,
 678         .copy_dma = NULL,
 679         .copy = NULL,
 680         .get_engine_clock = &radeon_atom_get_engine_clock,
 681         .set_engine_clock = &radeon_atom_set_engine_clock,
 682         .get_memory_clock = &radeon_atom_get_memory_clock,
 683         .set_memory_clock = &radeon_atom_set_memory_clock,
 684         .set_pcie_lanes = NULL,
 685         .set_clock_gating = NULL,
 686         .set_surface_reg = r600_set_surface_reg,
 687         .clear_surface_reg = r600_clear_surface_reg,
 688         .bandwidth_update = &evergreen_bandwidth_update,
 689         .hpd_init = &evergreen_hpd_init,
 690         .hpd_fini = &evergreen_hpd_fini,
 691         .hpd_sense = &evergreen_hpd_sense,
 692         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 693         .gui_idle = &r600_gui_idle,
 694         .set_power_state = &r600_set_power_state,
 695 };
 696
 697 int radeon_asic_init(struct radeon_device *rdev)
 698 {
 699         radeon_register_accessor_init(rdev);
 700         switch (rdev->family) {
 701         case CHIP_R100:
 702         case CHIP_RV100:
 703         case CHIP_RS100:
 704         case CHIP_RV200:
 705         case CHIP_RS200:
 706                 rdev->asic = &r100_asic;
 707                 break;
 708         case CHIP_R200:
 709         case CHIP_RV250:
 710         case CHIP_RS300:
 711         case CHIP_RV280:
 712                 rdev->asic = &r200_asic;
 713                 break;
 714         case CHIP_R300:
 715         case CHIP_R350:
 716         case CHIP_RV350:
 717         case CHIP_RV380:
 718                 if (rdev->flags & RADEON_IS_PCIE)
 719                         rdev->asic = &r300_asic_pcie;
 720                 else
 721                         rdev->asic = &r300_asic;
 722                 break;
 723         case CHIP_R420:
 724         case CHIP_R423:
 725         case CHIP_RV410:
 726                 rdev->asic = &r420_asic;
 727                 break;
 728         case CHIP_RS400:
 729         case CHIP_RS480:
 730                 rdev->asic = &rs400_asic;
 731                 break;
 732         case CHIP_RS600:
 733                 rdev->asic = &rs600_asic;
 734                 break;
 735         case CHIP_RS690:
 736         case CHIP_RS740:
 737                 rdev->asic = &rs690_asic;
 738                 break;
 739         case CHIP_RV515:
 740                 rdev->asic = &rv515_asic;
 741                 break;
 742         case CHIP_R520:
 743         case CHIP_RV530:
 744         case CHIP_RV560:
 745         case CHIP_RV570:
 746         case CHIP_R580:
 747                 rdev->asic = &r520_asic;
 748                 break;
 749         case CHIP_R600:
 750         case CHIP_RV610:
 751         case CHIP_RV630:
 752         case CHIP_RV620:
 753         case CHIP_RV635:
 754         case CHIP_RV670:
 755                 rdev->asic = &r600_asic;
 756                 break;
 757         case CHIP_RS780:
 758         case CHIP_RS880:
 759                 rdev->asic = &rs780_asic;
 760                 break;
 761         case CHIP_RV770:
 762         case CHIP_RV730:
 763         case CHIP_RV710:
 764         case CHIP_RV740:
 765                 rdev->asic = &rv770_asic;
 766                 break;
 767         case CHIP_CEDAR:
 768         case CHIP_REDWOOD:
 769         case CHIP_JUNIPER:
 770         case CHIP_CYPRESS:
 771         case CHIP_HEMLOCK:
 772                 rdev->asic = &evergreen_asic;
 773                 break;
 774         default:
 775                 /* FIXME: not supported yet */
 776                 return -EINVAL;
 777         }
 778
 779         if (rdev->flags & RADEON_IS_IGP) {
 780                 rdev->asic->get_memory_clock = NULL;
 781                 rdev->asic->set_memory_clock = NULL;
 782         }
 783
 784         /* set the number of crtcs */
 785         if (rdev->flags & RADEON_SINGLE_CRTC)
 786                 rdev->num_crtc = 1;
 787         else {
 788                 if (ASIC_IS_DCE4(rdev))
 789                         rdev->num_crtc = 6;
 790                 else
 791                         rdev->num_crtc = 2;
 792         }
 793
 794         return 0;
 795 }
 796
 797 /*
 798  * Wrapper around modesetting bits. Move to radeon_clocks.c?
 799  */
 800 int radeon_clocks_init(struct radeon_device *rdev)
 801 {
 802         int r;
 803
 804         r = radeon_static_clocks_init(rdev->ddev);
 805         if (r) {
 806                 return r;
 807         }
 808         DRM_INFO("Clocks initialized !\n");
 809         return 0;
 810 }
 811
 812 void radeon_clocks_fini(struct radeon_device *rdev)
 813 {
 814 }