SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .cp_commit = &r100_cp_commit,
 142         .ring_start = &r100_ring_start,
 143         .ring_test = &r100_ring_test,
 144         .ring_ib_execute = &r100_ring_ib_execute,
 145         .irq_set = &r100_irq_set,
 146         .irq_process = &r100_irq_process,
 147         .get_vblank_counter = &r100_get_vblank_counter,
 148         .fence_ring_emit = &r100_fence_ring_emit,
 149         .cs_parse = &r100_cs_parse,
 150         .copy_blit = &r100_copy_blit,
 151         .copy_dma = NULL,
 152         .copy = &r100_copy_blit,
 153         .get_engine_clock = &radeon_legacy_get_engine_clock,
 154         .set_engine_clock = &radeon_legacy_set_engine_clock,
 155         .get_memory_clock = &radeon_legacy_get_memory_clock,
 156         .set_memory_clock = NULL,
 157         .get_pcie_lanes = NULL,
 158         .set_pcie_lanes = NULL,
 159         .set_clock_gating = &radeon_legacy_set_clock_gating,
 160         .set_surface_reg = r100_set_surface_reg,
 161         .clear_surface_reg = r100_clear_surface_reg,
 162         .bandwidth_update = &r100_bandwidth_update,
 163         .hpd_init = &r100_hpd_init,
 164         .hpd_fini = &r100_hpd_fini,
 165         .hpd_sense = &r100_hpd_sense,
 166         .hpd_set_polarity = &r100_hpd_set_polarity,
 167         .ioctl_wait_idle = NULL,
 168         .gui_idle = &r100_gui_idle,
 169         .get_power_state = &r100_get_power_state,
 170         .set_power_state = &r100_set_power_state,
 171 };
 172
 173 static struct radeon_asic r200_asic = {
 174         .init = &r100_init,
 175         .fini = &r100_fini,
 176         .suspend = &r100_suspend,
 177         .resume = &r100_resume,
 178         .vga_set_state = &r100_vga_set_state,
 179         .gpu_is_lockup = &r100_gpu_is_lockup,
 180         .asic_reset = &r100_asic_reset,
 181         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 182         .gart_set_page = &r100_pci_gart_set_page,
 183         .cp_commit = &r100_cp_commit,
 184         .ring_start = &r100_ring_start,
 185         .ring_test = &r100_ring_test,
 186         .ring_ib_execute = &r100_ring_ib_execute,
 187         .irq_set = &r100_irq_set,
 188         .irq_process = &r100_irq_process,
 189         .get_vblank_counter = &r100_get_vblank_counter,
 190         .fence_ring_emit = &r100_fence_ring_emit,
 191         .cs_parse = &r100_cs_parse,
 192         .copy_blit = &r100_copy_blit,
 193         .copy_dma = &r200_copy_dma,
 194         .copy = &r100_copy_blit,
 195         .get_engine_clock = &radeon_legacy_get_engine_clock,
 196         .set_engine_clock = &radeon_legacy_set_engine_clock,
 197         .get_memory_clock = &radeon_legacy_get_memory_clock,
 198         .set_memory_clock = NULL,
 199         .set_pcie_lanes = NULL,
 200         .set_clock_gating = &radeon_legacy_set_clock_gating,
 201         .set_surface_reg = r100_set_surface_reg,
 202         .clear_surface_reg = r100_clear_surface_reg,
 203         .bandwidth_update = &r100_bandwidth_update,
 204         .hpd_init = &r100_hpd_init,
 205         .hpd_fini = &r100_hpd_fini,
 206         .hpd_sense = &r100_hpd_sense,
 207         .hpd_set_polarity = &r100_hpd_set_polarity,
 208         .ioctl_wait_idle = NULL,
 209         .gui_idle = &r100_gui_idle,
 210         .get_power_state = &r100_get_power_state,
 211         .set_power_state = &r100_set_power_state,
 212 };
 213
 214 static struct radeon_asic r300_asic = {
 215         .init = &r300_init,
 216         .fini = &r300_fini,
 217         .suspend = &r300_suspend,
 218         .resume = &r300_resume,
 219         .vga_set_state = &r100_vga_set_state,
 220         .gpu_is_lockup = &r300_gpu_is_lockup,
 221         .asic_reset = &r300_asic_reset,
 222         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 223         .gart_set_page = &r100_pci_gart_set_page,
 224         .cp_commit = &r100_cp_commit,
 225         .ring_start = &r300_ring_start,
 226         .ring_test = &r100_ring_test,
 227         .ring_ib_execute = &r100_ring_ib_execute,
 228         .irq_set = &r100_irq_set,
 229         .irq_process = &r100_irq_process,
 230         .get_vblank_counter = &r100_get_vblank_counter,
 231         .fence_ring_emit = &r300_fence_ring_emit,
 232         .cs_parse = &r300_cs_parse,
 233         .copy_blit = &r100_copy_blit,
 234         .copy_dma = &r200_copy_dma,
 235         .copy = &r100_copy_blit,
 236         .get_engine_clock = &radeon_legacy_get_engine_clock,
 237         .set_engine_clock = &radeon_legacy_set_engine_clock,
 238         .get_memory_clock = &radeon_legacy_get_memory_clock,
 239         .set_memory_clock = NULL,
 240         .get_pcie_lanes = &rv370_get_pcie_lanes,
 241         .set_pcie_lanes = &rv370_set_pcie_lanes,
 242         .set_clock_gating = &radeon_legacy_set_clock_gating,
 243         .set_surface_reg = r100_set_surface_reg,
 244         .clear_surface_reg = r100_clear_surface_reg,
 245         .bandwidth_update = &r100_bandwidth_update,
 246         .hpd_init = &r100_hpd_init,
 247         .hpd_fini = &r100_hpd_fini,
 248         .hpd_sense = &r100_hpd_sense,
 249         .hpd_set_polarity = &r100_hpd_set_polarity,
 250         .ioctl_wait_idle = NULL,
 251         .gui_idle = &r100_gui_idle,
 252         .get_power_state = &r100_get_power_state,
 253         .set_power_state = &r100_set_power_state,
 254 };
 255
 256 static struct radeon_asic r300_asic_pcie = {
 257         .init = &r300_init,
 258         .fini = &r300_fini,
 259         .suspend = &r300_suspend,
 260         .resume = &r300_resume,
 261         .vga_set_state = &r100_vga_set_state,
 262         .gpu_is_lockup = &r300_gpu_is_lockup,
 263         .asic_reset = &r300_asic_reset,
 264         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 265         .gart_set_page = &rv370_pcie_gart_set_page,
 266         .cp_commit = &r100_cp_commit,
 267         .ring_start = &r300_ring_start,
 268         .ring_test = &r100_ring_test,
 269         .ring_ib_execute = &r100_ring_ib_execute,
 270         .irq_set = &r100_irq_set,
 271         .irq_process = &r100_irq_process,
 272         .get_vblank_counter = &r100_get_vblank_counter,
 273         .fence_ring_emit = &r300_fence_ring_emit,
 274         .cs_parse = &r300_cs_parse,
 275         .copy_blit = &r100_copy_blit,
 276         .copy_dma = &r200_copy_dma,
 277         .copy = &r100_copy_blit,
 278         .get_engine_clock = &radeon_legacy_get_engine_clock,
 279         .set_engine_clock = &radeon_legacy_set_engine_clock,
 280         .get_memory_clock = &radeon_legacy_get_memory_clock,
 281         .set_memory_clock = NULL,
 282         .set_pcie_lanes = &rv370_set_pcie_lanes,
 283         .set_clock_gating = &radeon_legacy_set_clock_gating,
 284         .set_surface_reg = r100_set_surface_reg,
 285         .clear_surface_reg = r100_clear_surface_reg,
 286         .bandwidth_update = &r100_bandwidth_update,
 287         .hpd_init = &r100_hpd_init,
 288         .hpd_fini = &r100_hpd_fini,
 289         .hpd_sense = &r100_hpd_sense,
 290         .hpd_set_polarity = &r100_hpd_set_polarity,
 291         .ioctl_wait_idle = NULL,
 292         .gui_idle = &r100_gui_idle,
 293         .get_power_state = &r100_get_power_state,
 294         .set_power_state = &r100_set_power_state,
 295 };
 296
 297 static struct radeon_asic r420_asic = {
 298         .init = &r420_init,
 299         .fini = &r420_fini,
 300         .suspend = &r420_suspend,
 301         .resume = &r420_resume,
 302         .vga_set_state = &r100_vga_set_state,
 303         .gpu_is_lockup = &r300_gpu_is_lockup,
 304         .asic_reset = &r300_asic_reset,
 305         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 306         .gart_set_page = &rv370_pcie_gart_set_page,
 307         .cp_commit = &r100_cp_commit,
 308         .ring_start = &r300_ring_start,
 309         .ring_test = &r100_ring_test,
 310         .ring_ib_execute = &r100_ring_ib_execute,
 311         .irq_set = &r100_irq_set,
 312         .irq_process = &r100_irq_process,
 313         .get_vblank_counter = &r100_get_vblank_counter,
 314         .fence_ring_emit = &r300_fence_ring_emit,
 315         .cs_parse = &r300_cs_parse,
 316         .copy_blit = &r100_copy_blit,
 317         .copy_dma = &r200_copy_dma,
 318         .copy = &r100_copy_blit,
 319         .get_engine_clock = &radeon_atom_get_engine_clock,
 320         .set_engine_clock = &radeon_atom_set_engine_clock,
 321         .get_memory_clock = &radeon_atom_get_memory_clock,
 322         .set_memory_clock = &radeon_atom_set_memory_clock,
 323         .get_pcie_lanes = &rv370_get_pcie_lanes,
 324         .set_pcie_lanes = &rv370_set_pcie_lanes,
 325         .set_clock_gating = &radeon_atom_set_clock_gating,
 326         .set_surface_reg = r100_set_surface_reg,
 327         .clear_surface_reg = r100_clear_surface_reg,
 328         .bandwidth_update = &r100_bandwidth_update,
 329         .hpd_init = &r100_hpd_init,
 330         .hpd_fini = &r100_hpd_fini,
 331         .hpd_sense = &r100_hpd_sense,
 332         .hpd_set_polarity = &r100_hpd_set_polarity,
 333         .ioctl_wait_idle = NULL,
 334         .gui_idle = &r100_gui_idle,
 335         .get_power_state = &r100_get_power_state,
 336         .set_power_state = &r100_set_power_state,
 337 };
 338
 339 static struct radeon_asic rs400_asic = {
 340         .init = &rs400_init,
 341         .fini = &rs400_fini,
 342         .suspend = &rs400_suspend,
 343         .resume = &rs400_resume,
 344         .vga_set_state = &r100_vga_set_state,
 345         .gpu_is_lockup = &r300_gpu_is_lockup,
 346         .asic_reset = &r300_asic_reset,
 347         .gart_tlb_flush = &rs400_gart_tlb_flush,
 348         .gart_set_page = &rs400_gart_set_page,
 349         .cp_commit = &r100_cp_commit,
 350         .ring_start = &r300_ring_start,
 351         .ring_test = &r100_ring_test,
 352         .ring_ib_execute = &r100_ring_ib_execute,
 353         .irq_set = &r100_irq_set,
 354         .irq_process = &r100_irq_process,
 355         .get_vblank_counter = &r100_get_vblank_counter,
 356         .fence_ring_emit = &r300_fence_ring_emit,
 357         .cs_parse = &r300_cs_parse,
 358         .copy_blit = &r100_copy_blit,
 359         .copy_dma = &r200_copy_dma,
 360         .copy = &r100_copy_blit,
 361         .get_engine_clock = &radeon_legacy_get_engine_clock,
 362         .set_engine_clock = &radeon_legacy_set_engine_clock,
 363         .get_memory_clock = &radeon_legacy_get_memory_clock,
 364         .set_memory_clock = NULL,
 365         .get_pcie_lanes = NULL,
 366         .set_pcie_lanes = NULL,
 367         .set_clock_gating = &radeon_legacy_set_clock_gating,
 368         .set_surface_reg = r100_set_surface_reg,
 369         .clear_surface_reg = r100_clear_surface_reg,
 370         .bandwidth_update = &r100_bandwidth_update,
 371         .hpd_init = &r100_hpd_init,
 372         .hpd_fini = &r100_hpd_fini,
 373         .hpd_sense = &r100_hpd_sense,
 374         .hpd_set_polarity = &r100_hpd_set_polarity,
 375         .ioctl_wait_idle = NULL,
 376         .gui_idle = &r100_gui_idle,
 377         .get_power_state = &r100_get_power_state,
 378         .set_power_state = &r100_set_power_state,
 379 };
 380
 381 static struct radeon_asic rs600_asic = {
 382         .init = &rs600_init,
 383         .fini = &rs600_fini,
 384         .suspend = &rs600_suspend,
 385         .resume = &rs600_resume,
 386         .vga_set_state = &r100_vga_set_state,
 387         .gpu_is_lockup = &r300_gpu_is_lockup,
 388         .asic_reset = &rs600_asic_reset,
 389         .gart_tlb_flush = &rs600_gart_tlb_flush,
 390         .gart_set_page = &rs600_gart_set_page,
 391         .cp_commit = &r100_cp_commit,
 392         .ring_start = &r300_ring_start,
 393         .ring_test = &r100_ring_test,
 394         .ring_ib_execute = &r100_ring_ib_execute,
 395         .irq_set = &rs600_irq_set,
 396         .irq_process = &rs600_irq_process,
 397         .get_vblank_counter = &rs600_get_vblank_counter,
 398         .fence_ring_emit = &r300_fence_ring_emit,
 399         .cs_parse = &r300_cs_parse,
 400         .copy_blit = &r100_copy_blit,
 401         .copy_dma = &r200_copy_dma,
 402         .copy = &r100_copy_blit,
 403         .get_engine_clock = &radeon_atom_get_engine_clock,
 404         .set_engine_clock = &radeon_atom_set_engine_clock,
 405         .get_memory_clock = &radeon_atom_get_memory_clock,
 406         .set_memory_clock = &radeon_atom_set_memory_clock,
 407         .get_pcie_lanes = NULL,
 408         .set_pcie_lanes = NULL,
 409         .set_clock_gating = &radeon_atom_set_clock_gating,
 410         .set_surface_reg = r100_set_surface_reg,
 411         .clear_surface_reg = r100_clear_surface_reg,
 412         .bandwidth_update = &rs600_bandwidth_update,
 413         .hpd_init = &rs600_hpd_init,
 414         .hpd_fini = &rs600_hpd_fini,
 415         .hpd_sense = &rs600_hpd_sense,
 416         .hpd_set_polarity = &rs600_hpd_set_polarity,
 417         .ioctl_wait_idle = NULL,
 418         .gui_idle = &r100_gui_idle,
 419         .get_power_state = &r100_get_power_state,
 420         .set_power_state = &r100_set_power_state,
 421 };
 422
 423 static struct radeon_asic rs690_asic = {
 424         .init = &rs690_init,
 425         .fini = &rs690_fini,
 426         .suspend = &rs690_suspend,
 427         .resume = &rs690_resume,
 428         .vga_set_state = &r100_vga_set_state,
 429         .gpu_is_lockup = &r300_gpu_is_lockup,
 430         .asic_reset = &rs600_asic_reset,
 431         .gart_tlb_flush = &rs400_gart_tlb_flush,
 432         .gart_set_page = &rs400_gart_set_page,
 433         .cp_commit = &r100_cp_commit,
 434         .ring_start = &r300_ring_start,
 435         .ring_test = &r100_ring_test,
 436         .ring_ib_execute = &r100_ring_ib_execute,
 437         .irq_set = &rs600_irq_set,
 438         .irq_process = &rs600_irq_process,
 439         .get_vblank_counter = &rs600_get_vblank_counter,
 440         .fence_ring_emit = &r300_fence_ring_emit,
 441         .cs_parse = &r300_cs_parse,
 442         .copy_blit = &r100_copy_blit,
 443         .copy_dma = &r200_copy_dma,
 444         .copy = &r200_copy_dma,
 445         .get_engine_clock = &radeon_atom_get_engine_clock,
 446         .set_engine_clock = &radeon_atom_set_engine_clock,
 447         .get_memory_clock = &radeon_atom_get_memory_clock,
 448         .set_memory_clock = &radeon_atom_set_memory_clock,
 449         .get_pcie_lanes = NULL,
 450         .set_pcie_lanes = NULL,
 451         .set_clock_gating = &radeon_atom_set_clock_gating,
 452         .set_surface_reg = r100_set_surface_reg,
 453         .clear_surface_reg = r100_clear_surface_reg,
 454         .bandwidth_update = &rs690_bandwidth_update,
 455         .hpd_init = &rs600_hpd_init,
 456         .hpd_fini = &rs600_hpd_fini,
 457         .hpd_sense = &rs600_hpd_sense,
 458         .hpd_set_polarity = &rs600_hpd_set_polarity,
 459         .ioctl_wait_idle = NULL,
 460         .gui_idle = &r100_gui_idle,
 461         .get_power_state = &r100_get_power_state,
 462         .set_power_state = &r100_set_power_state,
 463 };
 464
 465 static struct radeon_asic rv515_asic = {
 466         .init = &rv515_init,
 467         .fini = &rv515_fini,
 468         .suspend = &rv515_suspend,
 469         .resume = &rv515_resume,
 470         .vga_set_state = &r100_vga_set_state,
 471         .gpu_is_lockup = &r300_gpu_is_lockup,
 472         .asic_reset = &rs600_asic_reset,
 473         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 474         .gart_set_page = &rv370_pcie_gart_set_page,
 475         .cp_commit = &r100_cp_commit,
 476         .ring_start = &rv515_ring_start,
 477         .ring_test = &r100_ring_test,
 478         .ring_ib_execute = &r100_ring_ib_execute,
 479         .irq_set = &rs600_irq_set,
 480         .irq_process = &rs600_irq_process,
 481         .get_vblank_counter = &rs600_get_vblank_counter,
 482         .fence_ring_emit = &r300_fence_ring_emit,
 483         .cs_parse = &r300_cs_parse,
 484         .copy_blit = &r100_copy_blit,
 485         .copy_dma = &r200_copy_dma,
 486         .copy = &r100_copy_blit,
 487         .get_engine_clock = &radeon_atom_get_engine_clock,
 488         .set_engine_clock = &radeon_atom_set_engine_clock,
 489         .get_memory_clock = &radeon_atom_get_memory_clock,
 490         .set_memory_clock = &radeon_atom_set_memory_clock,
 491         .get_pcie_lanes = &rv370_get_pcie_lanes,
 492         .set_pcie_lanes = &rv370_set_pcie_lanes,
 493         .set_clock_gating = &radeon_atom_set_clock_gating,
 494         .set_surface_reg = r100_set_surface_reg,
 495         .clear_surface_reg = r100_clear_surface_reg,
 496         .bandwidth_update = &rv515_bandwidth_update,
 497         .hpd_init = &rs600_hpd_init,
 498         .hpd_fini = &rs600_hpd_fini,
 499         .hpd_sense = &rs600_hpd_sense,
 500         .hpd_set_polarity = &rs600_hpd_set_polarity,
 501         .ioctl_wait_idle = NULL,
 502         .gui_idle = &r100_gui_idle,
 503         .get_power_state = &r100_get_power_state,
 504         .set_power_state = &r100_set_power_state,
 505 };
 506
 507 static struct radeon_asic r520_asic = {
 508         .init = &r520_init,
 509         .fini = &rv515_fini,
 510         .suspend = &rv515_suspend,
 511         .resume = &r520_resume,
 512         .vga_set_state = &r100_vga_set_state,
 513         .gpu_is_lockup = &r300_gpu_is_lockup,
 514         .asic_reset = &rs600_asic_reset,
 515         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 516         .gart_set_page = &rv370_pcie_gart_set_page,
 517         .cp_commit = &r100_cp_commit,
 518         .ring_start = &rv515_ring_start,
 519         .ring_test = &r100_ring_test,
 520         .ring_ib_execute = &r100_ring_ib_execute,
 521         .irq_set = &rs600_irq_set,
 522         .irq_process = &rs600_irq_process,
 523         .get_vblank_counter = &rs600_get_vblank_counter,
 524         .fence_ring_emit = &r300_fence_ring_emit,
 525         .cs_parse = &r300_cs_parse,
 526         .copy_blit = &r100_copy_blit,
 527         .copy_dma = &r200_copy_dma,
 528         .copy = &r100_copy_blit,
 529         .get_engine_clock = &radeon_atom_get_engine_clock,
 530         .set_engine_clock = &radeon_atom_set_engine_clock,
 531         .get_memory_clock = &radeon_atom_get_memory_clock,
 532         .set_memory_clock = &radeon_atom_set_memory_clock,
 533         .get_pcie_lanes = &rv370_get_pcie_lanes,
 534         .set_pcie_lanes = &rv370_set_pcie_lanes,
 535         .set_clock_gating = &radeon_atom_set_clock_gating,
 536         .set_surface_reg = r100_set_surface_reg,
 537         .clear_surface_reg = r100_clear_surface_reg,
 538         .bandwidth_update = &rv515_bandwidth_update,
 539         .hpd_init = &rs600_hpd_init,
 540         .hpd_fini = &rs600_hpd_fini,
 541         .hpd_sense = &rs600_hpd_sense,
 542         .hpd_set_polarity = &rs600_hpd_set_polarity,
 543         .ioctl_wait_idle = NULL,
 544         .gui_idle = &r100_gui_idle,
 545         .get_power_state = &r100_get_power_state,
 546         .set_power_state = &r100_set_power_state,
 547 };
 548
 549 static struct radeon_asic r600_asic = {
 550         .init = &r600_init,
 551         .fini = &r600_fini,
 552         .suspend = &r600_suspend,
 553         .resume = &r600_resume,
 554         .cp_commit = &r600_cp_commit,
 555         .vga_set_state = &r600_vga_set_state,
 556         .gpu_is_lockup = &r600_gpu_is_lockup,
 557         .asic_reset = &r600_asic_reset,
 558         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 559         .gart_set_page = &rs600_gart_set_page,
 560         .ring_test = &r600_ring_test,
 561         .ring_ib_execute = &r600_ring_ib_execute,
 562         .irq_set = &r600_irq_set,
 563         .irq_process = &r600_irq_process,
 564         .get_vblank_counter = &rs600_get_vblank_counter,
 565         .fence_ring_emit = &r600_fence_ring_emit,
 566         .cs_parse = &r600_cs_parse,
 567         .copy_blit = &r600_copy_blit,
 568         .copy_dma = &r600_copy_blit,
 569         .copy = &r600_copy_blit,
 570         .get_engine_clock = &radeon_atom_get_engine_clock,
 571         .set_engine_clock = &radeon_atom_set_engine_clock,
 572         .get_memory_clock = &radeon_atom_get_memory_clock,
 573         .set_memory_clock = &radeon_atom_set_memory_clock,
 574         .get_pcie_lanes = &rv370_get_pcie_lanes,
 575         .set_pcie_lanes = NULL,
 576         .set_clock_gating = NULL,
 577         .set_surface_reg = r600_set_surface_reg,
 578         .clear_surface_reg = r600_clear_surface_reg,
 579         .bandwidth_update = &rv515_bandwidth_update,
 580         .hpd_init = &r600_hpd_init,
 581         .hpd_fini = &r600_hpd_fini,
 582         .hpd_sense = &r600_hpd_sense,
 583         .hpd_set_polarity = &r600_hpd_set_polarity,
 584         .ioctl_wait_idle = r600_ioctl_wait_idle,
 585         .gui_idle = &r600_gui_idle,
 586         .get_power_state = &r600_get_power_state,
 587         .set_power_state = &r600_set_power_state,
 588 };
 589
 590 static struct radeon_asic rs780_asic = {
 591         .init = &r600_init,
 592         .fini = &r600_fini,
 593         .suspend = &r600_suspend,
 594         .resume = &r600_resume,
 595         .cp_commit = &r600_cp_commit,
 596         .gpu_is_lockup = &r600_gpu_is_lockup,
 597         .vga_set_state = &r600_vga_set_state,
 598         .asic_reset = &r600_asic_reset,
 599         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 600         .gart_set_page = &rs600_gart_set_page,
 601         .ring_test = &r600_ring_test,
 602         .ring_ib_execute = &r600_ring_ib_execute,
 603         .irq_set = &r600_irq_set,
 604         .irq_process = &r600_irq_process,
 605         .get_vblank_counter = &rs600_get_vblank_counter,
 606         .fence_ring_emit = &r600_fence_ring_emit,
 607         .cs_parse = &r600_cs_parse,
 608         .copy_blit = &r600_copy_blit,
 609         .copy_dma = &r600_copy_blit,
 610         .copy = &r600_copy_blit,
 611         .get_engine_clock = &radeon_atom_get_engine_clock,
 612         .set_engine_clock = &radeon_atom_set_engine_clock,
 613         .get_memory_clock = NULL,
 614         .set_memory_clock = NULL,
 615         .get_pcie_lanes = NULL,
 616         .set_pcie_lanes = NULL,
 617         .set_clock_gating = NULL,
 618         .set_surface_reg = r600_set_surface_reg,
 619         .clear_surface_reg = r600_clear_surface_reg,
 620         .bandwidth_update = &rs690_bandwidth_update,
 621         .hpd_init = &r600_hpd_init,
 622         .hpd_fini = &r600_hpd_fini,
 623         .hpd_sense = &r600_hpd_sense,
 624         .hpd_set_polarity = &r600_hpd_set_polarity,
 625         .ioctl_wait_idle = r600_ioctl_wait_idle,
 626         .gui_idle = &r600_gui_idle,
 627         .get_power_state = &r600_get_power_state,
 628         .set_power_state = &r600_set_power_state,
 629 };
 630
 631 static struct radeon_asic rv770_asic = {
 632         .init = &rv770_init,
 633         .fini = &rv770_fini,
 634         .suspend = &rv770_suspend,
 635         .resume = &rv770_resume,
 636         .cp_commit = &r600_cp_commit,
 637         .asic_reset = &r600_asic_reset,
 638         .gpu_is_lockup = &r600_gpu_is_lockup,
 639         .vga_set_state = &r600_vga_set_state,
 640         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 641         .gart_set_page = &rs600_gart_set_page,
 642         .ring_test = &r600_ring_test,
 643         .ring_ib_execute = &r600_ring_ib_execute,
 644         .irq_set = &r600_irq_set,
 645         .irq_process = &r600_irq_process,
 646         .get_vblank_counter = &rs600_get_vblank_counter,
 647         .fence_ring_emit = &r600_fence_ring_emit,
 648         .cs_parse = &r600_cs_parse,
 649         .copy_blit = &r600_copy_blit,
 650         .copy_dma = &r600_copy_blit,
 651         .copy = &r600_copy_blit,
 652         .get_engine_clock = &radeon_atom_get_engine_clock,
 653         .set_engine_clock = &radeon_atom_set_engine_clock,
 654         .get_memory_clock = &radeon_atom_get_memory_clock,
 655         .set_memory_clock = &radeon_atom_set_memory_clock,
 656         .get_pcie_lanes = &rv370_get_pcie_lanes,
 657         .set_pcie_lanes = NULL,
 658         .set_clock_gating = &radeon_atom_set_clock_gating,
 659         .set_surface_reg = r600_set_surface_reg,
 660         .clear_surface_reg = r600_clear_surface_reg,
 661         .bandwidth_update = &rv515_bandwidth_update,
 662         .hpd_init = &r600_hpd_init,
 663         .hpd_fini = &r600_hpd_fini,
 664         .hpd_sense = &r600_hpd_sense,
 665         .hpd_set_polarity = &r600_hpd_set_polarity,
 666         .ioctl_wait_idle = r600_ioctl_wait_idle,
 667         .gui_idle = &r600_gui_idle,
 668         .get_power_state = &r600_get_power_state,
 669         .set_power_state = &r600_set_power_state,
 670 };
 671
 672 static struct radeon_asic evergreen_asic = {
 673         .init = &evergreen_init,
 674         .fini = &evergreen_fini,
 675         .suspend = &evergreen_suspend,
 676         .resume = &evergreen_resume,
 677         .cp_commit = &r600_cp_commit,
 678         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 679         .asic_reset = &evergreen_asic_reset,
 680         .vga_set_state = &r600_vga_set_state,
 681         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 682         .gart_set_page = &rs600_gart_set_page,
 683         .ring_test = &r600_ring_test,
 684         .ring_ib_execute = &r600_ring_ib_execute,
 685         .irq_set = &evergreen_irq_set,
 686         .irq_process = &evergreen_irq_process,
 687         .get_vblank_counter = &evergreen_get_vblank_counter,
 688         .fence_ring_emit = NULL,
 689         .cs_parse = NULL,
 690         .copy_blit = NULL,
 691         .copy_dma = NULL,
 692         .copy = NULL,
 693         .get_engine_clock = &radeon_atom_get_engine_clock,
 694         .set_engine_clock = &radeon_atom_set_engine_clock,
 695         .get_memory_clock = &radeon_atom_get_memory_clock,
 696         .set_memory_clock = &radeon_atom_set_memory_clock,
 697         .set_pcie_lanes = NULL,
 698         .set_clock_gating = NULL,
 699         .set_surface_reg = r600_set_surface_reg,
 700         .clear_surface_reg = r600_clear_surface_reg,
 701         .bandwidth_update = &evergreen_bandwidth_update,
 702         .hpd_init = &evergreen_hpd_init,
 703         .hpd_fini = &evergreen_hpd_fini,
 704         .hpd_sense = &evergreen_hpd_sense,
 705         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 706         .gui_idle = &r600_gui_idle,
 707         .get_power_state = &r600_get_power_state,
 708         .set_power_state = &r600_set_power_state,
 709 };
 710
 711 int radeon_asic_init(struct radeon_device *rdev)
 712 {
 713         radeon_register_accessor_init(rdev);
 714         switch (rdev->family) {
 715         case CHIP_R100:
 716         case CHIP_RV100:
 717         case CHIP_RS100:
 718         case CHIP_RV200:
 719         case CHIP_RS200:
 720                 rdev->asic = &r100_asic;
 721                 break;
 722         case CHIP_R200:
 723         case CHIP_RV250:
 724         case CHIP_RS300:
 725         case CHIP_RV280:
 726                 rdev->asic = &r200_asic;
 727                 break;
 728         case CHIP_R300:
 729         case CHIP_R350:
 730         case CHIP_RV350:
 731         case CHIP_RV380:
 732                 if (rdev->flags & RADEON_IS_PCIE)
 733                         rdev->asic = &r300_asic_pcie;
 734                 else
 735                         rdev->asic = &r300_asic;
 736                 break;
 737         case CHIP_R420:
 738         case CHIP_R423:
 739         case CHIP_RV410:
 740                 rdev->asic = &r420_asic;
 741                 break;
 742         case CHIP_RS400:
 743         case CHIP_RS480:
 744                 rdev->asic = &rs400_asic;
 745                 break;
 746         case CHIP_RS600:
 747                 rdev->asic = &rs600_asic;
 748                 break;
 749         case CHIP_RS690:
 750         case CHIP_RS740:
 751                 rdev->asic = &rs690_asic;
 752                 break;
 753         case CHIP_RV515:
 754                 rdev->asic = &rv515_asic;
 755                 break;
 756         case CHIP_R520:
 757         case CHIP_RV530:
 758         case CHIP_RV560:
 759         case CHIP_RV570:
 760         case CHIP_R580:
 761                 rdev->asic = &r520_asic;
 762                 break;
 763         case CHIP_R600:
 764         case CHIP_RV610:
 765         case CHIP_RV630:
 766         case CHIP_RV620:
 767         case CHIP_RV635:
 768         case CHIP_RV670:
 769                 rdev->asic = &r600_asic;
 770                 break;
 771         case CHIP_RS780:
 772         case CHIP_RS880:
 773                 rdev->asic = &rs780_asic;
 774                 break;
 775         case CHIP_RV770:
 776         case CHIP_RV730:
 777         case CHIP_RV710:
 778         case CHIP_RV740:
 779                 rdev->asic = &rv770_asic;
 780                 break;
 781         case CHIP_CEDAR:
 782         case CHIP_REDWOOD:
 783         case CHIP_JUNIPER:
 784         case CHIP_CYPRESS:
 785         case CHIP_HEMLOCK:
 786                 rdev->asic = &evergreen_asic;
 787                 break;
 788         default:
 789                 /* FIXME: not supported yet */
 790                 return -EINVAL;
 791         }
 792
 793         if (rdev->flags & RADEON_IS_IGP) {
 794                 rdev->asic->get_memory_clock = NULL;
 795                 rdev->asic->set_memory_clock = NULL;
 796         }
 797
 798         /* set the number of crtcs */
 799         if (rdev->flags & RADEON_SINGLE_CRTC)
 800                 rdev->num_crtc = 1;
 801         else {
 802                 if (ASIC_IS_DCE4(rdev))
 803                         rdev->num_crtc = 6;
 804                 else
 805                         rdev->num_crtc = 2;
 806         }
 807
 808         return 0;
 809 }
 810
 811 /*
 812  * Wrapper around modesetting bits. Move to radeon_clocks.c?
 813  */
 814 int radeon_clocks_init(struct radeon_device *rdev)
 815 {
 816         int r;
 817
 818         r = radeon_static_clocks_init(rdev->ddev);
 819         if (r) {
 820                 return r;
 821         }
 822         DRM_INFO("Clocks initialized !\n");
 823         return 0;
 824 }
 825
 826 void radeon_clocks_fini(struct radeon_device *rdev)
 827 {
 828 }