2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_asic.h"
35 #include "radeon_mode.h"
40 #define PFP_UCODE_SIZE 576
41 #define PM4_UCODE_SIZE 1792
42 #define RLC_UCODE_SIZE 768
43 #define R700_PFP_UCODE_SIZE 848
44 #define R700_PM4_UCODE_SIZE 1360
45 #define R700_RLC_UCODE_SIZE 1024
48 MODULE_FIRMWARE("radeon/R600_pfp.bin");
49 MODULE_FIRMWARE("radeon/R600_me.bin");
50 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
51 MODULE_FIRMWARE("radeon/RV610_me.bin");
52 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
53 MODULE_FIRMWARE("radeon/RV630_me.bin");
54 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV620_me.bin");
56 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV635_me.bin");
58 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV670_me.bin");
60 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
61 MODULE_FIRMWARE("radeon/RS780_me.bin");
62 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV770_me.bin");
64 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
65 MODULE_FIRMWARE("radeon/RV730_me.bin");
66 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV710_me.bin");
68 MODULE_FIRMWARE("radeon/R600_rlc.bin");
69 MODULE_FIRMWARE("radeon/R700_rlc.bin");
71 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
73 /* r600,rv610,rv630,rv620,rv635,rv670 */
74 int r600_mc_wait_for_idle(struct radeon_device *rdev);
75 void r600_gpu_init(struct radeon_device *rdev);
76 void r600_fini(struct radeon_device *rdev);
78 /* hpd for digital panel detect/disconnect */
79 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
81 bool connected = false;
83 if (ASIC_IS_DCE3(rdev)) {
86 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
90 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
94 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
98 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
103 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
107 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
116 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
120 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
124 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
134 void r600_hpd_set_polarity(struct radeon_device *rdev,
135 enum radeon_hpd_id hpd)
138 bool connected = r600_hpd_sense(rdev, hpd);
140 if (ASIC_IS_DCE3(rdev)) {
143 tmp = RREG32(DC_HPD1_INT_CONTROL);
145 tmp &= ~DC_HPDx_INT_POLARITY;
147 tmp |= DC_HPDx_INT_POLARITY;
148 WREG32(DC_HPD1_INT_CONTROL, tmp);
151 tmp = RREG32(DC_HPD2_INT_CONTROL);
153 tmp &= ~DC_HPDx_INT_POLARITY;
155 tmp |= DC_HPDx_INT_POLARITY;
156 WREG32(DC_HPD2_INT_CONTROL, tmp);
159 tmp = RREG32(DC_HPD3_INT_CONTROL);
161 tmp &= ~DC_HPDx_INT_POLARITY;
163 tmp |= DC_HPDx_INT_POLARITY;
164 WREG32(DC_HPD3_INT_CONTROL, tmp);
167 tmp = RREG32(DC_HPD4_INT_CONTROL);
169 tmp &= ~DC_HPDx_INT_POLARITY;
171 tmp |= DC_HPDx_INT_POLARITY;
172 WREG32(DC_HPD4_INT_CONTROL, tmp);
175 tmp = RREG32(DC_HPD5_INT_CONTROL);
177 tmp &= ~DC_HPDx_INT_POLARITY;
179 tmp |= DC_HPDx_INT_POLARITY;
180 WREG32(DC_HPD5_INT_CONTROL, tmp);
184 tmp = RREG32(DC_HPD6_INT_CONTROL);
186 tmp &= ~DC_HPDx_INT_POLARITY;
188 tmp |= DC_HPDx_INT_POLARITY;
189 WREG32(DC_HPD6_INT_CONTROL, tmp);
197 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
199 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
202 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
205 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
207 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
210 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
213 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
215 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
218 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
226 void r600_hpd_init(struct radeon_device *rdev)
228 struct drm_device *dev = rdev->ddev;
229 struct drm_connector *connector;
231 if (ASIC_IS_DCE3(rdev)) {
232 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
233 if (ASIC_IS_DCE32(rdev))
236 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
237 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
238 switch (radeon_connector->hpd.hpd) {
240 WREG32(DC_HPD1_CONTROL, tmp);
241 rdev->irq.hpd[0] = true;
244 WREG32(DC_HPD2_CONTROL, tmp);
245 rdev->irq.hpd[1] = true;
248 WREG32(DC_HPD3_CONTROL, tmp);
249 rdev->irq.hpd[2] = true;
252 WREG32(DC_HPD4_CONTROL, tmp);
253 rdev->irq.hpd[3] = true;
257 WREG32(DC_HPD5_CONTROL, tmp);
258 rdev->irq.hpd[4] = true;
261 WREG32(DC_HPD6_CONTROL, tmp);
262 rdev->irq.hpd[5] = true;
269 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
270 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
271 switch (radeon_connector->hpd.hpd) {
273 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
274 rdev->irq.hpd[0] = true;
277 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
278 rdev->irq.hpd[1] = true;
281 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
282 rdev->irq.hpd[2] = true;
289 if (rdev->irq.installed)
293 void r600_hpd_fini(struct radeon_device *rdev)
295 struct drm_device *dev = rdev->ddev;
296 struct drm_connector *connector;
298 if (ASIC_IS_DCE3(rdev)) {
299 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
300 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
301 switch (radeon_connector->hpd.hpd) {
303 WREG32(DC_HPD1_CONTROL, 0);
304 rdev->irq.hpd[0] = false;
307 WREG32(DC_HPD2_CONTROL, 0);
308 rdev->irq.hpd[1] = false;
311 WREG32(DC_HPD3_CONTROL, 0);
312 rdev->irq.hpd[2] = false;
315 WREG32(DC_HPD4_CONTROL, 0);
316 rdev->irq.hpd[3] = false;
320 WREG32(DC_HPD5_CONTROL, 0);
321 rdev->irq.hpd[4] = false;
324 WREG32(DC_HPD6_CONTROL, 0);
325 rdev->irq.hpd[5] = false;
332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
333 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
334 switch (radeon_connector->hpd.hpd) {
336 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
337 rdev->irq.hpd[0] = false;
340 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
341 rdev->irq.hpd[1] = false;
344 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
345 rdev->irq.hpd[2] = false;
357 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
362 /* flush hdp cache so updates hit vram */
363 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
365 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
366 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
367 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
368 for (i = 0; i < rdev->usec_timeout; i++) {
370 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
371 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
373 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
383 int r600_pcie_gart_init(struct radeon_device *rdev)
387 if (rdev->gart.table.vram.robj) {
388 WARN(1, "R600 PCIE GART already initialized.\n");
391 /* Initialize common gart structure */
392 r = radeon_gart_init(rdev);
395 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
396 return radeon_gart_table_vram_alloc(rdev);
399 int r600_pcie_gart_enable(struct radeon_device *rdev)
404 if (rdev->gart.table.vram.robj == NULL) {
405 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
408 r = radeon_gart_table_vram_pin(rdev);
411 radeon_gart_restore(rdev);
414 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
415 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
416 EFFECTIVE_L2_QUEUE_SIZE(7));
417 WREG32(VM_L2_CNTL2, 0);
418 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
419 /* Setup TLB control */
420 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
421 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
422 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
423 ENABLE_WAIT_L2_QUERY;
424 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
425 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
426 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
427 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
428 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
429 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
430 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
431 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
434 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
436 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
437 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
438 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
439 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
440 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
441 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
442 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
443 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
444 (u32)(rdev->dummy_page.addr >> 12));
445 for (i = 1; i < 7; i++)
446 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
448 r600_pcie_gart_tlb_flush(rdev);
449 rdev->gart.ready = true;
453 void r600_pcie_gart_disable(struct radeon_device *rdev)
458 /* Disable all tables */
459 for (i = 0; i < 7; i++)
460 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
462 /* Disable L2 cache */
463 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
464 EFFECTIVE_L2_QUEUE_SIZE(7));
465 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
466 /* Setup L1 TLB control */
467 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
468 ENABLE_WAIT_L2_QUERY;
469 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
470 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
471 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
472 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
473 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
474 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
475 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
476 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
482 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
483 if (rdev->gart.table.vram.robj) {
484 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
485 if (likely(r == 0)) {
486 radeon_bo_kunmap(rdev->gart.table.vram.robj);
487 radeon_bo_unpin(rdev->gart.table.vram.robj);
488 radeon_bo_unreserve(rdev->gart.table.vram.robj);
493 void r600_pcie_gart_fini(struct radeon_device *rdev)
495 r600_pcie_gart_disable(rdev);
496 radeon_gart_table_vram_free(rdev);
497 radeon_gart_fini(rdev);
500 void r600_agp_enable(struct radeon_device *rdev)
506 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
507 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
508 EFFECTIVE_L2_QUEUE_SIZE(7));
509 WREG32(VM_L2_CNTL2, 0);
510 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
511 /* Setup TLB control */
512 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
513 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
514 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
515 ENABLE_WAIT_L2_QUERY;
516 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
517 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
518 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
519 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
520 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
521 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
522 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
523 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
526 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
528 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
529 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
530 for (i = 0; i < 7; i++)
531 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
534 int r600_mc_wait_for_idle(struct radeon_device *rdev)
539 for (i = 0; i < rdev->usec_timeout; i++) {
541 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
549 static void r600_mc_program(struct radeon_device *rdev)
551 struct rv515_mc_save save;
556 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
557 WREG32((0x2c14 + j), 0x00000000);
558 WREG32((0x2c18 + j), 0x00000000);
559 WREG32((0x2c1c + j), 0x00000000);
560 WREG32((0x2c20 + j), 0x00000000);
561 WREG32((0x2c24 + j), 0x00000000);
563 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
565 rv515_mc_stop(rdev, &save);
566 if (r600_mc_wait_for_idle(rdev)) {
567 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
569 /* Lockout access through VGA aperture (doesn't exist before R600) */
570 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
571 /* Update configuration */
572 if (rdev->flags & RADEON_IS_AGP) {
573 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
574 /* VRAM before AGP */
575 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
576 rdev->mc.vram_start >> 12);
577 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
578 rdev->mc.gtt_end >> 12);
581 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
582 rdev->mc.gtt_start >> 12);
583 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
584 rdev->mc.vram_end >> 12);
587 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
588 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
590 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
591 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
592 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
593 WREG32(MC_VM_FB_LOCATION, tmp);
594 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
595 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
596 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
597 if (rdev->flags & RADEON_IS_AGP) {
598 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
599 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
600 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
602 WREG32(MC_VM_AGP_BASE, 0);
603 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
604 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
606 if (r600_mc_wait_for_idle(rdev)) {
607 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
609 rv515_mc_resume(rdev, &save);
610 /* we need to own VRAM, so turn off the VGA renderer here
611 * to stop it overwriting our objects */
612 rv515_vga_render_disable(rdev);
616 * r600_vram_gtt_location - try to find VRAM & GTT location
617 * @rdev: radeon device structure holding all necessary informations
618 * @mc: memory controller structure holding memory informations
620 * Function will place try to place VRAM at same place as in CPU (PCI)
621 * address space as some GPU seems to have issue when we reprogram at
622 * different address space.
624 * If there is not enough space to fit the unvisible VRAM after the
625 * aperture then we limit the VRAM size to the aperture.
627 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
628 * them to be in one from GPU point of view so that we can program GPU to
629 * catch access outside them (weird GPU policy see ??).
631 * This function will never fails, worst case are limiting VRAM or GTT.
633 * Note: GTT start, end, size should be initialized before calling this
634 * function on AGP platform.
636 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
638 u64 size_bf, size_af;
640 if (mc->mc_vram_size > 0xE0000000) {
641 /* leave room for at least 512M GTT */
642 dev_warn(rdev->dev, "limiting VRAM\n");
643 mc->real_vram_size = 0xE0000000;
644 mc->mc_vram_size = 0xE0000000;
646 if (rdev->flags & RADEON_IS_AGP) {
647 size_bf = mc->gtt_start;
648 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
649 if (size_bf > size_af) {
650 if (mc->mc_vram_size > size_bf) {
651 dev_warn(rdev->dev, "limiting VRAM\n");
652 mc->real_vram_size = size_bf;
653 mc->mc_vram_size = size_bf;
655 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
657 if (mc->mc_vram_size > size_af) {
658 dev_warn(rdev->dev, "limiting VRAM\n");
659 mc->real_vram_size = size_af;
660 mc->mc_vram_size = size_af;
662 mc->vram_start = mc->gtt_end;
664 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
665 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
666 mc->mc_vram_size >> 20, mc->vram_start,
667 mc->vram_end, mc->real_vram_size >> 20);
670 if (rdev->flags & RADEON_IS_IGP)
671 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
672 radeon_vram_location(rdev, &rdev->mc, base);
673 radeon_gtt_location(rdev, mc);
677 int r600_mc_init(struct radeon_device *rdev)
681 int chansize, numchan;
683 /* Get VRAM informations */
684 rdev->mc.vram_is_ddr = true;
685 tmp = RREG32(RAMCFG);
686 if (tmp & CHANSIZE_OVERRIDE) {
688 } else if (tmp & CHANSIZE_MASK) {
694 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
709 rdev->mc.vram_width = numchan * chansize;
710 /* Could aper size report 0 ? */
711 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
712 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
713 /* Setup GPU memory space */
714 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
715 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
716 rdev->mc.visible_vram_size = rdev->mc.aper_size;
717 /* FIXME remove this once we support unmappable VRAM */
718 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
719 rdev->mc.mc_vram_size = rdev->mc.aper_size;
720 rdev->mc.real_vram_size = rdev->mc.aper_size;
722 r600_vram_gtt_location(rdev, &rdev->mc);
723 /* FIXME: we should enforce default clock in case GPU is not in
726 a.full = rfixed_const(100);
727 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
728 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
729 if (rdev->flags & RADEON_IS_IGP)
730 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
734 /* We doesn't check that the GPU really needs a reset we simply do the
735 * reset, it's up to the caller to determine if the GPU needs one. We
736 * might add an helper function to check that.
738 int r600_gpu_soft_reset(struct radeon_device *rdev)
740 struct rv515_mc_save save;
741 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
742 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
743 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
744 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
745 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
746 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
747 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
748 S_008010_GUI_ACTIVE(1);
749 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
750 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
751 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
752 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
753 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
754 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
755 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
756 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
760 dev_info(rdev->dev, "GPU softreset \n");
761 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
762 RREG32(R_008010_GRBM_STATUS));
763 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
764 RREG32(R_008014_GRBM_STATUS2));
765 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
766 RREG32(R_000E50_SRBM_STATUS));
767 rv515_mc_stop(rdev, &save);
768 if (r600_mc_wait_for_idle(rdev)) {
769 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
771 /* Disable CP parsing/prefetching */
772 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
773 /* Check if any of the rendering block is busy and reset it */
774 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
775 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
776 tmp = S_008020_SOFT_RESET_CR(1) |
777 S_008020_SOFT_RESET_DB(1) |
778 S_008020_SOFT_RESET_CB(1) |
779 S_008020_SOFT_RESET_PA(1) |
780 S_008020_SOFT_RESET_SC(1) |
781 S_008020_SOFT_RESET_SMX(1) |
782 S_008020_SOFT_RESET_SPI(1) |
783 S_008020_SOFT_RESET_SX(1) |
784 S_008020_SOFT_RESET_SH(1) |
785 S_008020_SOFT_RESET_TC(1) |
786 S_008020_SOFT_RESET_TA(1) |
787 S_008020_SOFT_RESET_VC(1) |
788 S_008020_SOFT_RESET_VGT(1);
789 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
790 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
791 (void)RREG32(R_008020_GRBM_SOFT_RESET);
793 WREG32(R_008020_GRBM_SOFT_RESET, 0);
794 (void)RREG32(R_008020_GRBM_SOFT_RESET);
796 /* Reset CP (we always reset CP) */
797 tmp = S_008020_SOFT_RESET_CP(1);
798 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
799 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
800 (void)RREG32(R_008020_GRBM_SOFT_RESET);
802 WREG32(R_008020_GRBM_SOFT_RESET, 0);
803 (void)RREG32(R_008020_GRBM_SOFT_RESET);
804 /* Reset others GPU block if necessary */
805 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
806 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
807 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
808 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
809 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
810 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
811 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
812 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
813 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
814 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
815 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
816 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
817 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
818 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
819 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
820 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
821 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
822 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
823 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
824 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
825 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
826 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
827 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
828 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
829 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
830 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
831 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
833 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
835 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
836 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
838 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
839 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
840 /* Wait a little for things to settle down */
842 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
843 RREG32(R_008010_GRBM_STATUS));
844 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
845 RREG32(R_008014_GRBM_STATUS2));
846 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
847 RREG32(R_000E50_SRBM_STATUS));
848 /* After reset we need to reinit the asic as GPU often endup in an
851 atom_asic_init(rdev->mode_info.atom_context);
852 rv515_mc_resume(rdev, &save);
856 int r600_gpu_reset(struct radeon_device *rdev)
858 return r600_gpu_soft_reset(rdev);
861 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
863 u32 backend_disable_mask)
866 u32 enabled_backends_mask;
867 u32 enabled_backends_count;
869 u32 swizzle_pipe[R6XX_MAX_PIPES];
873 if (num_tile_pipes > R6XX_MAX_PIPES)
874 num_tile_pipes = R6XX_MAX_PIPES;
875 if (num_tile_pipes < 1)
877 if (num_backends > R6XX_MAX_BACKENDS)
878 num_backends = R6XX_MAX_BACKENDS;
879 if (num_backends < 1)
882 enabled_backends_mask = 0;
883 enabled_backends_count = 0;
884 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
885 if (((backend_disable_mask >> i) & 1) == 0) {
886 enabled_backends_mask |= (1 << i);
887 ++enabled_backends_count;
889 if (enabled_backends_count == num_backends)
893 if (enabled_backends_count == 0) {
894 enabled_backends_mask = 1;
895 enabled_backends_count = 1;
898 if (enabled_backends_count != num_backends)
899 num_backends = enabled_backends_count;
901 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
902 switch (num_tile_pipes) {
958 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
959 while (((1 << cur_backend) & enabled_backends_mask) == 0)
960 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
962 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
964 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
970 int r600_count_pipe_bits(uint32_t val)
974 for (i = 0; i < 32; i++) {
981 void r600_gpu_init(struct radeon_device *rdev)
986 u32 cc_rb_backend_disable;
987 u32 cc_gc_shader_pipe_config;
991 u32 sq_gpr_resource_mgmt_1 = 0;
992 u32 sq_gpr_resource_mgmt_2 = 0;
993 u32 sq_thread_resource_mgmt = 0;
994 u32 sq_stack_resource_mgmt_1 = 0;
995 u32 sq_stack_resource_mgmt_2 = 0;
997 /* FIXME: implement */
998 switch (rdev->family) {
1000 rdev->config.r600.max_pipes = 4;
1001 rdev->config.r600.max_tile_pipes = 8;
1002 rdev->config.r600.max_simds = 4;
1003 rdev->config.r600.max_backends = 4;
1004 rdev->config.r600.max_gprs = 256;
1005 rdev->config.r600.max_threads = 192;
1006 rdev->config.r600.max_stack_entries = 256;
1007 rdev->config.r600.max_hw_contexts = 8;
1008 rdev->config.r600.max_gs_threads = 16;
1009 rdev->config.r600.sx_max_export_size = 128;
1010 rdev->config.r600.sx_max_export_pos_size = 16;
1011 rdev->config.r600.sx_max_export_smx_size = 128;
1012 rdev->config.r600.sq_num_cf_insts = 2;
1016 rdev->config.r600.max_pipes = 2;
1017 rdev->config.r600.max_tile_pipes = 2;
1018 rdev->config.r600.max_simds = 3;
1019 rdev->config.r600.max_backends = 1;
1020 rdev->config.r600.max_gprs = 128;
1021 rdev->config.r600.max_threads = 192;
1022 rdev->config.r600.max_stack_entries = 128;
1023 rdev->config.r600.max_hw_contexts = 8;
1024 rdev->config.r600.max_gs_threads = 4;
1025 rdev->config.r600.sx_max_export_size = 128;
1026 rdev->config.r600.sx_max_export_pos_size = 16;
1027 rdev->config.r600.sx_max_export_smx_size = 128;
1028 rdev->config.r600.sq_num_cf_insts = 2;
1034 rdev->config.r600.max_pipes = 1;
1035 rdev->config.r600.max_tile_pipes = 1;
1036 rdev->config.r600.max_simds = 2;
1037 rdev->config.r600.max_backends = 1;
1038 rdev->config.r600.max_gprs = 128;
1039 rdev->config.r600.max_threads = 192;
1040 rdev->config.r600.max_stack_entries = 128;
1041 rdev->config.r600.max_hw_contexts = 4;
1042 rdev->config.r600.max_gs_threads = 4;
1043 rdev->config.r600.sx_max_export_size = 128;
1044 rdev->config.r600.sx_max_export_pos_size = 16;
1045 rdev->config.r600.sx_max_export_smx_size = 128;
1046 rdev->config.r600.sq_num_cf_insts = 1;
1049 rdev->config.r600.max_pipes = 4;
1050 rdev->config.r600.max_tile_pipes = 4;
1051 rdev->config.r600.max_simds = 4;
1052 rdev->config.r600.max_backends = 4;
1053 rdev->config.r600.max_gprs = 192;
1054 rdev->config.r600.max_threads = 192;
1055 rdev->config.r600.max_stack_entries = 256;
1056 rdev->config.r600.max_hw_contexts = 8;
1057 rdev->config.r600.max_gs_threads = 16;
1058 rdev->config.r600.sx_max_export_size = 128;
1059 rdev->config.r600.sx_max_export_pos_size = 16;
1060 rdev->config.r600.sx_max_export_smx_size = 128;
1061 rdev->config.r600.sq_num_cf_insts = 2;
1067 /* Initialize HDP */
1068 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1069 WREG32((0x2c14 + j), 0x00000000);
1070 WREG32((0x2c18 + j), 0x00000000);
1071 WREG32((0x2c1c + j), 0x00000000);
1072 WREG32((0x2c20 + j), 0x00000000);
1073 WREG32((0x2c24 + j), 0x00000000);
1076 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1080 ramcfg = RREG32(RAMCFG);
1081 switch (rdev->config.r600.max_tile_pipes) {
1083 tiling_config |= PIPE_TILING(0);
1086 tiling_config |= PIPE_TILING(1);
1089 tiling_config |= PIPE_TILING(2);
1092 tiling_config |= PIPE_TILING(3);
1097 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1098 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1099 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1100 tiling_config |= GROUP_SIZE(0);
1101 rdev->config.r600.tiling_group_size = 256;
1102 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1104 tiling_config |= ROW_TILING(3);
1105 tiling_config |= SAMPLE_SPLIT(3);
1107 tiling_config |= ROW_TILING(tmp);
1108 tiling_config |= SAMPLE_SPLIT(tmp);
1110 tiling_config |= BANK_SWAPS(1);
1112 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1113 cc_rb_backend_disable |=
1114 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1116 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1117 cc_gc_shader_pipe_config |=
1118 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1119 cc_gc_shader_pipe_config |=
1120 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1122 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1123 (R6XX_MAX_BACKENDS -
1124 r600_count_pipe_bits((cc_rb_backend_disable &
1125 R6XX_MAX_BACKENDS_MASK) >> 16)),
1126 (cc_rb_backend_disable >> 16));
1128 tiling_config |= BACKEND_MAP(backend_map);
1129 WREG32(GB_TILING_CONFIG, tiling_config);
1130 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1131 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1134 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1135 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1136 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1138 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1139 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1140 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1142 /* Setup some CP states */
1143 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1144 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1146 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1147 SYNC_WALKER | SYNC_ALIGNER));
1148 /* Setup various GPU states */
1149 if (rdev->family == CHIP_RV670)
1150 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1152 tmp = RREG32(SX_DEBUG_1);
1153 tmp |= SMX_EVENT_RELEASE;
1154 if ((rdev->family > CHIP_R600))
1155 tmp |= ENABLE_NEW_SMX_ADDRESS;
1156 WREG32(SX_DEBUG_1, tmp);
1158 if (((rdev->family) == CHIP_R600) ||
1159 ((rdev->family) == CHIP_RV630) ||
1160 ((rdev->family) == CHIP_RV610) ||
1161 ((rdev->family) == CHIP_RV620) ||
1162 ((rdev->family) == CHIP_RS780) ||
1163 ((rdev->family) == CHIP_RS880)) {
1164 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1166 WREG32(DB_DEBUG, 0);
1168 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1169 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1171 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1172 WREG32(VGT_NUM_INSTANCES, 0);
1174 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1175 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1177 tmp = RREG32(SQ_MS_FIFO_SIZES);
1178 if (((rdev->family) == CHIP_RV610) ||
1179 ((rdev->family) == CHIP_RV620) ||
1180 ((rdev->family) == CHIP_RS780) ||
1181 ((rdev->family) == CHIP_RS880)) {
1182 tmp = (CACHE_FIFO_SIZE(0xa) |
1183 FETCH_FIFO_HIWATER(0xa) |
1184 DONE_FIFO_HIWATER(0xe0) |
1185 ALU_UPDATE_FIFO_HIWATER(0x8));
1186 } else if (((rdev->family) == CHIP_R600) ||
1187 ((rdev->family) == CHIP_RV630)) {
1188 tmp &= ~DONE_FIFO_HIWATER(0xff);
1189 tmp |= DONE_FIFO_HIWATER(0x4);
1191 WREG32(SQ_MS_FIFO_SIZES, tmp);
1193 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1194 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1196 sq_config = RREG32(SQ_CONFIG);
1197 sq_config &= ~(PS_PRIO(3) |
1201 sq_config |= (DX9_CONSTS |
1208 if ((rdev->family) == CHIP_R600) {
1209 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1211 NUM_CLAUSE_TEMP_GPRS(4));
1212 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1214 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1215 NUM_VS_THREADS(48) |
1218 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1219 NUM_VS_STACK_ENTRIES(128));
1220 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1221 NUM_ES_STACK_ENTRIES(0));
1222 } else if (((rdev->family) == CHIP_RV610) ||
1223 ((rdev->family) == CHIP_RV620) ||
1224 ((rdev->family) == CHIP_RS780) ||
1225 ((rdev->family) == CHIP_RS880)) {
1226 /* no vertex cache */
1227 sq_config &= ~VC_ENABLE;
1229 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1231 NUM_CLAUSE_TEMP_GPRS(2));
1232 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1234 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1235 NUM_VS_THREADS(78) |
1237 NUM_ES_THREADS(31));
1238 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1239 NUM_VS_STACK_ENTRIES(40));
1240 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1241 NUM_ES_STACK_ENTRIES(16));
1242 } else if (((rdev->family) == CHIP_RV630) ||
1243 ((rdev->family) == CHIP_RV635)) {
1244 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1246 NUM_CLAUSE_TEMP_GPRS(2));
1247 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1249 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1250 NUM_VS_THREADS(78) |
1252 NUM_ES_THREADS(31));
1253 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1254 NUM_VS_STACK_ENTRIES(40));
1255 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1256 NUM_ES_STACK_ENTRIES(16));
1257 } else if ((rdev->family) == CHIP_RV670) {
1258 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1260 NUM_CLAUSE_TEMP_GPRS(2));
1261 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1263 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1264 NUM_VS_THREADS(78) |
1266 NUM_ES_THREADS(31));
1267 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1268 NUM_VS_STACK_ENTRIES(64));
1269 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1270 NUM_ES_STACK_ENTRIES(64));
1273 WREG32(SQ_CONFIG, sq_config);
1274 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1275 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1276 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1277 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1278 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1280 if (((rdev->family) == CHIP_RV610) ||
1281 ((rdev->family) == CHIP_RV620) ||
1282 ((rdev->family) == CHIP_RS780) ||
1283 ((rdev->family) == CHIP_RS880)) {
1284 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1286 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1289 /* More default values. 2D/3D driver should adjust as needed */
1290 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1291 S1_X(0x4) | S1_Y(0xc)));
1292 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1293 S1_X(0x2) | S1_Y(0x2) |
1294 S2_X(0xa) | S2_Y(0x6) |
1295 S3_X(0x6) | S3_Y(0xa)));
1296 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1297 S1_X(0x4) | S1_Y(0xc) |
1298 S2_X(0x1) | S2_Y(0x6) |
1299 S3_X(0xa) | S3_Y(0xe)));
1300 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1301 S5_X(0x0) | S5_Y(0x0) |
1302 S6_X(0xb) | S6_Y(0x4) |
1303 S7_X(0x7) | S7_Y(0x8)));
1305 WREG32(VGT_STRMOUT_EN, 0);
1306 tmp = rdev->config.r600.max_pipes * 16;
1307 switch (rdev->family) {
1323 WREG32(VGT_ES_PER_GS, 128);
1324 WREG32(VGT_GS_PER_ES, tmp);
1325 WREG32(VGT_GS_PER_VS, 2);
1326 WREG32(VGT_GS_VERTEX_REUSE, 16);
1328 /* more default values. 2D/3D driver should adjust as needed */
1329 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1330 WREG32(VGT_STRMOUT_EN, 0);
1332 WREG32(PA_SC_MODE_CNTL, 0);
1333 WREG32(PA_SC_AA_CONFIG, 0);
1334 WREG32(PA_SC_LINE_STIPPLE, 0);
1335 WREG32(SPI_INPUT_Z, 0);
1336 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1337 WREG32(CB_COLOR7_FRAG, 0);
1339 /* Clear render buffer base addresses */
1340 WREG32(CB_COLOR0_BASE, 0);
1341 WREG32(CB_COLOR1_BASE, 0);
1342 WREG32(CB_COLOR2_BASE, 0);
1343 WREG32(CB_COLOR3_BASE, 0);
1344 WREG32(CB_COLOR4_BASE, 0);
1345 WREG32(CB_COLOR5_BASE, 0);
1346 WREG32(CB_COLOR6_BASE, 0);
1347 WREG32(CB_COLOR7_BASE, 0);
1348 WREG32(CB_COLOR7_FRAG, 0);
1350 switch (rdev->family) {
1355 tmp = TC_L2_SIZE(8);
1359 tmp = TC_L2_SIZE(4);
1362 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1365 tmp = TC_L2_SIZE(0);
1368 WREG32(TC_CNTL, tmp);
1370 tmp = RREG32(HDP_HOST_PATH_CNTL);
1371 WREG32(HDP_HOST_PATH_CNTL, tmp);
1373 tmp = RREG32(ARB_POP);
1374 tmp |= ENABLE_TC128;
1375 WREG32(ARB_POP, tmp);
1377 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1378 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1380 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1385 * Indirect registers accessor
1387 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1391 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1392 (void)RREG32(PCIE_PORT_INDEX);
1393 r = RREG32(PCIE_PORT_DATA);
1397 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1399 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1400 (void)RREG32(PCIE_PORT_INDEX);
1401 WREG32(PCIE_PORT_DATA, (v));
1402 (void)RREG32(PCIE_PORT_DATA);
1408 void r600_cp_stop(struct radeon_device *rdev)
1410 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1413 int r600_init_microcode(struct radeon_device *rdev)
1415 struct platform_device *pdev;
1416 const char *chip_name;
1417 const char *rlc_chip_name;
1418 size_t pfp_req_size, me_req_size, rlc_req_size;
1424 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1427 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1431 switch (rdev->family) {
1434 rlc_chip_name = "R600";
1437 chip_name = "RV610";
1438 rlc_chip_name = "R600";
1441 chip_name = "RV630";
1442 rlc_chip_name = "R600";
1445 chip_name = "RV620";
1446 rlc_chip_name = "R600";
1449 chip_name = "RV635";
1450 rlc_chip_name = "R600";
1453 chip_name = "RV670";
1454 rlc_chip_name = "R600";
1458 chip_name = "RS780";
1459 rlc_chip_name = "R600";
1462 chip_name = "RV770";
1463 rlc_chip_name = "R700";
1467 chip_name = "RV730";
1468 rlc_chip_name = "R700";
1471 chip_name = "RV710";
1472 rlc_chip_name = "R700";
1477 if (rdev->family >= CHIP_RV770) {
1478 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1479 me_req_size = R700_PM4_UCODE_SIZE * 4;
1480 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1482 pfp_req_size = PFP_UCODE_SIZE * 4;
1483 me_req_size = PM4_UCODE_SIZE * 12;
1484 rlc_req_size = RLC_UCODE_SIZE * 4;
1487 DRM_INFO("Loading %s Microcode\n", chip_name);
1489 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1490 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1493 if (rdev->pfp_fw->size != pfp_req_size) {
1495 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1496 rdev->pfp_fw->size, fw_name);
1501 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1502 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1505 if (rdev->me_fw->size != me_req_size) {
1507 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1508 rdev->me_fw->size, fw_name);
1512 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1513 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1516 if (rdev->rlc_fw->size != rlc_req_size) {
1518 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1519 rdev->rlc_fw->size, fw_name);
1524 platform_device_unregister(pdev);
1529 "r600_cp: Failed to load firmware \"%s\"\n",
1531 release_firmware(rdev->pfp_fw);
1532 rdev->pfp_fw = NULL;
1533 release_firmware(rdev->me_fw);
1535 release_firmware(rdev->rlc_fw);
1536 rdev->rlc_fw = NULL;
1541 static int r600_cp_load_microcode(struct radeon_device *rdev)
1543 const __be32 *fw_data;
1546 if (!rdev->me_fw || !rdev->pfp_fw)
1551 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1554 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1555 RREG32(GRBM_SOFT_RESET);
1557 WREG32(GRBM_SOFT_RESET, 0);
1559 WREG32(CP_ME_RAM_WADDR, 0);
1561 fw_data = (const __be32 *)rdev->me_fw->data;
1562 WREG32(CP_ME_RAM_WADDR, 0);
1563 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1564 WREG32(CP_ME_RAM_DATA,
1565 be32_to_cpup(fw_data++));
1567 fw_data = (const __be32 *)rdev->pfp_fw->data;
1568 WREG32(CP_PFP_UCODE_ADDR, 0);
1569 for (i = 0; i < PFP_UCODE_SIZE; i++)
1570 WREG32(CP_PFP_UCODE_DATA,
1571 be32_to_cpup(fw_data++));
1573 WREG32(CP_PFP_UCODE_ADDR, 0);
1574 WREG32(CP_ME_RAM_WADDR, 0);
1575 WREG32(CP_ME_RAM_RADDR, 0);
1579 int r600_cp_start(struct radeon_device *rdev)
1584 r = radeon_ring_lock(rdev, 7);
1586 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1589 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1590 radeon_ring_write(rdev, 0x1);
1591 if (rdev->family < CHIP_RV770) {
1592 radeon_ring_write(rdev, 0x3);
1593 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1595 radeon_ring_write(rdev, 0x0);
1596 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1598 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1599 radeon_ring_write(rdev, 0);
1600 radeon_ring_write(rdev, 0);
1601 radeon_ring_unlock_commit(rdev);
1604 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1608 int r600_cp_resume(struct radeon_device *rdev)
1615 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1616 RREG32(GRBM_SOFT_RESET);
1618 WREG32(GRBM_SOFT_RESET, 0);
1620 /* Set ring buffer size */
1621 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1622 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1624 tmp |= BUF_SWAP_32BIT;
1626 WREG32(CP_RB_CNTL, tmp);
1627 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1629 /* Set the write pointer delay */
1630 WREG32(CP_RB_WPTR_DELAY, 0);
1632 /* Initialize the ring buffer's read and write pointers */
1633 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1634 WREG32(CP_RB_RPTR_WR, 0);
1635 WREG32(CP_RB_WPTR, 0);
1636 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1637 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1639 WREG32(CP_RB_CNTL, tmp);
1641 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1642 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1644 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1645 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1647 r600_cp_start(rdev);
1648 rdev->cp.ready = true;
1649 r = radeon_ring_test(rdev);
1651 rdev->cp.ready = false;
1657 void r600_cp_commit(struct radeon_device *rdev)
1659 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1660 (void)RREG32(CP_RB_WPTR);
1663 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1667 /* Align ring size */
1668 rb_bufsz = drm_order(ring_size / 8);
1669 ring_size = (1 << (rb_bufsz + 1)) * 4;
1670 rdev->cp.ring_size = ring_size;
1671 rdev->cp.align_mask = 16 - 1;
1674 void r600_cp_fini(struct radeon_device *rdev)
1677 radeon_ring_fini(rdev);
1682 * GPU scratch registers helpers function.
1684 void r600_scratch_init(struct radeon_device *rdev)
1688 rdev->scratch.num_reg = 7;
1689 for (i = 0; i < rdev->scratch.num_reg; i++) {
1690 rdev->scratch.free[i] = true;
1691 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1695 int r600_ring_test(struct radeon_device *rdev)
1702 r = radeon_scratch_get(rdev, &scratch);
1704 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1707 WREG32(scratch, 0xCAFEDEAD);
1708 r = radeon_ring_lock(rdev, 3);
1710 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1711 radeon_scratch_free(rdev, scratch);
1714 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1715 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1716 radeon_ring_write(rdev, 0xDEADBEEF);
1717 radeon_ring_unlock_commit(rdev);
1718 for (i = 0; i < rdev->usec_timeout; i++) {
1719 tmp = RREG32(scratch);
1720 if (tmp == 0xDEADBEEF)
1724 if (i < rdev->usec_timeout) {
1725 DRM_INFO("ring test succeeded in %d usecs\n", i);
1727 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1731 radeon_scratch_free(rdev, scratch);
1735 void r600_wb_disable(struct radeon_device *rdev)
1739 WREG32(SCRATCH_UMSK, 0);
1740 if (rdev->wb.wb_obj) {
1741 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1742 if (unlikely(r != 0))
1744 radeon_bo_kunmap(rdev->wb.wb_obj);
1745 radeon_bo_unpin(rdev->wb.wb_obj);
1746 radeon_bo_unreserve(rdev->wb.wb_obj);
1750 void r600_wb_fini(struct radeon_device *rdev)
1752 r600_wb_disable(rdev);
1753 if (rdev->wb.wb_obj) {
1754 radeon_bo_unref(&rdev->wb.wb_obj);
1756 rdev->wb.wb_obj = NULL;
1760 int r600_wb_enable(struct radeon_device *rdev)
1764 if (rdev->wb.wb_obj == NULL) {
1765 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1766 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1768 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1771 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1772 if (unlikely(r != 0)) {
1776 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1777 &rdev->wb.gpu_addr);
1779 radeon_bo_unreserve(rdev->wb.wb_obj);
1780 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1784 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1785 radeon_bo_unreserve(rdev->wb.wb_obj);
1787 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1792 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1793 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1794 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1795 WREG32(SCRATCH_UMSK, 0xff);
1799 void r600_fence_ring_emit(struct radeon_device *rdev,
1800 struct radeon_fence *fence)
1802 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1804 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1805 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1806 /* wait for 3D idle clean */
1807 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1808 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1809 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1810 /* Emit fence sequence & fire IRQ */
1811 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1812 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1813 radeon_ring_write(rdev, fence->seq);
1814 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1815 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1816 radeon_ring_write(rdev, RB_INT_STAT);
1819 int r600_copy_blit(struct radeon_device *rdev,
1820 uint64_t src_offset, uint64_t dst_offset,
1821 unsigned num_pages, struct radeon_fence *fence)
1825 mutex_lock(&rdev->r600_blit.mutex);
1826 rdev->r600_blit.vb_ib = NULL;
1827 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1829 if (rdev->r600_blit.vb_ib)
1830 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1831 mutex_unlock(&rdev->r600_blit.mutex);
1834 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1835 r600_blit_done_copy(rdev, fence);
1836 mutex_unlock(&rdev->r600_blit.mutex);
1840 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1841 uint32_t tiling_flags, uint32_t pitch,
1842 uint32_t offset, uint32_t obj_size)
1844 /* FIXME: implement */
1848 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1850 /* FIXME: implement */
1854 bool r600_card_posted(struct radeon_device *rdev)
1858 /* first check CRTCs */
1859 reg = RREG32(D1CRTC_CONTROL) |
1860 RREG32(D2CRTC_CONTROL);
1864 /* then check MEM_SIZE, in case the crtcs are off */
1865 if (RREG32(CONFIG_MEMSIZE))
1871 int r600_startup(struct radeon_device *rdev)
1875 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1876 r = r600_init_microcode(rdev);
1878 DRM_ERROR("Failed to load firmware!\n");
1883 r600_mc_program(rdev);
1884 if (rdev->flags & RADEON_IS_AGP) {
1885 r600_agp_enable(rdev);
1887 r = r600_pcie_gart_enable(rdev);
1891 r600_gpu_init(rdev);
1892 r = r600_blit_init(rdev);
1894 r600_blit_fini(rdev);
1895 rdev->asic->copy = NULL;
1896 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1898 /* pin copy shader into vram */
1899 if (rdev->r600_blit.shader_obj) {
1900 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1901 if (unlikely(r != 0))
1903 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1904 &rdev->r600_blit.shader_gpu_addr);
1905 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1907 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1912 r = r600_irq_init(rdev);
1914 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1915 radeon_irq_kms_fini(rdev);
1920 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1923 r = r600_cp_load_microcode(rdev);
1926 r = r600_cp_resume(rdev);
1929 /* write back buffer are not vital so don't worry about failure */
1930 r600_wb_enable(rdev);
1934 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1938 temp = RREG32(CONFIG_CNTL);
1939 if (state == false) {
1945 WREG32(CONFIG_CNTL, temp);
1948 int r600_resume(struct radeon_device *rdev)
1952 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1953 * posting will perform necessary task to bring back GPU into good
1957 atom_asic_init(rdev->mode_info.atom_context);
1958 /* Initialize clocks */
1959 r = radeon_clocks_init(rdev);
1964 r = r600_startup(rdev);
1966 DRM_ERROR("r600 startup failed on resume\n");
1970 r = r600_ib_test(rdev);
1972 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1976 r = r600_audio_init(rdev);
1978 DRM_ERROR("radeon: audio resume failed\n");
1985 int r600_suspend(struct radeon_device *rdev)
1989 r600_audio_fini(rdev);
1990 /* FIXME: we should wait for ring to be empty */
1992 rdev->cp.ready = false;
1993 r600_irq_suspend(rdev);
1994 r600_wb_disable(rdev);
1995 r600_pcie_gart_disable(rdev);
1996 /* unpin shaders bo */
1997 if (rdev->r600_blit.shader_obj) {
1998 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2000 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2001 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2007 /* Plan is to move initialization in that function and use
2008 * helper function so that radeon_device_init pretty much
2009 * do nothing more than calling asic specific function. This
2010 * should also allow to remove a bunch of callback function
2013 int r600_init(struct radeon_device *rdev)
2017 r = radeon_dummy_page_init(rdev);
2020 if (r600_debugfs_mc_info_init(rdev)) {
2021 DRM_ERROR("Failed to register debugfs file for mc !\n");
2023 /* This don't do much */
2024 r = radeon_gem_init(rdev);
2028 if (!radeon_get_bios(rdev)) {
2029 if (ASIC_IS_AVIVO(rdev))
2032 /* Must be an ATOMBIOS */
2033 if (!rdev->is_atom_bios) {
2034 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2037 r = radeon_atombios_init(rdev);
2040 /* Post card if necessary */
2041 if (!r600_card_posted(rdev)) {
2043 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2046 DRM_INFO("GPU not posted. posting now...\n");
2047 atom_asic_init(rdev->mode_info.atom_context);
2049 /* Initialize scratch registers */
2050 r600_scratch_init(rdev);
2051 /* Initialize surface registers */
2052 radeon_surface_init(rdev);
2053 /* Initialize clocks */
2054 radeon_get_clock_info(rdev->ddev);
2055 r = radeon_clocks_init(rdev);
2058 /* Initialize power management */
2059 radeon_pm_init(rdev);
2061 r = radeon_fence_driver_init(rdev);
2064 if (rdev->flags & RADEON_IS_AGP) {
2065 r = radeon_agp_init(rdev);
2067 radeon_agp_disable(rdev);
2069 r = r600_mc_init(rdev);
2072 /* Memory manager */
2073 r = radeon_bo_init(rdev);
2077 r = radeon_irq_kms_init(rdev);
2081 rdev->cp.ring_obj = NULL;
2082 r600_ring_init(rdev, 1024 * 1024);
2084 rdev->ih.ring_obj = NULL;
2085 r600_ih_ring_init(rdev, 64 * 1024);
2087 r = r600_pcie_gart_init(rdev);
2091 rdev->accel_working = true;
2092 r = r600_startup(rdev);
2094 dev_err(rdev->dev, "disabling GPU acceleration\n");
2097 r600_irq_fini(rdev);
2098 radeon_irq_kms_fini(rdev);
2099 r600_pcie_gart_fini(rdev);
2100 rdev->accel_working = false;
2102 if (rdev->accel_working) {
2103 r = radeon_ib_pool_init(rdev);
2105 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2106 rdev->accel_working = false;
2108 r = r600_ib_test(rdev);
2110 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2111 rdev->accel_working = false;
2116 r = r600_audio_init(rdev);
2118 return r; /* TODO error handling */
2122 void r600_fini(struct radeon_device *rdev)
2124 radeon_pm_fini(rdev);
2125 r600_audio_fini(rdev);
2126 r600_blit_fini(rdev);
2129 r600_irq_fini(rdev);
2130 radeon_irq_kms_fini(rdev);
2131 r600_pcie_gart_fini(rdev);
2132 radeon_agp_fini(rdev);
2133 radeon_gem_fini(rdev);
2134 radeon_fence_driver_fini(rdev);
2135 radeon_clocks_fini(rdev);
2136 radeon_bo_fini(rdev);
2137 radeon_atombios_fini(rdev);
2140 radeon_dummy_page_fini(rdev);
2147 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2149 /* FIXME: implement */
2150 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2151 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2152 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2153 radeon_ring_write(rdev, ib->length_dw);
2156 int r600_ib_test(struct radeon_device *rdev)
2158 struct radeon_ib *ib;
2164 r = radeon_scratch_get(rdev, &scratch);
2166 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2169 WREG32(scratch, 0xCAFEDEAD);
2170 r = radeon_ib_get(rdev, &ib);
2172 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2175 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2176 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2177 ib->ptr[2] = 0xDEADBEEF;
2178 ib->ptr[3] = PACKET2(0);
2179 ib->ptr[4] = PACKET2(0);
2180 ib->ptr[5] = PACKET2(0);
2181 ib->ptr[6] = PACKET2(0);
2182 ib->ptr[7] = PACKET2(0);
2183 ib->ptr[8] = PACKET2(0);
2184 ib->ptr[9] = PACKET2(0);
2185 ib->ptr[10] = PACKET2(0);
2186 ib->ptr[11] = PACKET2(0);
2187 ib->ptr[12] = PACKET2(0);
2188 ib->ptr[13] = PACKET2(0);
2189 ib->ptr[14] = PACKET2(0);
2190 ib->ptr[15] = PACKET2(0);
2192 r = radeon_ib_schedule(rdev, ib);
2194 radeon_scratch_free(rdev, scratch);
2195 radeon_ib_free(rdev, &ib);
2196 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2199 r = radeon_fence_wait(ib->fence, false);
2201 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2204 for (i = 0; i < rdev->usec_timeout; i++) {
2205 tmp = RREG32(scratch);
2206 if (tmp == 0xDEADBEEF)
2210 if (i < rdev->usec_timeout) {
2211 DRM_INFO("ib test succeeded in %u usecs\n", i);
2213 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2217 radeon_scratch_free(rdev, scratch);
2218 radeon_ib_free(rdev, &ib);
2225 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2226 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2227 * writing to the ring and the GPU consuming, the GPU writes to the ring
2228 * and host consumes. As the host irq handler processes interrupts, it
2229 * increments the rptr. When the rptr catches up with the wptr, all the
2230 * current interrupts have been processed.
2233 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2237 /* Align ring size */
2238 rb_bufsz = drm_order(ring_size / 4);
2239 ring_size = (1 << rb_bufsz) * 4;
2240 rdev->ih.ring_size = ring_size;
2241 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2245 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2249 /* Allocate ring buffer */
2250 if (rdev->ih.ring_obj == NULL) {
2251 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2253 RADEON_GEM_DOMAIN_GTT,
2254 &rdev->ih.ring_obj);
2256 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2259 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2260 if (unlikely(r != 0))
2262 r = radeon_bo_pin(rdev->ih.ring_obj,
2263 RADEON_GEM_DOMAIN_GTT,
2264 &rdev->ih.gpu_addr);
2266 radeon_bo_unreserve(rdev->ih.ring_obj);
2267 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2270 r = radeon_bo_kmap(rdev->ih.ring_obj,
2271 (void **)&rdev->ih.ring);
2272 radeon_bo_unreserve(rdev->ih.ring_obj);
2274 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2281 static void r600_ih_ring_fini(struct radeon_device *rdev)
2284 if (rdev->ih.ring_obj) {
2285 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2286 if (likely(r == 0)) {
2287 radeon_bo_kunmap(rdev->ih.ring_obj);
2288 radeon_bo_unpin(rdev->ih.ring_obj);
2289 radeon_bo_unreserve(rdev->ih.ring_obj);
2291 radeon_bo_unref(&rdev->ih.ring_obj);
2292 rdev->ih.ring = NULL;
2293 rdev->ih.ring_obj = NULL;
2297 static void r600_rlc_stop(struct radeon_device *rdev)
2300 if (rdev->family >= CHIP_RV770) {
2301 /* r7xx asics need to soft reset RLC before halting */
2302 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2303 RREG32(SRBM_SOFT_RESET);
2305 WREG32(SRBM_SOFT_RESET, 0);
2306 RREG32(SRBM_SOFT_RESET);
2309 WREG32(RLC_CNTL, 0);
2312 static void r600_rlc_start(struct radeon_device *rdev)
2314 WREG32(RLC_CNTL, RLC_ENABLE);
2317 static int r600_rlc_init(struct radeon_device *rdev)
2320 const __be32 *fw_data;
2325 r600_rlc_stop(rdev);
2327 WREG32(RLC_HB_BASE, 0);
2328 WREG32(RLC_HB_CNTL, 0);
2329 WREG32(RLC_HB_RPTR, 0);
2330 WREG32(RLC_HB_WPTR, 0);
2331 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2332 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2333 WREG32(RLC_MC_CNTL, 0);
2334 WREG32(RLC_UCODE_CNTL, 0);
2336 fw_data = (const __be32 *)rdev->rlc_fw->data;
2337 if (rdev->family >= CHIP_RV770) {
2338 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2339 WREG32(RLC_UCODE_ADDR, i);
2340 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2343 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2344 WREG32(RLC_UCODE_ADDR, i);
2345 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2348 WREG32(RLC_UCODE_ADDR, 0);
2350 r600_rlc_start(rdev);
2355 static void r600_enable_interrupts(struct radeon_device *rdev)
2357 u32 ih_cntl = RREG32(IH_CNTL);
2358 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2360 ih_cntl |= ENABLE_INTR;
2361 ih_rb_cntl |= IH_RB_ENABLE;
2362 WREG32(IH_CNTL, ih_cntl);
2363 WREG32(IH_RB_CNTL, ih_rb_cntl);
2364 rdev->ih.enabled = true;
2367 static void r600_disable_interrupts(struct radeon_device *rdev)
2369 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2370 u32 ih_cntl = RREG32(IH_CNTL);
2372 ih_rb_cntl &= ~IH_RB_ENABLE;
2373 ih_cntl &= ~ENABLE_INTR;
2374 WREG32(IH_RB_CNTL, ih_rb_cntl);
2375 WREG32(IH_CNTL, ih_cntl);
2376 /* set rptr, wptr to 0 */
2377 WREG32(IH_RB_RPTR, 0);
2378 WREG32(IH_RB_WPTR, 0);
2379 rdev->ih.enabled = false;
2384 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2388 WREG32(CP_INT_CNTL, 0);
2389 WREG32(GRBM_INT_CNTL, 0);
2390 WREG32(DxMODE_INT_MASK, 0);
2391 if (ASIC_IS_DCE3(rdev)) {
2392 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2393 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2394 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2395 WREG32(DC_HPD1_INT_CONTROL, tmp);
2396 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2397 WREG32(DC_HPD2_INT_CONTROL, tmp);
2398 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2399 WREG32(DC_HPD3_INT_CONTROL, tmp);
2400 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2401 WREG32(DC_HPD4_INT_CONTROL, tmp);
2402 if (ASIC_IS_DCE32(rdev)) {
2403 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2404 WREG32(DC_HPD5_INT_CONTROL, 0);
2405 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2406 WREG32(DC_HPD6_INT_CONTROL, 0);
2409 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2410 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2411 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2412 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2413 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2414 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2415 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2416 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2420 int r600_irq_init(struct radeon_device *rdev)
2424 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2427 ret = r600_ih_ring_alloc(rdev);
2432 r600_disable_interrupts(rdev);
2435 ret = r600_rlc_init(rdev);
2437 r600_ih_ring_fini(rdev);
2441 /* setup interrupt control */
2442 /* set dummy read address to ring address */
2443 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2444 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2445 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2446 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2448 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2449 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2450 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2451 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2453 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2454 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2456 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2457 IH_WPTR_OVERFLOW_CLEAR |
2459 /* WPTR writeback, not yet */
2460 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2461 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2462 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2464 WREG32(IH_RB_CNTL, ih_rb_cntl);
2466 /* set rptr, wptr to 0 */
2467 WREG32(IH_RB_RPTR, 0);
2468 WREG32(IH_RB_WPTR, 0);
2470 /* Default settings for IH_CNTL (disabled at first) */
2471 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2472 /* RPTR_REARM only works if msi's are enabled */
2473 if (rdev->msi_enabled)
2474 ih_cntl |= RPTR_REARM;
2477 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2479 WREG32(IH_CNTL, ih_cntl);
2481 /* force the active interrupt state to all disabled */
2482 r600_disable_interrupt_state(rdev);
2485 r600_enable_interrupts(rdev);
2490 void r600_irq_suspend(struct radeon_device *rdev)
2492 r600_disable_interrupts(rdev);
2493 r600_rlc_stop(rdev);
2496 void r600_irq_fini(struct radeon_device *rdev)
2498 r600_irq_suspend(rdev);
2499 r600_ih_ring_fini(rdev);
2502 int r600_irq_set(struct radeon_device *rdev)
2504 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2506 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2508 if (!rdev->irq.installed) {
2509 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2512 /* don't enable anything if the ih is disabled */
2513 if (!rdev->ih.enabled) {
2514 r600_disable_interrupts(rdev);
2515 /* force the active interrupt state to all disabled */
2516 r600_disable_interrupt_state(rdev);
2520 if (ASIC_IS_DCE3(rdev)) {
2521 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2522 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2523 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2524 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2525 if (ASIC_IS_DCE32(rdev)) {
2526 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2527 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2530 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2531 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2532 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2535 if (rdev->irq.sw_int) {
2536 DRM_DEBUG("r600_irq_set: sw int\n");
2537 cp_int_cntl |= RB_INT_ENABLE;
2539 if (rdev->irq.crtc_vblank_int[0]) {
2540 DRM_DEBUG("r600_irq_set: vblank 0\n");
2541 mode_int |= D1MODE_VBLANK_INT_MASK;
2543 if (rdev->irq.crtc_vblank_int[1]) {
2544 DRM_DEBUG("r600_irq_set: vblank 1\n");
2545 mode_int |= D2MODE_VBLANK_INT_MASK;
2547 if (rdev->irq.hpd[0]) {
2548 DRM_DEBUG("r600_irq_set: hpd 1\n");
2549 hpd1 |= DC_HPDx_INT_EN;
2551 if (rdev->irq.hpd[1]) {
2552 DRM_DEBUG("r600_irq_set: hpd 2\n");
2553 hpd2 |= DC_HPDx_INT_EN;
2555 if (rdev->irq.hpd[2]) {
2556 DRM_DEBUG("r600_irq_set: hpd 3\n");
2557 hpd3 |= DC_HPDx_INT_EN;
2559 if (rdev->irq.hpd[3]) {
2560 DRM_DEBUG("r600_irq_set: hpd 4\n");
2561 hpd4 |= DC_HPDx_INT_EN;
2563 if (rdev->irq.hpd[4]) {
2564 DRM_DEBUG("r600_irq_set: hpd 5\n");
2565 hpd5 |= DC_HPDx_INT_EN;
2567 if (rdev->irq.hpd[5]) {
2568 DRM_DEBUG("r600_irq_set: hpd 6\n");
2569 hpd6 |= DC_HPDx_INT_EN;
2572 WREG32(CP_INT_CNTL, cp_int_cntl);
2573 WREG32(DxMODE_INT_MASK, mode_int);
2574 if (ASIC_IS_DCE3(rdev)) {
2575 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2576 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2577 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2578 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2579 if (ASIC_IS_DCE32(rdev)) {
2580 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2581 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2584 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2585 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2586 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2592 static inline void r600_irq_ack(struct radeon_device *rdev,
2595 u32 *disp_int_cont2)
2599 if (ASIC_IS_DCE3(rdev)) {
2600 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2601 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2602 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2604 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2605 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2606 *disp_int_cont2 = 0;
2609 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2610 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2611 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2612 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2613 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2614 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2615 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2616 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2617 if (*disp_int & DC_HPD1_INTERRUPT) {
2618 if (ASIC_IS_DCE3(rdev)) {
2619 tmp = RREG32(DC_HPD1_INT_CONTROL);
2620 tmp |= DC_HPDx_INT_ACK;
2621 WREG32(DC_HPD1_INT_CONTROL, tmp);
2623 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2624 tmp |= DC_HPDx_INT_ACK;
2625 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2628 if (*disp_int & DC_HPD2_INTERRUPT) {
2629 if (ASIC_IS_DCE3(rdev)) {
2630 tmp = RREG32(DC_HPD2_INT_CONTROL);
2631 tmp |= DC_HPDx_INT_ACK;
2632 WREG32(DC_HPD2_INT_CONTROL, tmp);
2634 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2635 tmp |= DC_HPDx_INT_ACK;
2636 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2639 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2640 if (ASIC_IS_DCE3(rdev)) {
2641 tmp = RREG32(DC_HPD3_INT_CONTROL);
2642 tmp |= DC_HPDx_INT_ACK;
2643 WREG32(DC_HPD3_INT_CONTROL, tmp);
2645 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2646 tmp |= DC_HPDx_INT_ACK;
2647 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2650 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2651 tmp = RREG32(DC_HPD4_INT_CONTROL);
2652 tmp |= DC_HPDx_INT_ACK;
2653 WREG32(DC_HPD4_INT_CONTROL, tmp);
2655 if (ASIC_IS_DCE32(rdev)) {
2656 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2657 tmp = RREG32(DC_HPD5_INT_CONTROL);
2658 tmp |= DC_HPDx_INT_ACK;
2659 WREG32(DC_HPD5_INT_CONTROL, tmp);
2661 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2662 tmp = RREG32(DC_HPD5_INT_CONTROL);
2663 tmp |= DC_HPDx_INT_ACK;
2664 WREG32(DC_HPD6_INT_CONTROL, tmp);
2669 void r600_irq_disable(struct radeon_device *rdev)
2671 u32 disp_int, disp_int_cont, disp_int_cont2;
2673 r600_disable_interrupts(rdev);
2674 /* Wait and acknowledge irq */
2676 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2677 r600_disable_interrupt_state(rdev);
2680 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2684 /* XXX use writeback */
2685 wptr = RREG32(IH_RB_WPTR);
2687 if (wptr & RB_OVERFLOW) {
2688 /* When a ring buffer overflow happen start parsing interrupt
2689 * from the last not overwritten vector (wptr + 16). Hopefully
2690 * this should allow us to catchup.
2692 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2693 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2694 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2695 tmp = RREG32(IH_RB_CNTL);
2696 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2697 WREG32(IH_RB_CNTL, tmp);
2699 return (wptr & rdev->ih.ptr_mask);
2703 * Each IV ring entry is 128 bits:
2704 * [7:0] - interrupt source id
2706 * [59:32] - interrupt source data
2707 * [127:60] - reserved
2709 * The basic interrupt vector entries
2710 * are decoded as follows:
2711 * src_id src_data description
2716 * 19 0 FP Hot plug detection A
2717 * 19 1 FP Hot plug detection B
2718 * 19 2 DAC A auto-detection
2719 * 19 3 DAC B auto-detection
2723 * 181 - EOP Interrupt
2726 * Note, these are based on r600 and may need to be
2727 * adjusted or added to on newer asics
2730 int r600_irq_process(struct radeon_device *rdev)
2732 u32 wptr = r600_get_ih_wptr(rdev);
2733 u32 rptr = rdev->ih.rptr;
2734 u32 src_id, src_data;
2735 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2736 unsigned long flags;
2737 bool queue_hotplug = false;
2739 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2740 if (!rdev->ih.enabled)
2743 spin_lock_irqsave(&rdev->ih.lock, flags);
2746 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2749 if (rdev->shutdown) {
2750 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2755 /* display interrupts */
2756 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2758 rdev->ih.wptr = wptr;
2759 while (rptr != wptr) {
2760 /* wptr/rptr are in bytes! */
2761 ring_index = rptr / 4;
2762 src_id = rdev->ih.ring[ring_index] & 0xff;
2763 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2766 case 1: /* D1 vblank/vline */
2768 case 0: /* D1 vblank */
2769 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2770 drm_handle_vblank(rdev->ddev, 0);
2771 rdev->pm.vblank_sync = true;
2772 wake_up(&rdev->irq.vblank_queue);
2773 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2774 DRM_DEBUG("IH: D1 vblank\n");
2777 case 1: /* D1 vline */
2778 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2779 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2780 DRM_DEBUG("IH: D1 vline\n");
2784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2788 case 5: /* D2 vblank/vline */
2790 case 0: /* D2 vblank */
2791 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2792 drm_handle_vblank(rdev->ddev, 1);
2793 rdev->pm.vblank_sync = true;
2794 wake_up(&rdev->irq.vblank_queue);
2795 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2796 DRM_DEBUG("IH: D2 vblank\n");
2799 case 1: /* D1 vline */
2800 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2801 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2802 DRM_DEBUG("IH: D2 vline\n");
2806 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2810 case 19: /* HPD/DAC hotplug */
2813 if (disp_int & DC_HPD1_INTERRUPT) {
2814 disp_int &= ~DC_HPD1_INTERRUPT;
2815 queue_hotplug = true;
2816 DRM_DEBUG("IH: HPD1\n");
2820 if (disp_int & DC_HPD2_INTERRUPT) {
2821 disp_int &= ~DC_HPD2_INTERRUPT;
2822 queue_hotplug = true;
2823 DRM_DEBUG("IH: HPD2\n");
2827 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2828 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2829 queue_hotplug = true;
2830 DRM_DEBUG("IH: HPD3\n");
2834 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2835 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2836 queue_hotplug = true;
2837 DRM_DEBUG("IH: HPD4\n");
2841 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2842 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2843 queue_hotplug = true;
2844 DRM_DEBUG("IH: HPD5\n");
2848 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2849 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2850 queue_hotplug = true;
2851 DRM_DEBUG("IH: HPD6\n");
2855 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2859 case 176: /* CP_INT in ring buffer */
2860 case 177: /* CP_INT in IB1 */
2861 case 178: /* CP_INT in IB2 */
2862 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2863 radeon_fence_process(rdev);
2865 case 181: /* CP EOP event */
2866 DRM_DEBUG("IH: CP EOP\n");
2869 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2873 /* wptr/rptr are in bytes! */
2875 rptr &= rdev->ih.ptr_mask;
2877 /* make sure wptr hasn't changed while processing */
2878 wptr = r600_get_ih_wptr(rdev);
2879 if (wptr != rdev->ih.wptr)
2882 queue_work(rdev->wq, &rdev->hotplug_work);
2883 rdev->ih.rptr = rptr;
2884 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2885 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2892 #if defined(CONFIG_DEBUG_FS)
2894 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2896 struct drm_info_node *node = (struct drm_info_node *) m->private;
2897 struct drm_device *dev = node->minor->dev;
2898 struct radeon_device *rdev = dev->dev_private;
2899 unsigned count, i, j;
2901 radeon_ring_free_size(rdev);
2902 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2903 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2904 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2905 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2906 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2907 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2908 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2909 seq_printf(m, "%u dwords in ring\n", count);
2911 for (j = 0; j <= count; j++) {
2912 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2913 i = (i + 1) & rdev->cp.ptr_mask;
2918 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2920 struct drm_info_node *node = (struct drm_info_node *) m->private;
2921 struct drm_device *dev = node->minor->dev;
2922 struct radeon_device *rdev = dev->dev_private;
2924 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2925 DREG32_SYS(m, rdev, VM_L2_STATUS);
2929 static struct drm_info_list r600_mc_info_list[] = {
2930 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2931 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2935 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2937 #if defined(CONFIG_DEBUG_FS)
2938 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2945 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2946 * rdev: radeon device structure
2947 * bo: buffer object struct which userspace is waiting for idle
2949 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2950 * through ring buffer, this leads to corruption in rendering, see
2951 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2952 * directly perform HDP flush by writing register through MMIO.
2954 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2956 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);