2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_mode.h"
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
80 bool connected = false;
82 if (ASIC_IS_DCE3(rdev)) {
85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134 enum radeon_hpd_id hpd)
137 bool connected = r600_hpd_sense(rdev, hpd);
139 if (ASIC_IS_DCE3(rdev)) {
142 tmp = RREG32(DC_HPD1_INT_CONTROL);
144 tmp &= ~DC_HPDx_INT_POLARITY;
146 tmp |= DC_HPDx_INT_POLARITY;
147 WREG32(DC_HPD1_INT_CONTROL, tmp);
150 tmp = RREG32(DC_HPD2_INT_CONTROL);
152 tmp &= ~DC_HPDx_INT_POLARITY;
154 tmp |= DC_HPDx_INT_POLARITY;
155 WREG32(DC_HPD2_INT_CONTROL, tmp);
158 tmp = RREG32(DC_HPD3_INT_CONTROL);
160 tmp &= ~DC_HPDx_INT_POLARITY;
162 tmp |= DC_HPDx_INT_POLARITY;
163 WREG32(DC_HPD3_INT_CONTROL, tmp);
166 tmp = RREG32(DC_HPD4_INT_CONTROL);
168 tmp &= ~DC_HPDx_INT_POLARITY;
170 tmp |= DC_HPDx_INT_POLARITY;
171 WREG32(DC_HPD4_INT_CONTROL, tmp);
174 tmp = RREG32(DC_HPD5_INT_CONTROL);
176 tmp &= ~DC_HPDx_INT_POLARITY;
178 tmp |= DC_HPDx_INT_POLARITY;
179 WREG32(DC_HPD5_INT_CONTROL, tmp);
183 tmp = RREG32(DC_HPD6_INT_CONTROL);
185 tmp &= ~DC_HPDx_INT_POLARITY;
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD6_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
225 void r600_hpd_init(struct radeon_device *rdev)
227 struct drm_device *dev = rdev->ddev;
228 struct drm_connector *connector;
230 if (ASIC_IS_DCE3(rdev)) {
231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev))
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
239 WREG32(DC_HPD1_CONTROL, tmp);
240 rdev->irq.hpd[0] = true;
243 WREG32(DC_HPD2_CONTROL, tmp);
244 rdev->irq.hpd[1] = true;
247 WREG32(DC_HPD3_CONTROL, tmp);
248 rdev->irq.hpd[2] = true;
251 WREG32(DC_HPD4_CONTROL, tmp);
252 rdev->irq.hpd[3] = true;
256 WREG32(DC_HPD5_CONTROL, tmp);
257 rdev->irq.hpd[4] = true;
260 WREG32(DC_HPD6_CONTROL, tmp);
261 rdev->irq.hpd[5] = true;
268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270 switch (radeon_connector->hpd.hpd) {
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273 rdev->irq.hpd[0] = true;
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277 rdev->irq.hpd[1] = true;
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281 rdev->irq.hpd[2] = true;
288 if (rdev->irq.installed)
292 void r600_hpd_fini(struct radeon_device *rdev)
294 struct drm_device *dev = rdev->ddev;
295 struct drm_connector *connector;
297 if (ASIC_IS_DCE3(rdev)) {
298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300 switch (radeon_connector->hpd.hpd) {
302 WREG32(DC_HPD1_CONTROL, 0);
303 rdev->irq.hpd[0] = false;
306 WREG32(DC_HPD2_CONTROL, 0);
307 rdev->irq.hpd[1] = false;
310 WREG32(DC_HPD3_CONTROL, 0);
311 rdev->irq.hpd[2] = false;
314 WREG32(DC_HPD4_CONTROL, 0);
315 rdev->irq.hpd[3] = false;
319 WREG32(DC_HPD5_CONTROL, 0);
320 rdev->irq.hpd[4] = false;
323 WREG32(DC_HPD6_CONTROL, 0);
324 rdev->irq.hpd[5] = false;
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
335 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336 rdev->irq.hpd[0] = false;
339 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340 rdev->irq.hpd[1] = false;
343 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344 rdev->irq.hpd[2] = false;
356 int r600_gart_clear_page(struct radeon_device *rdev, int i)
358 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
361 if (i < 0 || i > rdev->gart.num_gpu_pages)
364 writeq(pte, ((void __iomem *)ptr) + (i * 8));
368 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
373 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
374 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
375 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
376 for (i = 0; i < rdev->usec_timeout; i++) {
378 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
379 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
381 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
391 int r600_pcie_gart_init(struct radeon_device *rdev)
395 if (rdev->gart.table.vram.robj) {
396 WARN(1, "R600 PCIE GART already initialized.\n");
399 /* Initialize common gart structure */
400 r = radeon_gart_init(rdev);
403 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
404 return radeon_gart_table_vram_alloc(rdev);
407 int r600_pcie_gart_enable(struct radeon_device *rdev)
412 if (rdev->gart.table.vram.robj == NULL) {
413 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
416 r = radeon_gart_table_vram_pin(rdev);
421 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
422 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
423 EFFECTIVE_L2_QUEUE_SIZE(7));
424 WREG32(VM_L2_CNTL2, 0);
425 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
426 /* Setup TLB control */
427 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
428 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
429 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
430 ENABLE_WAIT_L2_QUERY;
431 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
434 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
436 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
437 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
438 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
439 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
440 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
441 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
442 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
443 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
444 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
445 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
446 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
447 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
448 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
449 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
450 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
451 (u32)(rdev->dummy_page.addr >> 12));
452 for (i = 1; i < 7; i++)
453 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
455 r600_pcie_gart_tlb_flush(rdev);
456 rdev->gart.ready = true;
460 void r600_pcie_gart_disable(struct radeon_device *rdev)
465 /* Disable all tables */
466 for (i = 0; i < 7; i++)
467 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
469 /* Disable L2 cache */
470 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
471 EFFECTIVE_L2_QUEUE_SIZE(7));
472 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
473 /* Setup L1 TLB control */
474 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
475 ENABLE_WAIT_L2_QUERY;
476 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
482 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
483 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
484 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
485 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
486 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
487 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
488 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
489 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
490 if (rdev->gart.table.vram.robj) {
491 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
492 if (likely(r == 0)) {
493 radeon_bo_kunmap(rdev->gart.table.vram.robj);
494 radeon_bo_unpin(rdev->gart.table.vram.robj);
495 radeon_bo_unreserve(rdev->gart.table.vram.robj);
500 void r600_pcie_gart_fini(struct radeon_device *rdev)
502 r600_pcie_gart_disable(rdev);
503 radeon_gart_table_vram_free(rdev);
504 radeon_gart_fini(rdev);
507 void r600_agp_enable(struct radeon_device *rdev)
513 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
514 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
515 EFFECTIVE_L2_QUEUE_SIZE(7));
516 WREG32(VM_L2_CNTL2, 0);
517 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
518 /* Setup TLB control */
519 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
520 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
521 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
522 ENABLE_WAIT_L2_QUERY;
523 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
526 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
528 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
529 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
530 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
531 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
532 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
533 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
534 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
535 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
536 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
537 for (i = 0; i < 7; i++)
538 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
541 int r600_mc_wait_for_idle(struct radeon_device *rdev)
546 for (i = 0; i < rdev->usec_timeout; i++) {
548 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
556 static void r600_mc_program(struct radeon_device *rdev)
558 struct rv515_mc_save save;
563 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
564 WREG32((0x2c14 + j), 0x00000000);
565 WREG32((0x2c18 + j), 0x00000000);
566 WREG32((0x2c1c + j), 0x00000000);
567 WREG32((0x2c20 + j), 0x00000000);
568 WREG32((0x2c24 + j), 0x00000000);
570 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
572 rv515_mc_stop(rdev, &save);
573 if (r600_mc_wait_for_idle(rdev)) {
574 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
576 /* Lockout access through VGA aperture (doesn't exist before R600) */
577 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
578 /* Update configuration */
579 if (rdev->flags & RADEON_IS_AGP) {
580 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
581 /* VRAM before AGP */
582 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
583 rdev->mc.vram_start >> 12);
584 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
585 rdev->mc.gtt_end >> 12);
588 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
589 rdev->mc.gtt_start >> 12);
590 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
591 rdev->mc.vram_end >> 12);
594 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
595 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
597 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
598 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
599 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
600 WREG32(MC_VM_FB_LOCATION, tmp);
601 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
602 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
603 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
604 if (rdev->flags & RADEON_IS_AGP) {
605 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
606 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
607 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
609 WREG32(MC_VM_AGP_BASE, 0);
610 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
611 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
613 if (r600_mc_wait_for_idle(rdev)) {
614 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
616 rv515_mc_resume(rdev, &save);
617 /* we need to own VRAM, so turn off the VGA renderer here
618 * to stop it overwriting our objects */
619 rv515_vga_render_disable(rdev);
622 int r600_mc_init(struct radeon_device *rdev)
626 int chansize, numchan;
628 /* Get VRAM informations */
629 rdev->mc.vram_is_ddr = true;
630 tmp = RREG32(RAMCFG);
631 if (tmp & CHANSIZE_OVERRIDE) {
633 } else if (tmp & CHANSIZE_MASK) {
639 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
654 rdev->mc.vram_width = numchan * chansize;
655 /* Could aper size report 0 ? */
656 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
657 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
658 /* Setup GPU memory space */
659 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
660 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
662 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
663 rdev->mc.mc_vram_size = rdev->mc.aper_size;
665 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
666 rdev->mc.real_vram_size = rdev->mc.aper_size;
668 if (rdev->flags & RADEON_IS_AGP) {
669 /* gtt_size is setup by radeon_agp_init */
670 rdev->mc.gtt_location = rdev->mc.agp_base;
671 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
672 /* Try to put vram before or after AGP because we
673 * we want SYSTEM_APERTURE to cover both VRAM and
674 * AGP so that GPU can catch out of VRAM/AGP access
676 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
677 /* Enought place before */
678 rdev->mc.vram_location = rdev->mc.gtt_location -
679 rdev->mc.mc_vram_size;
680 } else if (tmp > rdev->mc.mc_vram_size) {
681 /* Enought place after */
682 rdev->mc.vram_location = rdev->mc.gtt_location +
685 /* Try to setup VRAM then AGP might not
686 * not work on some card
688 rdev->mc.vram_location = 0x00000000UL;
689 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
692 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
693 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
695 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
696 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
697 /* Enough place after vram */
698 rdev->mc.gtt_location = tmp;
699 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
700 /* Enough place before vram */
701 rdev->mc.gtt_location = 0;
703 /* Not enough place after or before shrink
706 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
707 rdev->mc.gtt_location = 0;
708 rdev->mc.gtt_size = rdev->mc.vram_location;
710 rdev->mc.gtt_location = tmp;
711 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
714 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
716 rdev->mc.vram_start = rdev->mc.vram_location;
717 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
718 rdev->mc.gtt_start = rdev->mc.gtt_location;
719 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
720 /* FIXME: we should enforce default clock in case GPU is not in
723 a.full = rfixed_const(100);
724 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
725 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
727 if (rdev->flags & RADEON_IS_IGP)
728 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
733 /* We doesn't check that the GPU really needs a reset we simply do the
734 * reset, it's up to the caller to determine if the GPU needs one. We
735 * might add an helper function to check that.
737 int r600_gpu_soft_reset(struct radeon_device *rdev)
739 struct rv515_mc_save save;
740 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
741 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
742 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
743 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
744 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
745 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
746 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
747 S_008010_GUI_ACTIVE(1);
748 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
749 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
750 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
751 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
752 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
753 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
754 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
755 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
759 dev_info(rdev->dev, "GPU softreset \n");
760 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
761 RREG32(R_008010_GRBM_STATUS));
762 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
763 RREG32(R_008014_GRBM_STATUS2));
764 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
765 RREG32(R_000E50_SRBM_STATUS));
766 rv515_mc_stop(rdev, &save);
767 if (r600_mc_wait_for_idle(rdev)) {
768 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
770 /* Disable CP parsing/prefetching */
771 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
772 /* Check if any of the rendering block is busy and reset it */
773 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
774 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
775 tmp = S_008020_SOFT_RESET_CR(1) |
776 S_008020_SOFT_RESET_DB(1) |
777 S_008020_SOFT_RESET_CB(1) |
778 S_008020_SOFT_RESET_PA(1) |
779 S_008020_SOFT_RESET_SC(1) |
780 S_008020_SOFT_RESET_SMX(1) |
781 S_008020_SOFT_RESET_SPI(1) |
782 S_008020_SOFT_RESET_SX(1) |
783 S_008020_SOFT_RESET_SH(1) |
784 S_008020_SOFT_RESET_TC(1) |
785 S_008020_SOFT_RESET_TA(1) |
786 S_008020_SOFT_RESET_VC(1) |
787 S_008020_SOFT_RESET_VGT(1);
788 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
789 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
790 (void)RREG32(R_008020_GRBM_SOFT_RESET);
792 WREG32(R_008020_GRBM_SOFT_RESET, 0);
793 (void)RREG32(R_008020_GRBM_SOFT_RESET);
795 /* Reset CP (we always reset CP) */
796 tmp = S_008020_SOFT_RESET_CP(1);
797 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
798 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
799 (void)RREG32(R_008020_GRBM_SOFT_RESET);
801 WREG32(R_008020_GRBM_SOFT_RESET, 0);
802 (void)RREG32(R_008020_GRBM_SOFT_RESET);
803 /* Reset others GPU block if necessary */
804 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
805 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
806 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
807 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
808 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
809 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
810 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
811 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
812 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
813 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
814 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
816 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
820 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
822 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
824 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
825 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
826 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
827 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
828 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
829 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
830 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
832 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
833 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
834 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
835 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
837 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
838 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
839 /* Wait a little for things to settle down */
841 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
842 RREG32(R_008010_GRBM_STATUS));
843 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
844 RREG32(R_008014_GRBM_STATUS2));
845 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
846 RREG32(R_000E50_SRBM_STATUS));
847 /* After reset we need to reinit the asic as GPU often endup in an
850 atom_asic_init(rdev->mode_info.atom_context);
851 rv515_mc_resume(rdev, &save);
855 int r600_gpu_reset(struct radeon_device *rdev)
857 return r600_gpu_soft_reset(rdev);
860 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
862 u32 backend_disable_mask)
865 u32 enabled_backends_mask;
866 u32 enabled_backends_count;
868 u32 swizzle_pipe[R6XX_MAX_PIPES];
872 if (num_tile_pipes > R6XX_MAX_PIPES)
873 num_tile_pipes = R6XX_MAX_PIPES;
874 if (num_tile_pipes < 1)
876 if (num_backends > R6XX_MAX_BACKENDS)
877 num_backends = R6XX_MAX_BACKENDS;
878 if (num_backends < 1)
881 enabled_backends_mask = 0;
882 enabled_backends_count = 0;
883 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
884 if (((backend_disable_mask >> i) & 1) == 0) {
885 enabled_backends_mask |= (1 << i);
886 ++enabled_backends_count;
888 if (enabled_backends_count == num_backends)
892 if (enabled_backends_count == 0) {
893 enabled_backends_mask = 1;
894 enabled_backends_count = 1;
897 if (enabled_backends_count != num_backends)
898 num_backends = enabled_backends_count;
900 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
901 switch (num_tile_pipes) {
957 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
958 while (((1 << cur_backend) & enabled_backends_mask) == 0)
959 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
961 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
963 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
969 int r600_count_pipe_bits(uint32_t val)
973 for (i = 0; i < 32; i++) {
980 void r600_gpu_init(struct radeon_device *rdev)
987 u32 sq_gpr_resource_mgmt_1 = 0;
988 u32 sq_gpr_resource_mgmt_2 = 0;
989 u32 sq_thread_resource_mgmt = 0;
990 u32 sq_stack_resource_mgmt_1 = 0;
991 u32 sq_stack_resource_mgmt_2 = 0;
993 /* FIXME: implement */
994 switch (rdev->family) {
996 rdev->config.r600.max_pipes = 4;
997 rdev->config.r600.max_tile_pipes = 8;
998 rdev->config.r600.max_simds = 4;
999 rdev->config.r600.max_backends = 4;
1000 rdev->config.r600.max_gprs = 256;
1001 rdev->config.r600.max_threads = 192;
1002 rdev->config.r600.max_stack_entries = 256;
1003 rdev->config.r600.max_hw_contexts = 8;
1004 rdev->config.r600.max_gs_threads = 16;
1005 rdev->config.r600.sx_max_export_size = 128;
1006 rdev->config.r600.sx_max_export_pos_size = 16;
1007 rdev->config.r600.sx_max_export_smx_size = 128;
1008 rdev->config.r600.sq_num_cf_insts = 2;
1012 rdev->config.r600.max_pipes = 2;
1013 rdev->config.r600.max_tile_pipes = 2;
1014 rdev->config.r600.max_simds = 3;
1015 rdev->config.r600.max_backends = 1;
1016 rdev->config.r600.max_gprs = 128;
1017 rdev->config.r600.max_threads = 192;
1018 rdev->config.r600.max_stack_entries = 128;
1019 rdev->config.r600.max_hw_contexts = 8;
1020 rdev->config.r600.max_gs_threads = 4;
1021 rdev->config.r600.sx_max_export_size = 128;
1022 rdev->config.r600.sx_max_export_pos_size = 16;
1023 rdev->config.r600.sx_max_export_smx_size = 128;
1024 rdev->config.r600.sq_num_cf_insts = 2;
1030 rdev->config.r600.max_pipes = 1;
1031 rdev->config.r600.max_tile_pipes = 1;
1032 rdev->config.r600.max_simds = 2;
1033 rdev->config.r600.max_backends = 1;
1034 rdev->config.r600.max_gprs = 128;
1035 rdev->config.r600.max_threads = 192;
1036 rdev->config.r600.max_stack_entries = 128;
1037 rdev->config.r600.max_hw_contexts = 4;
1038 rdev->config.r600.max_gs_threads = 4;
1039 rdev->config.r600.sx_max_export_size = 128;
1040 rdev->config.r600.sx_max_export_pos_size = 16;
1041 rdev->config.r600.sx_max_export_smx_size = 128;
1042 rdev->config.r600.sq_num_cf_insts = 1;
1045 rdev->config.r600.max_pipes = 4;
1046 rdev->config.r600.max_tile_pipes = 4;
1047 rdev->config.r600.max_simds = 4;
1048 rdev->config.r600.max_backends = 4;
1049 rdev->config.r600.max_gprs = 192;
1050 rdev->config.r600.max_threads = 192;
1051 rdev->config.r600.max_stack_entries = 256;
1052 rdev->config.r600.max_hw_contexts = 8;
1053 rdev->config.r600.max_gs_threads = 16;
1054 rdev->config.r600.sx_max_export_size = 128;
1055 rdev->config.r600.sx_max_export_pos_size = 16;
1056 rdev->config.r600.sx_max_export_smx_size = 128;
1057 rdev->config.r600.sq_num_cf_insts = 2;
1063 /* Initialize HDP */
1064 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1065 WREG32((0x2c14 + j), 0x00000000);
1066 WREG32((0x2c18 + j), 0x00000000);
1067 WREG32((0x2c1c + j), 0x00000000);
1068 WREG32((0x2c20 + j), 0x00000000);
1069 WREG32((0x2c24 + j), 0x00000000);
1072 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1076 ramcfg = RREG32(RAMCFG);
1077 switch (rdev->config.r600.max_tile_pipes) {
1079 tiling_config |= PIPE_TILING(0);
1080 rdev->config.r600.tiling_npipes = 1;
1083 tiling_config |= PIPE_TILING(1);
1084 rdev->config.r600.tiling_npipes = 2;
1087 tiling_config |= PIPE_TILING(2);
1088 rdev->config.r600.tiling_npipes = 4;
1091 tiling_config |= PIPE_TILING(3);
1092 rdev->config.r600.tiling_npipes = 8;
1097 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1098 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1099 tiling_config |= GROUP_SIZE(0);
1100 rdev->config.r600.tiling_group_size = 256;
1101 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1103 tiling_config |= ROW_TILING(3);
1104 tiling_config |= SAMPLE_SPLIT(3);
1106 tiling_config |= ROW_TILING(tmp);
1107 tiling_config |= SAMPLE_SPLIT(tmp);
1109 tiling_config |= BANK_SWAPS(1);
1110 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1111 rdev->config.r600.max_backends,
1112 (0xff << rdev->config.r600.max_backends) & 0xff);
1113 tiling_config |= BACKEND_MAP(tmp);
1114 WREG32(GB_TILING_CONFIG, tiling_config);
1115 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1116 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1118 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1119 WREG32(CC_RB_BACKEND_DISABLE, tmp);
1122 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1123 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1124 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1125 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1127 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1128 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1129 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1131 /* Setup some CP states */
1132 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1133 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1135 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1136 SYNC_WALKER | SYNC_ALIGNER));
1137 /* Setup various GPU states */
1138 if (rdev->family == CHIP_RV670)
1139 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1141 tmp = RREG32(SX_DEBUG_1);
1142 tmp |= SMX_EVENT_RELEASE;
1143 if ((rdev->family > CHIP_R600))
1144 tmp |= ENABLE_NEW_SMX_ADDRESS;
1145 WREG32(SX_DEBUG_1, tmp);
1147 if (((rdev->family) == CHIP_R600) ||
1148 ((rdev->family) == CHIP_RV630) ||
1149 ((rdev->family) == CHIP_RV610) ||
1150 ((rdev->family) == CHIP_RV620) ||
1151 ((rdev->family) == CHIP_RS780) ||
1152 ((rdev->family) == CHIP_RS880)) {
1153 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1155 WREG32(DB_DEBUG, 0);
1157 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1158 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1160 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1161 WREG32(VGT_NUM_INSTANCES, 0);
1163 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1164 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1166 tmp = RREG32(SQ_MS_FIFO_SIZES);
1167 if (((rdev->family) == CHIP_RV610) ||
1168 ((rdev->family) == CHIP_RV620) ||
1169 ((rdev->family) == CHIP_RS780) ||
1170 ((rdev->family) == CHIP_RS880)) {
1171 tmp = (CACHE_FIFO_SIZE(0xa) |
1172 FETCH_FIFO_HIWATER(0xa) |
1173 DONE_FIFO_HIWATER(0xe0) |
1174 ALU_UPDATE_FIFO_HIWATER(0x8));
1175 } else if (((rdev->family) == CHIP_R600) ||
1176 ((rdev->family) == CHIP_RV630)) {
1177 tmp &= ~DONE_FIFO_HIWATER(0xff);
1178 tmp |= DONE_FIFO_HIWATER(0x4);
1180 WREG32(SQ_MS_FIFO_SIZES, tmp);
1182 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1183 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1185 sq_config = RREG32(SQ_CONFIG);
1186 sq_config &= ~(PS_PRIO(3) |
1190 sq_config |= (DX9_CONSTS |
1197 if ((rdev->family) == CHIP_R600) {
1198 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1200 NUM_CLAUSE_TEMP_GPRS(4));
1201 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1203 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1204 NUM_VS_THREADS(48) |
1207 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1208 NUM_VS_STACK_ENTRIES(128));
1209 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1210 NUM_ES_STACK_ENTRIES(0));
1211 } else if (((rdev->family) == CHIP_RV610) ||
1212 ((rdev->family) == CHIP_RV620) ||
1213 ((rdev->family) == CHIP_RS780) ||
1214 ((rdev->family) == CHIP_RS880)) {
1215 /* no vertex cache */
1216 sq_config &= ~VC_ENABLE;
1218 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1220 NUM_CLAUSE_TEMP_GPRS(2));
1221 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1223 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1224 NUM_VS_THREADS(78) |
1226 NUM_ES_THREADS(31));
1227 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1228 NUM_VS_STACK_ENTRIES(40));
1229 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1230 NUM_ES_STACK_ENTRIES(16));
1231 } else if (((rdev->family) == CHIP_RV630) ||
1232 ((rdev->family) == CHIP_RV635)) {
1233 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1235 NUM_CLAUSE_TEMP_GPRS(2));
1236 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1238 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1239 NUM_VS_THREADS(78) |
1241 NUM_ES_THREADS(31));
1242 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1243 NUM_VS_STACK_ENTRIES(40));
1244 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1245 NUM_ES_STACK_ENTRIES(16));
1246 } else if ((rdev->family) == CHIP_RV670) {
1247 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1249 NUM_CLAUSE_TEMP_GPRS(2));
1250 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1252 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1253 NUM_VS_THREADS(78) |
1255 NUM_ES_THREADS(31));
1256 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1257 NUM_VS_STACK_ENTRIES(64));
1258 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1259 NUM_ES_STACK_ENTRIES(64));
1262 WREG32(SQ_CONFIG, sq_config);
1263 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1264 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1265 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1266 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1267 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1269 if (((rdev->family) == CHIP_RV610) ||
1270 ((rdev->family) == CHIP_RV620) ||
1271 ((rdev->family) == CHIP_RS780) ||
1272 ((rdev->family) == CHIP_RS880)) {
1273 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1275 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1278 /* More default values. 2D/3D driver should adjust as needed */
1279 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1280 S1_X(0x4) | S1_Y(0xc)));
1281 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1282 S1_X(0x2) | S1_Y(0x2) |
1283 S2_X(0xa) | S2_Y(0x6) |
1284 S3_X(0x6) | S3_Y(0xa)));
1285 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1286 S1_X(0x4) | S1_Y(0xc) |
1287 S2_X(0x1) | S2_Y(0x6) |
1288 S3_X(0xa) | S3_Y(0xe)));
1289 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1290 S5_X(0x0) | S5_Y(0x0) |
1291 S6_X(0xb) | S6_Y(0x4) |
1292 S7_X(0x7) | S7_Y(0x8)));
1294 WREG32(VGT_STRMOUT_EN, 0);
1295 tmp = rdev->config.r600.max_pipes * 16;
1296 switch (rdev->family) {
1312 WREG32(VGT_ES_PER_GS, 128);
1313 WREG32(VGT_GS_PER_ES, tmp);
1314 WREG32(VGT_GS_PER_VS, 2);
1315 WREG32(VGT_GS_VERTEX_REUSE, 16);
1317 /* more default values. 2D/3D driver should adjust as needed */
1318 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1319 WREG32(VGT_STRMOUT_EN, 0);
1321 WREG32(PA_SC_MODE_CNTL, 0);
1322 WREG32(PA_SC_AA_CONFIG, 0);
1323 WREG32(PA_SC_LINE_STIPPLE, 0);
1324 WREG32(SPI_INPUT_Z, 0);
1325 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1326 WREG32(CB_COLOR7_FRAG, 0);
1328 /* Clear render buffer base addresses */
1329 WREG32(CB_COLOR0_BASE, 0);
1330 WREG32(CB_COLOR1_BASE, 0);
1331 WREG32(CB_COLOR2_BASE, 0);
1332 WREG32(CB_COLOR3_BASE, 0);
1333 WREG32(CB_COLOR4_BASE, 0);
1334 WREG32(CB_COLOR5_BASE, 0);
1335 WREG32(CB_COLOR6_BASE, 0);
1336 WREG32(CB_COLOR7_BASE, 0);
1337 WREG32(CB_COLOR7_FRAG, 0);
1339 switch (rdev->family) {
1344 tmp = TC_L2_SIZE(8);
1348 tmp = TC_L2_SIZE(4);
1351 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1354 tmp = TC_L2_SIZE(0);
1357 WREG32(TC_CNTL, tmp);
1359 tmp = RREG32(HDP_HOST_PATH_CNTL);
1360 WREG32(HDP_HOST_PATH_CNTL, tmp);
1362 tmp = RREG32(ARB_POP);
1363 tmp |= ENABLE_TC128;
1364 WREG32(ARB_POP, tmp);
1366 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1367 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1369 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1374 * Indirect registers accessor
1376 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1380 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1381 (void)RREG32(PCIE_PORT_INDEX);
1382 r = RREG32(PCIE_PORT_DATA);
1386 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1388 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1389 (void)RREG32(PCIE_PORT_INDEX);
1390 WREG32(PCIE_PORT_DATA, (v));
1391 (void)RREG32(PCIE_PORT_DATA);
1397 void r600_cp_stop(struct radeon_device *rdev)
1399 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1402 int r600_init_microcode(struct radeon_device *rdev)
1404 struct platform_device *pdev;
1405 const char *chip_name;
1406 const char *rlc_chip_name;
1407 size_t pfp_req_size, me_req_size, rlc_req_size;
1413 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1416 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1420 switch (rdev->family) {
1423 rlc_chip_name = "R600";
1426 chip_name = "RV610";
1427 rlc_chip_name = "R600";
1430 chip_name = "RV630";
1431 rlc_chip_name = "R600";
1434 chip_name = "RV620";
1435 rlc_chip_name = "R600";
1438 chip_name = "RV635";
1439 rlc_chip_name = "R600";
1442 chip_name = "RV670";
1443 rlc_chip_name = "R600";
1447 chip_name = "RS780";
1448 rlc_chip_name = "R600";
1451 chip_name = "RV770";
1452 rlc_chip_name = "R700";
1456 chip_name = "RV730";
1457 rlc_chip_name = "R700";
1460 chip_name = "RV710";
1461 rlc_chip_name = "R700";
1466 if (rdev->family >= CHIP_RV770) {
1467 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1468 me_req_size = R700_PM4_UCODE_SIZE * 4;
1469 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1471 pfp_req_size = PFP_UCODE_SIZE * 4;
1472 me_req_size = PM4_UCODE_SIZE * 12;
1473 rlc_req_size = RLC_UCODE_SIZE * 4;
1476 DRM_INFO("Loading %s Microcode\n", chip_name);
1478 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1479 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1482 if (rdev->pfp_fw->size != pfp_req_size) {
1484 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1485 rdev->pfp_fw->size, fw_name);
1490 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1491 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1494 if (rdev->me_fw->size != me_req_size) {
1496 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1497 rdev->me_fw->size, fw_name);
1501 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1502 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1505 if (rdev->rlc_fw->size != rlc_req_size) {
1507 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1508 rdev->rlc_fw->size, fw_name);
1513 platform_device_unregister(pdev);
1518 "r600_cp: Failed to load firmware \"%s\"\n",
1520 release_firmware(rdev->pfp_fw);
1521 rdev->pfp_fw = NULL;
1522 release_firmware(rdev->me_fw);
1524 release_firmware(rdev->rlc_fw);
1525 rdev->rlc_fw = NULL;
1530 static int r600_cp_load_microcode(struct radeon_device *rdev)
1532 const __be32 *fw_data;
1535 if (!rdev->me_fw || !rdev->pfp_fw)
1540 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1543 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1544 RREG32(GRBM_SOFT_RESET);
1546 WREG32(GRBM_SOFT_RESET, 0);
1548 WREG32(CP_ME_RAM_WADDR, 0);
1550 fw_data = (const __be32 *)rdev->me_fw->data;
1551 WREG32(CP_ME_RAM_WADDR, 0);
1552 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1553 WREG32(CP_ME_RAM_DATA,
1554 be32_to_cpup(fw_data++));
1556 fw_data = (const __be32 *)rdev->pfp_fw->data;
1557 WREG32(CP_PFP_UCODE_ADDR, 0);
1558 for (i = 0; i < PFP_UCODE_SIZE; i++)
1559 WREG32(CP_PFP_UCODE_DATA,
1560 be32_to_cpup(fw_data++));
1562 WREG32(CP_PFP_UCODE_ADDR, 0);
1563 WREG32(CP_ME_RAM_WADDR, 0);
1564 WREG32(CP_ME_RAM_RADDR, 0);
1568 int r600_cp_start(struct radeon_device *rdev)
1573 r = radeon_ring_lock(rdev, 7);
1575 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1578 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1579 radeon_ring_write(rdev, 0x1);
1580 if (rdev->family < CHIP_RV770) {
1581 radeon_ring_write(rdev, 0x3);
1582 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1584 radeon_ring_write(rdev, 0x0);
1585 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1587 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1588 radeon_ring_write(rdev, 0);
1589 radeon_ring_write(rdev, 0);
1590 radeon_ring_unlock_commit(rdev);
1593 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1597 int r600_cp_resume(struct radeon_device *rdev)
1604 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1605 RREG32(GRBM_SOFT_RESET);
1607 WREG32(GRBM_SOFT_RESET, 0);
1609 /* Set ring buffer size */
1610 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1611 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1613 tmp |= BUF_SWAP_32BIT;
1615 WREG32(CP_RB_CNTL, tmp);
1616 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1618 /* Set the write pointer delay */
1619 WREG32(CP_RB_WPTR_DELAY, 0);
1621 /* Initialize the ring buffer's read and write pointers */
1622 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1623 WREG32(CP_RB_RPTR_WR, 0);
1624 WREG32(CP_RB_WPTR, 0);
1625 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1626 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1628 WREG32(CP_RB_CNTL, tmp);
1630 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1631 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1633 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1634 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1636 r600_cp_start(rdev);
1637 rdev->cp.ready = true;
1638 r = radeon_ring_test(rdev);
1640 rdev->cp.ready = false;
1646 void r600_cp_commit(struct radeon_device *rdev)
1648 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1649 (void)RREG32(CP_RB_WPTR);
1652 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1656 /* Align ring size */
1657 rb_bufsz = drm_order(ring_size / 8);
1658 ring_size = (1 << (rb_bufsz + 1)) * 4;
1659 rdev->cp.ring_size = ring_size;
1660 rdev->cp.align_mask = 16 - 1;
1663 void r600_cp_fini(struct radeon_device *rdev)
1666 radeon_ring_fini(rdev);
1671 * GPU scratch registers helpers function.
1673 void r600_scratch_init(struct radeon_device *rdev)
1677 rdev->scratch.num_reg = 7;
1678 for (i = 0; i < rdev->scratch.num_reg; i++) {
1679 rdev->scratch.free[i] = true;
1680 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1684 int r600_ring_test(struct radeon_device *rdev)
1691 r = radeon_scratch_get(rdev, &scratch);
1693 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1696 WREG32(scratch, 0xCAFEDEAD);
1697 r = radeon_ring_lock(rdev, 3);
1699 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1700 radeon_scratch_free(rdev, scratch);
1703 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1704 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1705 radeon_ring_write(rdev, 0xDEADBEEF);
1706 radeon_ring_unlock_commit(rdev);
1707 for (i = 0; i < rdev->usec_timeout; i++) {
1708 tmp = RREG32(scratch);
1709 if (tmp == 0xDEADBEEF)
1713 if (i < rdev->usec_timeout) {
1714 DRM_INFO("ring test succeeded in %d usecs\n", i);
1716 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1720 radeon_scratch_free(rdev, scratch);
1724 void r600_wb_disable(struct radeon_device *rdev)
1728 WREG32(SCRATCH_UMSK, 0);
1729 if (rdev->wb.wb_obj) {
1730 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1731 if (unlikely(r != 0))
1733 radeon_bo_kunmap(rdev->wb.wb_obj);
1734 radeon_bo_unpin(rdev->wb.wb_obj);
1735 radeon_bo_unreserve(rdev->wb.wb_obj);
1739 void r600_wb_fini(struct radeon_device *rdev)
1741 r600_wb_disable(rdev);
1742 if (rdev->wb.wb_obj) {
1743 radeon_bo_unref(&rdev->wb.wb_obj);
1745 rdev->wb.wb_obj = NULL;
1749 int r600_wb_enable(struct radeon_device *rdev)
1753 if (rdev->wb.wb_obj == NULL) {
1754 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1755 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1757 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1760 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1761 if (unlikely(r != 0)) {
1765 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1766 &rdev->wb.gpu_addr);
1768 radeon_bo_unreserve(rdev->wb.wb_obj);
1769 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1773 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1774 radeon_bo_unreserve(rdev->wb.wb_obj);
1776 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1781 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1782 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1783 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1784 WREG32(SCRATCH_UMSK, 0xff);
1788 void r600_fence_ring_emit(struct radeon_device *rdev,
1789 struct radeon_fence *fence)
1791 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1793 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1794 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1795 /* wait for 3D idle clean */
1796 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1797 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1798 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1799 /* Emit fence sequence & fire IRQ */
1800 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1801 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1802 radeon_ring_write(rdev, fence->seq);
1803 radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1804 radeon_ring_write(rdev, 1);
1805 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1806 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1807 radeon_ring_write(rdev, RB_INT_STAT);
1810 int r600_copy_blit(struct radeon_device *rdev,
1811 uint64_t src_offset, uint64_t dst_offset,
1812 unsigned num_pages, struct radeon_fence *fence)
1816 mutex_lock(&rdev->r600_blit.mutex);
1817 rdev->r600_blit.vb_ib = NULL;
1818 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1820 if (rdev->r600_blit.vb_ib)
1821 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1822 mutex_unlock(&rdev->r600_blit.mutex);
1825 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1826 r600_blit_done_copy(rdev, fence);
1827 mutex_unlock(&rdev->r600_blit.mutex);
1831 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1832 uint32_t tiling_flags, uint32_t pitch,
1833 uint32_t offset, uint32_t obj_size)
1835 /* FIXME: implement */
1839 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1841 /* FIXME: implement */
1845 bool r600_card_posted(struct radeon_device *rdev)
1849 /* first check CRTCs */
1850 reg = RREG32(D1CRTC_CONTROL) |
1851 RREG32(D2CRTC_CONTROL);
1855 /* then check MEM_SIZE, in case the crtcs are off */
1856 if (RREG32(CONFIG_MEMSIZE))
1862 int r600_startup(struct radeon_device *rdev)
1866 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1867 r = r600_init_microcode(rdev);
1869 DRM_ERROR("Failed to load firmware!\n");
1874 r600_mc_program(rdev);
1875 if (rdev->flags & RADEON_IS_AGP) {
1876 r600_agp_enable(rdev);
1878 r = r600_pcie_gart_enable(rdev);
1882 r600_gpu_init(rdev);
1883 r = r600_blit_init(rdev);
1885 r600_blit_fini(rdev);
1886 rdev->asic->copy = NULL;
1887 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1889 /* pin copy shader into vram */
1890 if (rdev->r600_blit.shader_obj) {
1891 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1892 if (unlikely(r != 0))
1894 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1895 &rdev->r600_blit.shader_gpu_addr);
1896 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1898 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1903 r = r600_irq_init(rdev);
1905 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1906 radeon_irq_kms_fini(rdev);
1911 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1914 r = r600_cp_load_microcode(rdev);
1917 r = r600_cp_resume(rdev);
1920 /* write back buffer are not vital so don't worry about failure */
1921 r600_wb_enable(rdev);
1925 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1929 temp = RREG32(CONFIG_CNTL);
1930 if (state == false) {
1936 WREG32(CONFIG_CNTL, temp);
1939 int r600_resume(struct radeon_device *rdev)
1943 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1944 * posting will perform necessary task to bring back GPU into good
1948 atom_asic_init(rdev->mode_info.atom_context);
1949 /* Initialize clocks */
1950 r = radeon_clocks_init(rdev);
1955 r = r600_startup(rdev);
1957 DRM_ERROR("r600 startup failed on resume\n");
1961 r = r600_ib_test(rdev);
1963 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1969 int r600_suspend(struct radeon_device *rdev)
1973 /* FIXME: we should wait for ring to be empty */
1975 rdev->cp.ready = false;
1976 r600_irq_suspend(rdev);
1977 r600_wb_disable(rdev);
1978 r600_pcie_gart_disable(rdev);
1979 /* unpin shaders bo */
1980 if (rdev->r600_blit.shader_obj) {
1981 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1983 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1984 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1990 /* Plan is to move initialization in that function and use
1991 * helper function so that radeon_device_init pretty much
1992 * do nothing more than calling asic specific function. This
1993 * should also allow to remove a bunch of callback function
1996 int r600_init(struct radeon_device *rdev)
2000 r = radeon_dummy_page_init(rdev);
2003 if (r600_debugfs_mc_info_init(rdev)) {
2004 DRM_ERROR("Failed to register debugfs file for mc !\n");
2006 /* This don't do much */
2007 r = radeon_gem_init(rdev);
2011 if (!radeon_get_bios(rdev)) {
2012 if (ASIC_IS_AVIVO(rdev))
2015 /* Must be an ATOMBIOS */
2016 if (!rdev->is_atom_bios) {
2017 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2020 r = radeon_atombios_init(rdev);
2023 /* Post card if necessary */
2024 if (!r600_card_posted(rdev)) {
2026 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2029 DRM_INFO("GPU not posted. posting now...\n");
2030 atom_asic_init(rdev->mode_info.atom_context);
2032 /* Initialize scratch registers */
2033 r600_scratch_init(rdev);
2034 /* Initialize surface registers */
2035 radeon_surface_init(rdev);
2036 /* Initialize clocks */
2037 radeon_get_clock_info(rdev->ddev);
2038 r = radeon_clocks_init(rdev);
2041 /* Initialize power management */
2042 radeon_pm_init(rdev);
2044 r = radeon_fence_driver_init(rdev);
2047 if (rdev->flags & RADEON_IS_AGP) {
2048 r = radeon_agp_init(rdev);
2050 radeon_agp_disable(rdev);
2052 r = r600_mc_init(rdev);
2055 /* Memory manager */
2056 r = radeon_bo_init(rdev);
2060 r = radeon_irq_kms_init(rdev);
2064 rdev->cp.ring_obj = NULL;
2065 r600_ring_init(rdev, 1024 * 1024);
2067 rdev->ih.ring_obj = NULL;
2068 r600_ih_ring_init(rdev, 64 * 1024);
2070 r = r600_pcie_gart_init(rdev);
2074 rdev->accel_working = true;
2075 r = r600_startup(rdev);
2077 dev_err(rdev->dev, "disabling GPU acceleration\n");
2080 r600_irq_fini(rdev);
2081 radeon_irq_kms_fini(rdev);
2082 r600_pcie_gart_fini(rdev);
2083 rdev->accel_working = false;
2085 if (rdev->accel_working) {
2086 r = radeon_ib_pool_init(rdev);
2088 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2089 rdev->accel_working = false;
2091 r = r600_ib_test(rdev);
2093 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2094 rdev->accel_working = false;
2099 r = r600_audio_init(rdev);
2101 return r; /* TODO error handling */
2105 void r600_fini(struct radeon_device *rdev)
2107 r600_audio_fini(rdev);
2108 r600_blit_fini(rdev);
2111 r600_irq_fini(rdev);
2112 radeon_irq_kms_fini(rdev);
2113 r600_pcie_gart_fini(rdev);
2114 radeon_agp_fini(rdev);
2115 radeon_gem_fini(rdev);
2116 radeon_fence_driver_fini(rdev);
2117 radeon_clocks_fini(rdev);
2118 radeon_bo_fini(rdev);
2119 radeon_atombios_fini(rdev);
2122 radeon_dummy_page_fini(rdev);
2129 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2131 /* FIXME: implement */
2132 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2133 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2134 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2135 radeon_ring_write(rdev, ib->length_dw);
2138 int r600_ib_test(struct radeon_device *rdev)
2140 struct radeon_ib *ib;
2146 r = radeon_scratch_get(rdev, &scratch);
2148 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2151 WREG32(scratch, 0xCAFEDEAD);
2152 r = radeon_ib_get(rdev, &ib);
2154 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2157 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2158 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2159 ib->ptr[2] = 0xDEADBEEF;
2160 ib->ptr[3] = PACKET2(0);
2161 ib->ptr[4] = PACKET2(0);
2162 ib->ptr[5] = PACKET2(0);
2163 ib->ptr[6] = PACKET2(0);
2164 ib->ptr[7] = PACKET2(0);
2165 ib->ptr[8] = PACKET2(0);
2166 ib->ptr[9] = PACKET2(0);
2167 ib->ptr[10] = PACKET2(0);
2168 ib->ptr[11] = PACKET2(0);
2169 ib->ptr[12] = PACKET2(0);
2170 ib->ptr[13] = PACKET2(0);
2171 ib->ptr[14] = PACKET2(0);
2172 ib->ptr[15] = PACKET2(0);
2174 r = radeon_ib_schedule(rdev, ib);
2176 radeon_scratch_free(rdev, scratch);
2177 radeon_ib_free(rdev, &ib);
2178 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2181 r = radeon_fence_wait(ib->fence, false);
2183 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2186 for (i = 0; i < rdev->usec_timeout; i++) {
2187 tmp = RREG32(scratch);
2188 if (tmp == 0xDEADBEEF)
2192 if (i < rdev->usec_timeout) {
2193 DRM_INFO("ib test succeeded in %u usecs\n", i);
2195 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2199 radeon_scratch_free(rdev, scratch);
2200 radeon_ib_free(rdev, &ib);
2207 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2208 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2209 * writing to the ring and the GPU consuming, the GPU writes to the ring
2210 * and host consumes. As the host irq handler processes interrupts, it
2211 * increments the rptr. When the rptr catches up with the wptr, all the
2212 * current interrupts have been processed.
2215 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2219 /* Align ring size */
2220 rb_bufsz = drm_order(ring_size / 4);
2221 ring_size = (1 << rb_bufsz) * 4;
2222 rdev->ih.ring_size = ring_size;
2223 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2227 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2231 /* Allocate ring buffer */
2232 if (rdev->ih.ring_obj == NULL) {
2233 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2235 RADEON_GEM_DOMAIN_GTT,
2236 &rdev->ih.ring_obj);
2238 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2241 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2242 if (unlikely(r != 0))
2244 r = radeon_bo_pin(rdev->ih.ring_obj,
2245 RADEON_GEM_DOMAIN_GTT,
2246 &rdev->ih.gpu_addr);
2248 radeon_bo_unreserve(rdev->ih.ring_obj);
2249 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2252 r = radeon_bo_kmap(rdev->ih.ring_obj,
2253 (void **)&rdev->ih.ring);
2254 radeon_bo_unreserve(rdev->ih.ring_obj);
2256 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2263 static void r600_ih_ring_fini(struct radeon_device *rdev)
2266 if (rdev->ih.ring_obj) {
2267 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2268 if (likely(r == 0)) {
2269 radeon_bo_kunmap(rdev->ih.ring_obj);
2270 radeon_bo_unpin(rdev->ih.ring_obj);
2271 radeon_bo_unreserve(rdev->ih.ring_obj);
2273 radeon_bo_unref(&rdev->ih.ring_obj);
2274 rdev->ih.ring = NULL;
2275 rdev->ih.ring_obj = NULL;
2279 static void r600_rlc_stop(struct radeon_device *rdev)
2282 if (rdev->family >= CHIP_RV770) {
2283 /* r7xx asics need to soft reset RLC before halting */
2284 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2285 RREG32(SRBM_SOFT_RESET);
2287 WREG32(SRBM_SOFT_RESET, 0);
2288 RREG32(SRBM_SOFT_RESET);
2291 WREG32(RLC_CNTL, 0);
2294 static void r600_rlc_start(struct radeon_device *rdev)
2296 WREG32(RLC_CNTL, RLC_ENABLE);
2299 static int r600_rlc_init(struct radeon_device *rdev)
2302 const __be32 *fw_data;
2307 r600_rlc_stop(rdev);
2309 WREG32(RLC_HB_BASE, 0);
2310 WREG32(RLC_HB_CNTL, 0);
2311 WREG32(RLC_HB_RPTR, 0);
2312 WREG32(RLC_HB_WPTR, 0);
2313 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2314 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2315 WREG32(RLC_MC_CNTL, 0);
2316 WREG32(RLC_UCODE_CNTL, 0);
2318 fw_data = (const __be32 *)rdev->rlc_fw->data;
2319 if (rdev->family >= CHIP_RV770) {
2320 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2321 WREG32(RLC_UCODE_ADDR, i);
2322 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2325 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2326 WREG32(RLC_UCODE_ADDR, i);
2327 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2330 WREG32(RLC_UCODE_ADDR, 0);
2332 r600_rlc_start(rdev);
2337 static void r600_enable_interrupts(struct radeon_device *rdev)
2339 u32 ih_cntl = RREG32(IH_CNTL);
2340 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2342 ih_cntl |= ENABLE_INTR;
2343 ih_rb_cntl |= IH_RB_ENABLE;
2344 WREG32(IH_CNTL, ih_cntl);
2345 WREG32(IH_RB_CNTL, ih_rb_cntl);
2346 rdev->ih.enabled = true;
2349 static void r600_disable_interrupts(struct radeon_device *rdev)
2351 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2352 u32 ih_cntl = RREG32(IH_CNTL);
2354 ih_rb_cntl &= ~IH_RB_ENABLE;
2355 ih_cntl &= ~ENABLE_INTR;
2356 WREG32(IH_RB_CNTL, ih_rb_cntl);
2357 WREG32(IH_CNTL, ih_cntl);
2358 /* set rptr, wptr to 0 */
2359 WREG32(IH_RB_RPTR, 0);
2360 WREG32(IH_RB_WPTR, 0);
2361 rdev->ih.enabled = false;
2366 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2370 WREG32(CP_INT_CNTL, 0);
2371 WREG32(GRBM_INT_CNTL, 0);
2372 WREG32(DxMODE_INT_MASK, 0);
2373 if (ASIC_IS_DCE3(rdev)) {
2374 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2375 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2376 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2377 WREG32(DC_HPD1_INT_CONTROL, tmp);
2378 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2379 WREG32(DC_HPD2_INT_CONTROL, tmp);
2380 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2381 WREG32(DC_HPD3_INT_CONTROL, tmp);
2382 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383 WREG32(DC_HPD4_INT_CONTROL, tmp);
2384 if (ASIC_IS_DCE32(rdev)) {
2385 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2386 WREG32(DC_HPD5_INT_CONTROL, 0);
2387 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2388 WREG32(DC_HPD6_INT_CONTROL, 0);
2391 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2392 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2393 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2394 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2395 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2396 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2397 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2398 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2402 int r600_irq_init(struct radeon_device *rdev)
2406 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2409 ret = r600_ih_ring_alloc(rdev);
2414 r600_disable_interrupts(rdev);
2417 ret = r600_rlc_init(rdev);
2419 r600_ih_ring_fini(rdev);
2423 /* setup interrupt control */
2424 /* set dummy read address to ring address */
2425 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2426 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2427 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2428 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2430 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2431 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2432 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2433 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2435 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2436 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2438 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2439 IH_WPTR_OVERFLOW_CLEAR |
2441 /* WPTR writeback, not yet */
2442 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2443 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2444 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2446 WREG32(IH_RB_CNTL, ih_rb_cntl);
2448 /* set rptr, wptr to 0 */
2449 WREG32(IH_RB_RPTR, 0);
2450 WREG32(IH_RB_WPTR, 0);
2452 /* Default settings for IH_CNTL (disabled at first) */
2453 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2454 /* RPTR_REARM only works if msi's are enabled */
2455 if (rdev->msi_enabled)
2456 ih_cntl |= RPTR_REARM;
2459 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2461 WREG32(IH_CNTL, ih_cntl);
2463 /* force the active interrupt state to all disabled */
2464 r600_disable_interrupt_state(rdev);
2467 r600_enable_interrupts(rdev);
2472 void r600_irq_suspend(struct radeon_device *rdev)
2474 r600_disable_interrupts(rdev);
2475 r600_rlc_stop(rdev);
2478 void r600_irq_fini(struct radeon_device *rdev)
2480 r600_irq_suspend(rdev);
2481 r600_ih_ring_fini(rdev);
2484 int r600_irq_set(struct radeon_device *rdev)
2486 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2488 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2490 if (!rdev->irq.installed) {
2491 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2494 /* don't enable anything if the ih is disabled */
2495 if (!rdev->ih.enabled) {
2496 r600_disable_interrupts(rdev);
2497 /* force the active interrupt state to all disabled */
2498 r600_disable_interrupt_state(rdev);
2502 if (ASIC_IS_DCE3(rdev)) {
2503 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2504 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2505 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2506 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2507 if (ASIC_IS_DCE32(rdev)) {
2508 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2512 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2513 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2514 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2517 if (rdev->irq.sw_int) {
2518 DRM_DEBUG("r600_irq_set: sw int\n");
2519 cp_int_cntl |= RB_INT_ENABLE;
2521 if (rdev->irq.crtc_vblank_int[0]) {
2522 DRM_DEBUG("r600_irq_set: vblank 0\n");
2523 mode_int |= D1MODE_VBLANK_INT_MASK;
2525 if (rdev->irq.crtc_vblank_int[1]) {
2526 DRM_DEBUG("r600_irq_set: vblank 1\n");
2527 mode_int |= D2MODE_VBLANK_INT_MASK;
2529 if (rdev->irq.hpd[0]) {
2530 DRM_DEBUG("r600_irq_set: hpd 1\n");
2531 hpd1 |= DC_HPDx_INT_EN;
2533 if (rdev->irq.hpd[1]) {
2534 DRM_DEBUG("r600_irq_set: hpd 2\n");
2535 hpd2 |= DC_HPDx_INT_EN;
2537 if (rdev->irq.hpd[2]) {
2538 DRM_DEBUG("r600_irq_set: hpd 3\n");
2539 hpd3 |= DC_HPDx_INT_EN;
2541 if (rdev->irq.hpd[3]) {
2542 DRM_DEBUG("r600_irq_set: hpd 4\n");
2543 hpd4 |= DC_HPDx_INT_EN;
2545 if (rdev->irq.hpd[4]) {
2546 DRM_DEBUG("r600_irq_set: hpd 5\n");
2547 hpd5 |= DC_HPDx_INT_EN;
2549 if (rdev->irq.hpd[5]) {
2550 DRM_DEBUG("r600_irq_set: hpd 6\n");
2551 hpd6 |= DC_HPDx_INT_EN;
2554 WREG32(CP_INT_CNTL, cp_int_cntl);
2555 WREG32(DxMODE_INT_MASK, mode_int);
2556 if (ASIC_IS_DCE3(rdev)) {
2557 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2558 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2559 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2560 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2561 if (ASIC_IS_DCE32(rdev)) {
2562 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2563 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2566 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2567 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2568 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2574 static inline void r600_irq_ack(struct radeon_device *rdev,
2577 u32 *disp_int_cont2)
2581 if (ASIC_IS_DCE3(rdev)) {
2582 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2583 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2584 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2586 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2587 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2588 *disp_int_cont2 = 0;
2591 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2592 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2593 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2594 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2595 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2596 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2597 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2598 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2599 if (*disp_int & DC_HPD1_INTERRUPT) {
2600 if (ASIC_IS_DCE3(rdev)) {
2601 tmp = RREG32(DC_HPD1_INT_CONTROL);
2602 tmp |= DC_HPDx_INT_ACK;
2603 WREG32(DC_HPD1_INT_CONTROL, tmp);
2605 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2606 tmp |= DC_HPDx_INT_ACK;
2607 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2610 if (*disp_int & DC_HPD2_INTERRUPT) {
2611 if (ASIC_IS_DCE3(rdev)) {
2612 tmp = RREG32(DC_HPD2_INT_CONTROL);
2613 tmp |= DC_HPDx_INT_ACK;
2614 WREG32(DC_HPD2_INT_CONTROL, tmp);
2616 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2617 tmp |= DC_HPDx_INT_ACK;
2618 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2621 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2622 if (ASIC_IS_DCE3(rdev)) {
2623 tmp = RREG32(DC_HPD3_INT_CONTROL);
2624 tmp |= DC_HPDx_INT_ACK;
2625 WREG32(DC_HPD3_INT_CONTROL, tmp);
2627 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2628 tmp |= DC_HPDx_INT_ACK;
2629 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2632 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2633 tmp = RREG32(DC_HPD4_INT_CONTROL);
2634 tmp |= DC_HPDx_INT_ACK;
2635 WREG32(DC_HPD4_INT_CONTROL, tmp);
2637 if (ASIC_IS_DCE32(rdev)) {
2638 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2639 tmp = RREG32(DC_HPD5_INT_CONTROL);
2640 tmp |= DC_HPDx_INT_ACK;
2641 WREG32(DC_HPD5_INT_CONTROL, tmp);
2643 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2644 tmp = RREG32(DC_HPD5_INT_CONTROL);
2645 tmp |= DC_HPDx_INT_ACK;
2646 WREG32(DC_HPD6_INT_CONTROL, tmp);
2651 void r600_irq_disable(struct radeon_device *rdev)
2653 u32 disp_int, disp_int_cont, disp_int_cont2;
2655 r600_disable_interrupts(rdev);
2656 /* Wait and acknowledge irq */
2658 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2659 r600_disable_interrupt_state(rdev);
2662 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2666 /* XXX use writeback */
2667 wptr = RREG32(IH_RB_WPTR);
2669 if (wptr & RB_OVERFLOW) {
2670 /* When a ring buffer overflow happen start parsing interrupt
2671 * from the last not overwritten vector (wptr + 16). Hopefully
2672 * this should allow us to catchup.
2674 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2675 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2676 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2677 tmp = RREG32(IH_RB_CNTL);
2678 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2679 WREG32(IH_RB_CNTL, tmp);
2681 return (wptr & rdev->ih.ptr_mask);
2685 * Each IV ring entry is 128 bits:
2686 * [7:0] - interrupt source id
2688 * [59:32] - interrupt source data
2689 * [127:60] - reserved
2691 * The basic interrupt vector entries
2692 * are decoded as follows:
2693 * src_id src_data description
2698 * 19 0 FP Hot plug detection A
2699 * 19 1 FP Hot plug detection B
2700 * 19 2 DAC A auto-detection
2701 * 19 3 DAC B auto-detection
2705 * 181 - EOP Interrupt
2708 * Note, these are based on r600 and may need to be
2709 * adjusted or added to on newer asics
2712 int r600_irq_process(struct radeon_device *rdev)
2714 u32 wptr = r600_get_ih_wptr(rdev);
2715 u32 rptr = rdev->ih.rptr;
2716 u32 src_id, src_data;
2717 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2718 unsigned long flags;
2719 bool queue_hotplug = false;
2721 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2722 if (!rdev->ih.enabled)
2725 spin_lock_irqsave(&rdev->ih.lock, flags);
2728 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2731 if (rdev->shutdown) {
2732 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2737 /* display interrupts */
2738 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2740 rdev->ih.wptr = wptr;
2741 while (rptr != wptr) {
2742 /* wptr/rptr are in bytes! */
2743 ring_index = rptr / 4;
2744 src_id = rdev->ih.ring[ring_index] & 0xff;
2745 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2748 case 1: /* D1 vblank/vline */
2750 case 0: /* D1 vblank */
2751 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2752 drm_handle_vblank(rdev->ddev, 0);
2753 wake_up(&rdev->irq.vblank_queue);
2754 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2755 DRM_DEBUG("IH: D1 vblank\n");
2758 case 1: /* D1 vline */
2759 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2760 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2761 DRM_DEBUG("IH: D1 vline\n");
2765 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2769 case 5: /* D2 vblank/vline */
2771 case 0: /* D2 vblank */
2772 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2773 drm_handle_vblank(rdev->ddev, 1);
2774 wake_up(&rdev->irq.vblank_queue);
2775 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2776 DRM_DEBUG("IH: D2 vblank\n");
2779 case 1: /* D1 vline */
2780 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2781 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2782 DRM_DEBUG("IH: D2 vline\n");
2786 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2790 case 19: /* HPD/DAC hotplug */
2793 if (disp_int & DC_HPD1_INTERRUPT) {
2794 disp_int &= ~DC_HPD1_INTERRUPT;
2795 queue_hotplug = true;
2796 DRM_DEBUG("IH: HPD1\n");
2800 if (disp_int & DC_HPD2_INTERRUPT) {
2801 disp_int &= ~DC_HPD2_INTERRUPT;
2802 queue_hotplug = true;
2803 DRM_DEBUG("IH: HPD2\n");
2807 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2808 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2809 queue_hotplug = true;
2810 DRM_DEBUG("IH: HPD3\n");
2814 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2815 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2816 queue_hotplug = true;
2817 DRM_DEBUG("IH: HPD4\n");
2821 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2822 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2823 queue_hotplug = true;
2824 DRM_DEBUG("IH: HPD5\n");
2828 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2829 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2830 queue_hotplug = true;
2831 DRM_DEBUG("IH: HPD6\n");
2835 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2839 case 176: /* CP_INT in ring buffer */
2840 case 177: /* CP_INT in IB1 */
2841 case 178: /* CP_INT in IB2 */
2842 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2843 radeon_fence_process(rdev);
2845 case 181: /* CP EOP event */
2846 DRM_DEBUG("IH: CP EOP\n");
2849 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2853 /* wptr/rptr are in bytes! */
2855 rptr &= rdev->ih.ptr_mask;
2857 /* make sure wptr hasn't changed while processing */
2858 wptr = r600_get_ih_wptr(rdev);
2859 if (wptr != rdev->ih.wptr)
2862 queue_work(rdev->wq, &rdev->hotplug_work);
2863 rdev->ih.rptr = rptr;
2864 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2865 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2872 #if defined(CONFIG_DEBUG_FS)
2874 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2876 struct drm_info_node *node = (struct drm_info_node *) m->private;
2877 struct drm_device *dev = node->minor->dev;
2878 struct radeon_device *rdev = dev->dev_private;
2879 unsigned count, i, j;
2881 radeon_ring_free_size(rdev);
2882 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2883 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2884 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2885 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2886 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2887 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2888 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2889 seq_printf(m, "%u dwords in ring\n", count);
2891 for (j = 0; j <= count; j++) {
2892 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2893 i = (i + 1) & rdev->cp.ptr_mask;
2898 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2900 struct drm_info_node *node = (struct drm_info_node *) m->private;
2901 struct drm_device *dev = node->minor->dev;
2902 struct radeon_device *rdev = dev->dev_private;
2904 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2905 DREG32_SYS(m, rdev, VM_L2_STATUS);
2909 static struct drm_info_list r600_mc_info_list[] = {
2910 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2911 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2915 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2917 #if defined(CONFIG_DEBUG_FS)
2918 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2925 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2926 * rdev: radeon device structure
2927 * bo: buffer object struct which userspace is waiting for idle
2929 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2930 * through ring buffer, this leads to corruption in rendering, see
2931 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2932 * directly perform HDP flush by writing register through MMIO.
2934 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2936 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);