2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_mode.h"
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
80 bool connected = false;
82 if (ASIC_IS_DCE3(rdev)) {
85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134 enum radeon_hpd_id hpd)
137 bool connected = r600_hpd_sense(rdev, hpd);
139 if (ASIC_IS_DCE3(rdev)) {
142 tmp = RREG32(DC_HPD1_INT_CONTROL);
144 tmp &= ~DC_HPDx_INT_POLARITY;
146 tmp |= DC_HPDx_INT_POLARITY;
147 WREG32(DC_HPD1_INT_CONTROL, tmp);
150 tmp = RREG32(DC_HPD2_INT_CONTROL);
152 tmp &= ~DC_HPDx_INT_POLARITY;
154 tmp |= DC_HPDx_INT_POLARITY;
155 WREG32(DC_HPD2_INT_CONTROL, tmp);
158 tmp = RREG32(DC_HPD3_INT_CONTROL);
160 tmp &= ~DC_HPDx_INT_POLARITY;
162 tmp |= DC_HPDx_INT_POLARITY;
163 WREG32(DC_HPD3_INT_CONTROL, tmp);
166 tmp = RREG32(DC_HPD4_INT_CONTROL);
168 tmp &= ~DC_HPDx_INT_POLARITY;
170 tmp |= DC_HPDx_INT_POLARITY;
171 WREG32(DC_HPD4_INT_CONTROL, tmp);
174 tmp = RREG32(DC_HPD5_INT_CONTROL);
176 tmp &= ~DC_HPDx_INT_POLARITY;
178 tmp |= DC_HPDx_INT_POLARITY;
179 WREG32(DC_HPD5_INT_CONTROL, tmp);
183 tmp = RREG32(DC_HPD6_INT_CONTROL);
185 tmp &= ~DC_HPDx_INT_POLARITY;
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD6_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
225 void r600_hpd_init(struct radeon_device *rdev)
227 struct drm_device *dev = rdev->ddev;
228 struct drm_connector *connector;
230 if (ASIC_IS_DCE3(rdev)) {
231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev))
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
239 WREG32(DC_HPD1_CONTROL, tmp);
240 rdev->irq.hpd[0] = true;
243 WREG32(DC_HPD2_CONTROL, tmp);
244 rdev->irq.hpd[1] = true;
247 WREG32(DC_HPD3_CONTROL, tmp);
248 rdev->irq.hpd[2] = true;
251 WREG32(DC_HPD4_CONTROL, tmp);
252 rdev->irq.hpd[3] = true;
256 WREG32(DC_HPD5_CONTROL, tmp);
257 rdev->irq.hpd[4] = true;
260 WREG32(DC_HPD6_CONTROL, tmp);
261 rdev->irq.hpd[5] = true;
268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270 switch (radeon_connector->hpd.hpd) {
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273 rdev->irq.hpd[0] = true;
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277 rdev->irq.hpd[1] = true;
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281 rdev->irq.hpd[2] = true;
288 if (rdev->irq.installed)
292 void r600_hpd_fini(struct radeon_device *rdev)
294 struct drm_device *dev = rdev->ddev;
295 struct drm_connector *connector;
297 if (ASIC_IS_DCE3(rdev)) {
298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300 switch (radeon_connector->hpd.hpd) {
302 WREG32(DC_HPD1_CONTROL, 0);
303 rdev->irq.hpd[0] = false;
306 WREG32(DC_HPD2_CONTROL, 0);
307 rdev->irq.hpd[1] = false;
310 WREG32(DC_HPD3_CONTROL, 0);
311 rdev->irq.hpd[2] = false;
314 WREG32(DC_HPD4_CONTROL, 0);
315 rdev->irq.hpd[3] = false;
319 WREG32(DC_HPD5_CONTROL, 0);
320 rdev->irq.hpd[4] = false;
323 WREG32(DC_HPD6_CONTROL, 0);
324 rdev->irq.hpd[5] = false;
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
335 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336 rdev->irq.hpd[0] = false;
339 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340 rdev->irq.hpd[1] = false;
343 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344 rdev->irq.hpd[2] = false;
356 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
361 /* flush hdp cache so updates hit vram */
362 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
364 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
365 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
366 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
367 for (i = 0; i < rdev->usec_timeout; i++) {
369 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
370 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
372 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
382 int r600_pcie_gart_init(struct radeon_device *rdev)
386 if (rdev->gart.table.vram.robj) {
387 WARN(1, "R600 PCIE GART already initialized.\n");
390 /* Initialize common gart structure */
391 r = radeon_gart_init(rdev);
394 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
395 return radeon_gart_table_vram_alloc(rdev);
398 int r600_pcie_gart_enable(struct radeon_device *rdev)
403 if (rdev->gart.table.vram.robj == NULL) {
404 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
407 r = radeon_gart_table_vram_pin(rdev);
410 radeon_gart_restore(rdev);
413 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
414 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
415 EFFECTIVE_L2_QUEUE_SIZE(7));
416 WREG32(VM_L2_CNTL2, 0);
417 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
418 /* Setup TLB control */
419 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
420 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
421 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
422 ENABLE_WAIT_L2_QUERY;
423 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
424 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
425 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
426 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
427 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
428 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
429 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
430 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
431 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
434 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
436 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
437 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
438 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
439 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
440 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
441 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
442 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
443 (u32)(rdev->dummy_page.addr >> 12));
444 for (i = 1; i < 7; i++)
445 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
447 r600_pcie_gart_tlb_flush(rdev);
448 rdev->gart.ready = true;
452 void r600_pcie_gart_disable(struct radeon_device *rdev)
457 /* Disable all tables */
458 for (i = 0; i < 7; i++)
459 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
461 /* Disable L2 cache */
462 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
463 EFFECTIVE_L2_QUEUE_SIZE(7));
464 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
465 /* Setup L1 TLB control */
466 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
467 ENABLE_WAIT_L2_QUERY;
468 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
469 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
470 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
471 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
472 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
473 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
474 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
475 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
476 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
482 if (rdev->gart.table.vram.robj) {
483 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
484 if (likely(r == 0)) {
485 radeon_bo_kunmap(rdev->gart.table.vram.robj);
486 radeon_bo_unpin(rdev->gart.table.vram.robj);
487 radeon_bo_unreserve(rdev->gart.table.vram.robj);
492 void r600_pcie_gart_fini(struct radeon_device *rdev)
494 r600_pcie_gart_disable(rdev);
495 radeon_gart_table_vram_free(rdev);
496 radeon_gart_fini(rdev);
499 void r600_agp_enable(struct radeon_device *rdev)
505 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
506 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
507 EFFECTIVE_L2_QUEUE_SIZE(7));
508 WREG32(VM_L2_CNTL2, 0);
509 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
510 /* Setup TLB control */
511 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
512 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
513 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
514 ENABLE_WAIT_L2_QUERY;
515 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
516 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
517 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
518 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
519 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
520 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
521 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
522 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
523 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
526 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
528 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
529 for (i = 0; i < 7; i++)
530 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
533 int r600_mc_wait_for_idle(struct radeon_device *rdev)
538 for (i = 0; i < rdev->usec_timeout; i++) {
540 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
548 static void r600_mc_program(struct radeon_device *rdev)
550 struct rv515_mc_save save;
555 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
556 WREG32((0x2c14 + j), 0x00000000);
557 WREG32((0x2c18 + j), 0x00000000);
558 WREG32((0x2c1c + j), 0x00000000);
559 WREG32((0x2c20 + j), 0x00000000);
560 WREG32((0x2c24 + j), 0x00000000);
562 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
564 rv515_mc_stop(rdev, &save);
565 if (r600_mc_wait_for_idle(rdev)) {
566 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
568 /* Lockout access through VGA aperture (doesn't exist before R600) */
569 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
570 /* Update configuration */
571 if (rdev->flags & RADEON_IS_AGP) {
572 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
573 /* VRAM before AGP */
574 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
575 rdev->mc.vram_start >> 12);
576 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
577 rdev->mc.gtt_end >> 12);
580 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
581 rdev->mc.gtt_start >> 12);
582 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
583 rdev->mc.vram_end >> 12);
586 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
587 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
589 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
590 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
591 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
592 WREG32(MC_VM_FB_LOCATION, tmp);
593 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
594 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
595 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
596 if (rdev->flags & RADEON_IS_AGP) {
597 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
598 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
599 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
601 WREG32(MC_VM_AGP_BASE, 0);
602 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
603 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
605 if (r600_mc_wait_for_idle(rdev)) {
606 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
608 rv515_mc_resume(rdev, &save);
609 /* we need to own VRAM, so turn off the VGA renderer here
610 * to stop it overwriting our objects */
611 rv515_vga_render_disable(rdev);
615 * r600_vram_gtt_location - try to find VRAM & GTT location
616 * @rdev: radeon device structure holding all necessary informations
617 * @mc: memory controller structure holding memory informations
619 * Function will place try to place VRAM at same place as in CPU (PCI)
620 * address space as some GPU seems to have issue when we reprogram at
621 * different address space.
623 * If there is not enough space to fit the unvisible VRAM after the
624 * aperture then we limit the VRAM size to the aperture.
626 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
627 * them to be in one from GPU point of view so that we can program GPU to
628 * catch access outside them (weird GPU policy see ??).
630 * This function will never fails, worst case are limiting VRAM or GTT.
632 * Note: GTT start, end, size should be initialized before calling this
633 * function on AGP platform.
635 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
637 u64 size_bf, size_af;
639 if (mc->mc_vram_size > 0xE0000000) {
640 /* leave room for at least 512M GTT */
641 dev_warn(rdev->dev, "limiting VRAM\n");
642 mc->real_vram_size = 0xE0000000;
643 mc->mc_vram_size = 0xE0000000;
645 if (rdev->flags & RADEON_IS_AGP) {
646 size_bf = mc->gtt_start;
647 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
648 if (size_bf > size_af) {
649 if (mc->mc_vram_size > size_bf) {
650 dev_warn(rdev->dev, "limiting VRAM\n");
651 mc->real_vram_size = size_bf;
652 mc->mc_vram_size = size_bf;
654 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
656 if (mc->mc_vram_size > size_af) {
657 dev_warn(rdev->dev, "limiting VRAM\n");
658 mc->real_vram_size = size_af;
659 mc->mc_vram_size = size_af;
661 mc->vram_start = mc->gtt_end;
663 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
664 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
665 mc->mc_vram_size >> 20, mc->vram_start,
666 mc->vram_end, mc->real_vram_size >> 20);
669 if (rdev->flags & RADEON_IS_IGP)
670 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
671 radeon_vram_location(rdev, &rdev->mc, base);
672 radeon_gtt_location(rdev, mc);
676 int r600_mc_init(struct radeon_device *rdev)
680 int chansize, numchan;
682 /* Get VRAM informations */
683 rdev->mc.vram_is_ddr = true;
684 tmp = RREG32(RAMCFG);
685 if (tmp & CHANSIZE_OVERRIDE) {
687 } else if (tmp & CHANSIZE_MASK) {
693 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
708 rdev->mc.vram_width = numchan * chansize;
709 /* Could aper size report 0 ? */
710 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
711 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
712 /* Setup GPU memory space */
713 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
714 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
715 /* FIXME remove this once we support unmappable VRAM */
716 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
717 rdev->mc.mc_vram_size = rdev->mc.aper_size;
718 rdev->mc.real_vram_size = rdev->mc.aper_size;
720 r600_vram_gtt_location(rdev, &rdev->mc);
721 /* FIXME: we should enforce default clock in case GPU is not in
724 a.full = rfixed_const(100);
725 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
726 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
727 if (rdev->flags & RADEON_IS_IGP)
728 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
732 /* We doesn't check that the GPU really needs a reset we simply do the
733 * reset, it's up to the caller to determine if the GPU needs one. We
734 * might add an helper function to check that.
736 int r600_gpu_soft_reset(struct radeon_device *rdev)
738 struct rv515_mc_save save;
739 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
740 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
741 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
742 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
743 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
744 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
745 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
746 S_008010_GUI_ACTIVE(1);
747 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
748 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
749 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
750 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
751 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
752 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
753 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
754 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
758 dev_info(rdev->dev, "GPU softreset \n");
759 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
760 RREG32(R_008010_GRBM_STATUS));
761 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
762 RREG32(R_008014_GRBM_STATUS2));
763 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
764 RREG32(R_000E50_SRBM_STATUS));
765 rv515_mc_stop(rdev, &save);
766 if (r600_mc_wait_for_idle(rdev)) {
767 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
769 /* Disable CP parsing/prefetching */
770 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
771 /* Check if any of the rendering block is busy and reset it */
772 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
773 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
774 tmp = S_008020_SOFT_RESET_CR(1) |
775 S_008020_SOFT_RESET_DB(1) |
776 S_008020_SOFT_RESET_CB(1) |
777 S_008020_SOFT_RESET_PA(1) |
778 S_008020_SOFT_RESET_SC(1) |
779 S_008020_SOFT_RESET_SMX(1) |
780 S_008020_SOFT_RESET_SPI(1) |
781 S_008020_SOFT_RESET_SX(1) |
782 S_008020_SOFT_RESET_SH(1) |
783 S_008020_SOFT_RESET_TC(1) |
784 S_008020_SOFT_RESET_TA(1) |
785 S_008020_SOFT_RESET_VC(1) |
786 S_008020_SOFT_RESET_VGT(1);
787 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
788 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
789 (void)RREG32(R_008020_GRBM_SOFT_RESET);
791 WREG32(R_008020_GRBM_SOFT_RESET, 0);
792 (void)RREG32(R_008020_GRBM_SOFT_RESET);
794 /* Reset CP (we always reset CP) */
795 tmp = S_008020_SOFT_RESET_CP(1);
796 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
797 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
798 (void)RREG32(R_008020_GRBM_SOFT_RESET);
800 WREG32(R_008020_GRBM_SOFT_RESET, 0);
801 (void)RREG32(R_008020_GRBM_SOFT_RESET);
802 /* Reset others GPU block if necessary */
803 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
804 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
805 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
806 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
807 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
808 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
809 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
810 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
811 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
812 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
813 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
814 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
815 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
816 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
817 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
818 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
819 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
820 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
821 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
822 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
823 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
824 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
825 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
826 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
827 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
828 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
829 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
831 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
832 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
833 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
836 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
837 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
838 /* Wait a little for things to settle down */
840 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
841 RREG32(R_008010_GRBM_STATUS));
842 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
843 RREG32(R_008014_GRBM_STATUS2));
844 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
845 RREG32(R_000E50_SRBM_STATUS));
846 /* After reset we need to reinit the asic as GPU often endup in an
849 atom_asic_init(rdev->mode_info.atom_context);
850 rv515_mc_resume(rdev, &save);
854 int r600_gpu_reset(struct radeon_device *rdev)
856 return r600_gpu_soft_reset(rdev);
859 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
861 u32 backend_disable_mask)
864 u32 enabled_backends_mask;
865 u32 enabled_backends_count;
867 u32 swizzle_pipe[R6XX_MAX_PIPES];
871 if (num_tile_pipes > R6XX_MAX_PIPES)
872 num_tile_pipes = R6XX_MAX_PIPES;
873 if (num_tile_pipes < 1)
875 if (num_backends > R6XX_MAX_BACKENDS)
876 num_backends = R6XX_MAX_BACKENDS;
877 if (num_backends < 1)
880 enabled_backends_mask = 0;
881 enabled_backends_count = 0;
882 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
883 if (((backend_disable_mask >> i) & 1) == 0) {
884 enabled_backends_mask |= (1 << i);
885 ++enabled_backends_count;
887 if (enabled_backends_count == num_backends)
891 if (enabled_backends_count == 0) {
892 enabled_backends_mask = 1;
893 enabled_backends_count = 1;
896 if (enabled_backends_count != num_backends)
897 num_backends = enabled_backends_count;
899 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
900 switch (num_tile_pipes) {
956 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
957 while (((1 << cur_backend) & enabled_backends_mask) == 0)
958 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
960 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
962 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
968 int r600_count_pipe_bits(uint32_t val)
972 for (i = 0; i < 32; i++) {
979 void r600_gpu_init(struct radeon_device *rdev)
986 u32 sq_gpr_resource_mgmt_1 = 0;
987 u32 sq_gpr_resource_mgmt_2 = 0;
988 u32 sq_thread_resource_mgmt = 0;
989 u32 sq_stack_resource_mgmt_1 = 0;
990 u32 sq_stack_resource_mgmt_2 = 0;
992 /* FIXME: implement */
993 switch (rdev->family) {
995 rdev->config.r600.max_pipes = 4;
996 rdev->config.r600.max_tile_pipes = 8;
997 rdev->config.r600.max_simds = 4;
998 rdev->config.r600.max_backends = 4;
999 rdev->config.r600.max_gprs = 256;
1000 rdev->config.r600.max_threads = 192;
1001 rdev->config.r600.max_stack_entries = 256;
1002 rdev->config.r600.max_hw_contexts = 8;
1003 rdev->config.r600.max_gs_threads = 16;
1004 rdev->config.r600.sx_max_export_size = 128;
1005 rdev->config.r600.sx_max_export_pos_size = 16;
1006 rdev->config.r600.sx_max_export_smx_size = 128;
1007 rdev->config.r600.sq_num_cf_insts = 2;
1011 rdev->config.r600.max_pipes = 2;
1012 rdev->config.r600.max_tile_pipes = 2;
1013 rdev->config.r600.max_simds = 3;
1014 rdev->config.r600.max_backends = 1;
1015 rdev->config.r600.max_gprs = 128;
1016 rdev->config.r600.max_threads = 192;
1017 rdev->config.r600.max_stack_entries = 128;
1018 rdev->config.r600.max_hw_contexts = 8;
1019 rdev->config.r600.max_gs_threads = 4;
1020 rdev->config.r600.sx_max_export_size = 128;
1021 rdev->config.r600.sx_max_export_pos_size = 16;
1022 rdev->config.r600.sx_max_export_smx_size = 128;
1023 rdev->config.r600.sq_num_cf_insts = 2;
1029 rdev->config.r600.max_pipes = 1;
1030 rdev->config.r600.max_tile_pipes = 1;
1031 rdev->config.r600.max_simds = 2;
1032 rdev->config.r600.max_backends = 1;
1033 rdev->config.r600.max_gprs = 128;
1034 rdev->config.r600.max_threads = 192;
1035 rdev->config.r600.max_stack_entries = 128;
1036 rdev->config.r600.max_hw_contexts = 4;
1037 rdev->config.r600.max_gs_threads = 4;
1038 rdev->config.r600.sx_max_export_size = 128;
1039 rdev->config.r600.sx_max_export_pos_size = 16;
1040 rdev->config.r600.sx_max_export_smx_size = 128;
1041 rdev->config.r600.sq_num_cf_insts = 1;
1044 rdev->config.r600.max_pipes = 4;
1045 rdev->config.r600.max_tile_pipes = 4;
1046 rdev->config.r600.max_simds = 4;
1047 rdev->config.r600.max_backends = 4;
1048 rdev->config.r600.max_gprs = 192;
1049 rdev->config.r600.max_threads = 192;
1050 rdev->config.r600.max_stack_entries = 256;
1051 rdev->config.r600.max_hw_contexts = 8;
1052 rdev->config.r600.max_gs_threads = 16;
1053 rdev->config.r600.sx_max_export_size = 128;
1054 rdev->config.r600.sx_max_export_pos_size = 16;
1055 rdev->config.r600.sx_max_export_smx_size = 128;
1056 rdev->config.r600.sq_num_cf_insts = 2;
1062 /* Initialize HDP */
1063 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1064 WREG32((0x2c14 + j), 0x00000000);
1065 WREG32((0x2c18 + j), 0x00000000);
1066 WREG32((0x2c1c + j), 0x00000000);
1067 WREG32((0x2c20 + j), 0x00000000);
1068 WREG32((0x2c24 + j), 0x00000000);
1071 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1075 ramcfg = RREG32(RAMCFG);
1076 switch (rdev->config.r600.max_tile_pipes) {
1078 tiling_config |= PIPE_TILING(0);
1079 rdev->config.r600.tiling_npipes = 1;
1082 tiling_config |= PIPE_TILING(1);
1083 rdev->config.r600.tiling_npipes = 2;
1086 tiling_config |= PIPE_TILING(2);
1087 rdev->config.r600.tiling_npipes = 4;
1090 tiling_config |= PIPE_TILING(3);
1091 rdev->config.r600.tiling_npipes = 8;
1096 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1097 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1098 tiling_config |= GROUP_SIZE(0);
1099 rdev->config.r600.tiling_group_size = 256;
1100 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1102 tiling_config |= ROW_TILING(3);
1103 tiling_config |= SAMPLE_SPLIT(3);
1105 tiling_config |= ROW_TILING(tmp);
1106 tiling_config |= SAMPLE_SPLIT(tmp);
1108 tiling_config |= BANK_SWAPS(1);
1109 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1110 rdev->config.r600.max_backends,
1111 (0xff << rdev->config.r600.max_backends) & 0xff);
1112 tiling_config |= BACKEND_MAP(tmp);
1113 WREG32(GB_TILING_CONFIG, tiling_config);
1114 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1115 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1117 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1118 WREG32(CC_RB_BACKEND_DISABLE, tmp);
1121 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1122 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1123 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1124 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1126 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1127 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1128 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1130 /* Setup some CP states */
1131 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1132 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1134 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1135 SYNC_WALKER | SYNC_ALIGNER));
1136 /* Setup various GPU states */
1137 if (rdev->family == CHIP_RV670)
1138 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1140 tmp = RREG32(SX_DEBUG_1);
1141 tmp |= SMX_EVENT_RELEASE;
1142 if ((rdev->family > CHIP_R600))
1143 tmp |= ENABLE_NEW_SMX_ADDRESS;
1144 WREG32(SX_DEBUG_1, tmp);
1146 if (((rdev->family) == CHIP_R600) ||
1147 ((rdev->family) == CHIP_RV630) ||
1148 ((rdev->family) == CHIP_RV610) ||
1149 ((rdev->family) == CHIP_RV620) ||
1150 ((rdev->family) == CHIP_RS780) ||
1151 ((rdev->family) == CHIP_RS880)) {
1152 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1154 WREG32(DB_DEBUG, 0);
1156 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1157 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1159 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1160 WREG32(VGT_NUM_INSTANCES, 0);
1162 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1163 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1165 tmp = RREG32(SQ_MS_FIFO_SIZES);
1166 if (((rdev->family) == CHIP_RV610) ||
1167 ((rdev->family) == CHIP_RV620) ||
1168 ((rdev->family) == CHIP_RS780) ||
1169 ((rdev->family) == CHIP_RS880)) {
1170 tmp = (CACHE_FIFO_SIZE(0xa) |
1171 FETCH_FIFO_HIWATER(0xa) |
1172 DONE_FIFO_HIWATER(0xe0) |
1173 ALU_UPDATE_FIFO_HIWATER(0x8));
1174 } else if (((rdev->family) == CHIP_R600) ||
1175 ((rdev->family) == CHIP_RV630)) {
1176 tmp &= ~DONE_FIFO_HIWATER(0xff);
1177 tmp |= DONE_FIFO_HIWATER(0x4);
1179 WREG32(SQ_MS_FIFO_SIZES, tmp);
1181 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1182 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1184 sq_config = RREG32(SQ_CONFIG);
1185 sq_config &= ~(PS_PRIO(3) |
1189 sq_config |= (DX9_CONSTS |
1196 if ((rdev->family) == CHIP_R600) {
1197 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1199 NUM_CLAUSE_TEMP_GPRS(4));
1200 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1202 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1203 NUM_VS_THREADS(48) |
1206 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1207 NUM_VS_STACK_ENTRIES(128));
1208 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1209 NUM_ES_STACK_ENTRIES(0));
1210 } else if (((rdev->family) == CHIP_RV610) ||
1211 ((rdev->family) == CHIP_RV620) ||
1212 ((rdev->family) == CHIP_RS780) ||
1213 ((rdev->family) == CHIP_RS880)) {
1214 /* no vertex cache */
1215 sq_config &= ~VC_ENABLE;
1217 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1219 NUM_CLAUSE_TEMP_GPRS(2));
1220 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1222 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1223 NUM_VS_THREADS(78) |
1225 NUM_ES_THREADS(31));
1226 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1227 NUM_VS_STACK_ENTRIES(40));
1228 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1229 NUM_ES_STACK_ENTRIES(16));
1230 } else if (((rdev->family) == CHIP_RV630) ||
1231 ((rdev->family) == CHIP_RV635)) {
1232 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1234 NUM_CLAUSE_TEMP_GPRS(2));
1235 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1237 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1238 NUM_VS_THREADS(78) |
1240 NUM_ES_THREADS(31));
1241 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1242 NUM_VS_STACK_ENTRIES(40));
1243 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1244 NUM_ES_STACK_ENTRIES(16));
1245 } else if ((rdev->family) == CHIP_RV670) {
1246 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1248 NUM_CLAUSE_TEMP_GPRS(2));
1249 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1251 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1252 NUM_VS_THREADS(78) |
1254 NUM_ES_THREADS(31));
1255 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1256 NUM_VS_STACK_ENTRIES(64));
1257 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1258 NUM_ES_STACK_ENTRIES(64));
1261 WREG32(SQ_CONFIG, sq_config);
1262 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1263 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1264 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1265 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1266 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1268 if (((rdev->family) == CHIP_RV610) ||
1269 ((rdev->family) == CHIP_RV620) ||
1270 ((rdev->family) == CHIP_RS780) ||
1271 ((rdev->family) == CHIP_RS880)) {
1272 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1274 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1277 /* More default values. 2D/3D driver should adjust as needed */
1278 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1279 S1_X(0x4) | S1_Y(0xc)));
1280 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1281 S1_X(0x2) | S1_Y(0x2) |
1282 S2_X(0xa) | S2_Y(0x6) |
1283 S3_X(0x6) | S3_Y(0xa)));
1284 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1285 S1_X(0x4) | S1_Y(0xc) |
1286 S2_X(0x1) | S2_Y(0x6) |
1287 S3_X(0xa) | S3_Y(0xe)));
1288 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1289 S5_X(0x0) | S5_Y(0x0) |
1290 S6_X(0xb) | S6_Y(0x4) |
1291 S7_X(0x7) | S7_Y(0x8)));
1293 WREG32(VGT_STRMOUT_EN, 0);
1294 tmp = rdev->config.r600.max_pipes * 16;
1295 switch (rdev->family) {
1311 WREG32(VGT_ES_PER_GS, 128);
1312 WREG32(VGT_GS_PER_ES, tmp);
1313 WREG32(VGT_GS_PER_VS, 2);
1314 WREG32(VGT_GS_VERTEX_REUSE, 16);
1316 /* more default values. 2D/3D driver should adjust as needed */
1317 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1318 WREG32(VGT_STRMOUT_EN, 0);
1320 WREG32(PA_SC_MODE_CNTL, 0);
1321 WREG32(PA_SC_AA_CONFIG, 0);
1322 WREG32(PA_SC_LINE_STIPPLE, 0);
1323 WREG32(SPI_INPUT_Z, 0);
1324 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1325 WREG32(CB_COLOR7_FRAG, 0);
1327 /* Clear render buffer base addresses */
1328 WREG32(CB_COLOR0_BASE, 0);
1329 WREG32(CB_COLOR1_BASE, 0);
1330 WREG32(CB_COLOR2_BASE, 0);
1331 WREG32(CB_COLOR3_BASE, 0);
1332 WREG32(CB_COLOR4_BASE, 0);
1333 WREG32(CB_COLOR5_BASE, 0);
1334 WREG32(CB_COLOR6_BASE, 0);
1335 WREG32(CB_COLOR7_BASE, 0);
1336 WREG32(CB_COLOR7_FRAG, 0);
1338 switch (rdev->family) {
1343 tmp = TC_L2_SIZE(8);
1347 tmp = TC_L2_SIZE(4);
1350 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1353 tmp = TC_L2_SIZE(0);
1356 WREG32(TC_CNTL, tmp);
1358 tmp = RREG32(HDP_HOST_PATH_CNTL);
1359 WREG32(HDP_HOST_PATH_CNTL, tmp);
1361 tmp = RREG32(ARB_POP);
1362 tmp |= ENABLE_TC128;
1363 WREG32(ARB_POP, tmp);
1365 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1366 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1368 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1373 * Indirect registers accessor
1375 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1379 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1380 (void)RREG32(PCIE_PORT_INDEX);
1381 r = RREG32(PCIE_PORT_DATA);
1385 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1387 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1388 (void)RREG32(PCIE_PORT_INDEX);
1389 WREG32(PCIE_PORT_DATA, (v));
1390 (void)RREG32(PCIE_PORT_DATA);
1396 void r600_cp_stop(struct radeon_device *rdev)
1398 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1401 int r600_init_microcode(struct radeon_device *rdev)
1403 struct platform_device *pdev;
1404 const char *chip_name;
1405 const char *rlc_chip_name;
1406 size_t pfp_req_size, me_req_size, rlc_req_size;
1412 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1415 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1419 switch (rdev->family) {
1422 rlc_chip_name = "R600";
1425 chip_name = "RV610";
1426 rlc_chip_name = "R600";
1429 chip_name = "RV630";
1430 rlc_chip_name = "R600";
1433 chip_name = "RV620";
1434 rlc_chip_name = "R600";
1437 chip_name = "RV635";
1438 rlc_chip_name = "R600";
1441 chip_name = "RV670";
1442 rlc_chip_name = "R600";
1446 chip_name = "RS780";
1447 rlc_chip_name = "R600";
1450 chip_name = "RV770";
1451 rlc_chip_name = "R700";
1455 chip_name = "RV730";
1456 rlc_chip_name = "R700";
1459 chip_name = "RV710";
1460 rlc_chip_name = "R700";
1465 if (rdev->family >= CHIP_RV770) {
1466 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1467 me_req_size = R700_PM4_UCODE_SIZE * 4;
1468 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1470 pfp_req_size = PFP_UCODE_SIZE * 4;
1471 me_req_size = PM4_UCODE_SIZE * 12;
1472 rlc_req_size = RLC_UCODE_SIZE * 4;
1475 DRM_INFO("Loading %s Microcode\n", chip_name);
1477 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1478 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1481 if (rdev->pfp_fw->size != pfp_req_size) {
1483 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1484 rdev->pfp_fw->size, fw_name);
1489 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1490 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1493 if (rdev->me_fw->size != me_req_size) {
1495 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1496 rdev->me_fw->size, fw_name);
1500 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1501 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1504 if (rdev->rlc_fw->size != rlc_req_size) {
1506 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1507 rdev->rlc_fw->size, fw_name);
1512 platform_device_unregister(pdev);
1517 "r600_cp: Failed to load firmware \"%s\"\n",
1519 release_firmware(rdev->pfp_fw);
1520 rdev->pfp_fw = NULL;
1521 release_firmware(rdev->me_fw);
1523 release_firmware(rdev->rlc_fw);
1524 rdev->rlc_fw = NULL;
1529 static int r600_cp_load_microcode(struct radeon_device *rdev)
1531 const __be32 *fw_data;
1534 if (!rdev->me_fw || !rdev->pfp_fw)
1539 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1542 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1543 RREG32(GRBM_SOFT_RESET);
1545 WREG32(GRBM_SOFT_RESET, 0);
1547 WREG32(CP_ME_RAM_WADDR, 0);
1549 fw_data = (const __be32 *)rdev->me_fw->data;
1550 WREG32(CP_ME_RAM_WADDR, 0);
1551 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1552 WREG32(CP_ME_RAM_DATA,
1553 be32_to_cpup(fw_data++));
1555 fw_data = (const __be32 *)rdev->pfp_fw->data;
1556 WREG32(CP_PFP_UCODE_ADDR, 0);
1557 for (i = 0; i < PFP_UCODE_SIZE; i++)
1558 WREG32(CP_PFP_UCODE_DATA,
1559 be32_to_cpup(fw_data++));
1561 WREG32(CP_PFP_UCODE_ADDR, 0);
1562 WREG32(CP_ME_RAM_WADDR, 0);
1563 WREG32(CP_ME_RAM_RADDR, 0);
1567 int r600_cp_start(struct radeon_device *rdev)
1572 r = radeon_ring_lock(rdev, 7);
1574 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1577 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1578 radeon_ring_write(rdev, 0x1);
1579 if (rdev->family < CHIP_RV770) {
1580 radeon_ring_write(rdev, 0x3);
1581 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1583 radeon_ring_write(rdev, 0x0);
1584 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1586 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1587 radeon_ring_write(rdev, 0);
1588 radeon_ring_write(rdev, 0);
1589 radeon_ring_unlock_commit(rdev);
1592 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1596 int r600_cp_resume(struct radeon_device *rdev)
1603 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1604 RREG32(GRBM_SOFT_RESET);
1606 WREG32(GRBM_SOFT_RESET, 0);
1608 /* Set ring buffer size */
1609 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1610 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1612 tmp |= BUF_SWAP_32BIT;
1614 WREG32(CP_RB_CNTL, tmp);
1615 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1617 /* Set the write pointer delay */
1618 WREG32(CP_RB_WPTR_DELAY, 0);
1620 /* Initialize the ring buffer's read and write pointers */
1621 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1622 WREG32(CP_RB_RPTR_WR, 0);
1623 WREG32(CP_RB_WPTR, 0);
1624 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1625 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1627 WREG32(CP_RB_CNTL, tmp);
1629 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1630 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1632 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1633 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1635 r600_cp_start(rdev);
1636 rdev->cp.ready = true;
1637 r = radeon_ring_test(rdev);
1639 rdev->cp.ready = false;
1645 void r600_cp_commit(struct radeon_device *rdev)
1647 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1648 (void)RREG32(CP_RB_WPTR);
1651 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1655 /* Align ring size */
1656 rb_bufsz = drm_order(ring_size / 8);
1657 ring_size = (1 << (rb_bufsz + 1)) * 4;
1658 rdev->cp.ring_size = ring_size;
1659 rdev->cp.align_mask = 16 - 1;
1662 void r600_cp_fini(struct radeon_device *rdev)
1665 radeon_ring_fini(rdev);
1670 * GPU scratch registers helpers function.
1672 void r600_scratch_init(struct radeon_device *rdev)
1676 rdev->scratch.num_reg = 7;
1677 for (i = 0; i < rdev->scratch.num_reg; i++) {
1678 rdev->scratch.free[i] = true;
1679 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1683 int r600_ring_test(struct radeon_device *rdev)
1690 r = radeon_scratch_get(rdev, &scratch);
1692 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1695 WREG32(scratch, 0xCAFEDEAD);
1696 r = radeon_ring_lock(rdev, 3);
1698 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1699 radeon_scratch_free(rdev, scratch);
1702 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1703 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1704 radeon_ring_write(rdev, 0xDEADBEEF);
1705 radeon_ring_unlock_commit(rdev);
1706 for (i = 0; i < rdev->usec_timeout; i++) {
1707 tmp = RREG32(scratch);
1708 if (tmp == 0xDEADBEEF)
1712 if (i < rdev->usec_timeout) {
1713 DRM_INFO("ring test succeeded in %d usecs\n", i);
1715 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1719 radeon_scratch_free(rdev, scratch);
1723 void r600_wb_disable(struct radeon_device *rdev)
1727 WREG32(SCRATCH_UMSK, 0);
1728 if (rdev->wb.wb_obj) {
1729 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1730 if (unlikely(r != 0))
1732 radeon_bo_kunmap(rdev->wb.wb_obj);
1733 radeon_bo_unpin(rdev->wb.wb_obj);
1734 radeon_bo_unreserve(rdev->wb.wb_obj);
1738 void r600_wb_fini(struct radeon_device *rdev)
1740 r600_wb_disable(rdev);
1741 if (rdev->wb.wb_obj) {
1742 radeon_bo_unref(&rdev->wb.wb_obj);
1744 rdev->wb.wb_obj = NULL;
1748 int r600_wb_enable(struct radeon_device *rdev)
1752 if (rdev->wb.wb_obj == NULL) {
1753 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1754 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1756 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1759 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1760 if (unlikely(r != 0)) {
1764 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1765 &rdev->wb.gpu_addr);
1767 radeon_bo_unreserve(rdev->wb.wb_obj);
1768 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1772 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1773 radeon_bo_unreserve(rdev->wb.wb_obj);
1775 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1780 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1781 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1782 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1783 WREG32(SCRATCH_UMSK, 0xff);
1787 void r600_fence_ring_emit(struct radeon_device *rdev,
1788 struct radeon_fence *fence)
1790 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1792 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1793 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1794 /* wait for 3D idle clean */
1795 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1796 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1797 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1798 /* Emit fence sequence & fire IRQ */
1799 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1800 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1801 radeon_ring_write(rdev, fence->seq);
1802 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1803 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1804 radeon_ring_write(rdev, RB_INT_STAT);
1807 int r600_copy_blit(struct radeon_device *rdev,
1808 uint64_t src_offset, uint64_t dst_offset,
1809 unsigned num_pages, struct radeon_fence *fence)
1813 mutex_lock(&rdev->r600_blit.mutex);
1814 rdev->r600_blit.vb_ib = NULL;
1815 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1817 if (rdev->r600_blit.vb_ib)
1818 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1819 mutex_unlock(&rdev->r600_blit.mutex);
1822 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1823 r600_blit_done_copy(rdev, fence);
1824 mutex_unlock(&rdev->r600_blit.mutex);
1828 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1829 uint32_t tiling_flags, uint32_t pitch,
1830 uint32_t offset, uint32_t obj_size)
1832 /* FIXME: implement */
1836 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1838 /* FIXME: implement */
1842 bool r600_card_posted(struct radeon_device *rdev)
1846 /* first check CRTCs */
1847 reg = RREG32(D1CRTC_CONTROL) |
1848 RREG32(D2CRTC_CONTROL);
1852 /* then check MEM_SIZE, in case the crtcs are off */
1853 if (RREG32(CONFIG_MEMSIZE))
1859 int r600_startup(struct radeon_device *rdev)
1863 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1864 r = r600_init_microcode(rdev);
1866 DRM_ERROR("Failed to load firmware!\n");
1871 r600_mc_program(rdev);
1872 if (rdev->flags & RADEON_IS_AGP) {
1873 r600_agp_enable(rdev);
1875 r = r600_pcie_gart_enable(rdev);
1879 r600_gpu_init(rdev);
1880 r = r600_blit_init(rdev);
1882 r600_blit_fini(rdev);
1883 rdev->asic->copy = NULL;
1884 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1886 /* pin copy shader into vram */
1887 if (rdev->r600_blit.shader_obj) {
1888 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1889 if (unlikely(r != 0))
1891 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1892 &rdev->r600_blit.shader_gpu_addr);
1893 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1895 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1900 r = r600_irq_init(rdev);
1902 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1903 radeon_irq_kms_fini(rdev);
1908 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1911 r = r600_cp_load_microcode(rdev);
1914 r = r600_cp_resume(rdev);
1917 /* write back buffer are not vital so don't worry about failure */
1918 r600_wb_enable(rdev);
1922 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1926 temp = RREG32(CONFIG_CNTL);
1927 if (state == false) {
1933 WREG32(CONFIG_CNTL, temp);
1936 int r600_resume(struct radeon_device *rdev)
1940 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1941 * posting will perform necessary task to bring back GPU into good
1945 atom_asic_init(rdev->mode_info.atom_context);
1946 /* Initialize clocks */
1947 r = radeon_clocks_init(rdev);
1952 r = r600_startup(rdev);
1954 DRM_ERROR("r600 startup failed on resume\n");
1958 r = r600_ib_test(rdev);
1960 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1966 int r600_suspend(struct radeon_device *rdev)
1970 /* FIXME: we should wait for ring to be empty */
1972 rdev->cp.ready = false;
1973 r600_irq_suspend(rdev);
1974 r600_wb_disable(rdev);
1975 r600_pcie_gart_disable(rdev);
1976 /* unpin shaders bo */
1977 if (rdev->r600_blit.shader_obj) {
1978 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1980 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1981 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1987 /* Plan is to move initialization in that function and use
1988 * helper function so that radeon_device_init pretty much
1989 * do nothing more than calling asic specific function. This
1990 * should also allow to remove a bunch of callback function
1993 int r600_init(struct radeon_device *rdev)
1997 r = radeon_dummy_page_init(rdev);
2000 if (r600_debugfs_mc_info_init(rdev)) {
2001 DRM_ERROR("Failed to register debugfs file for mc !\n");
2003 /* This don't do much */
2004 r = radeon_gem_init(rdev);
2008 if (!radeon_get_bios(rdev)) {
2009 if (ASIC_IS_AVIVO(rdev))
2012 /* Must be an ATOMBIOS */
2013 if (!rdev->is_atom_bios) {
2014 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2017 r = radeon_atombios_init(rdev);
2020 /* Post card if necessary */
2021 if (!r600_card_posted(rdev)) {
2023 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2026 DRM_INFO("GPU not posted. posting now...\n");
2027 atom_asic_init(rdev->mode_info.atom_context);
2029 /* Initialize scratch registers */
2030 r600_scratch_init(rdev);
2031 /* Initialize surface registers */
2032 radeon_surface_init(rdev);
2033 /* Initialize clocks */
2034 radeon_get_clock_info(rdev->ddev);
2035 r = radeon_clocks_init(rdev);
2038 /* Initialize power management */
2039 radeon_pm_init(rdev);
2041 r = radeon_fence_driver_init(rdev);
2044 if (rdev->flags & RADEON_IS_AGP) {
2045 r = radeon_agp_init(rdev);
2047 radeon_agp_disable(rdev);
2049 r = r600_mc_init(rdev);
2052 /* Memory manager */
2053 r = radeon_bo_init(rdev);
2057 r = radeon_irq_kms_init(rdev);
2061 rdev->cp.ring_obj = NULL;
2062 r600_ring_init(rdev, 1024 * 1024);
2064 rdev->ih.ring_obj = NULL;
2065 r600_ih_ring_init(rdev, 64 * 1024);
2067 r = r600_pcie_gart_init(rdev);
2071 rdev->accel_working = true;
2072 r = r600_startup(rdev);
2074 dev_err(rdev->dev, "disabling GPU acceleration\n");
2077 r600_irq_fini(rdev);
2078 radeon_irq_kms_fini(rdev);
2079 r600_pcie_gart_fini(rdev);
2080 rdev->accel_working = false;
2082 if (rdev->accel_working) {
2083 r = radeon_ib_pool_init(rdev);
2085 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2086 rdev->accel_working = false;
2088 r = r600_ib_test(rdev);
2090 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2091 rdev->accel_working = false;
2096 r = r600_audio_init(rdev);
2098 return r; /* TODO error handling */
2102 void r600_fini(struct radeon_device *rdev)
2104 r600_audio_fini(rdev);
2105 r600_blit_fini(rdev);
2108 r600_irq_fini(rdev);
2109 radeon_irq_kms_fini(rdev);
2110 r600_pcie_gart_fini(rdev);
2111 radeon_agp_fini(rdev);
2112 radeon_gem_fini(rdev);
2113 radeon_fence_driver_fini(rdev);
2114 radeon_clocks_fini(rdev);
2115 radeon_bo_fini(rdev);
2116 radeon_atombios_fini(rdev);
2119 radeon_dummy_page_fini(rdev);
2126 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2128 /* FIXME: implement */
2129 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2130 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2131 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2132 radeon_ring_write(rdev, ib->length_dw);
2135 int r600_ib_test(struct radeon_device *rdev)
2137 struct radeon_ib *ib;
2143 r = radeon_scratch_get(rdev, &scratch);
2145 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2148 WREG32(scratch, 0xCAFEDEAD);
2149 r = radeon_ib_get(rdev, &ib);
2151 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2154 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2155 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2156 ib->ptr[2] = 0xDEADBEEF;
2157 ib->ptr[3] = PACKET2(0);
2158 ib->ptr[4] = PACKET2(0);
2159 ib->ptr[5] = PACKET2(0);
2160 ib->ptr[6] = PACKET2(0);
2161 ib->ptr[7] = PACKET2(0);
2162 ib->ptr[8] = PACKET2(0);
2163 ib->ptr[9] = PACKET2(0);
2164 ib->ptr[10] = PACKET2(0);
2165 ib->ptr[11] = PACKET2(0);
2166 ib->ptr[12] = PACKET2(0);
2167 ib->ptr[13] = PACKET2(0);
2168 ib->ptr[14] = PACKET2(0);
2169 ib->ptr[15] = PACKET2(0);
2171 r = radeon_ib_schedule(rdev, ib);
2173 radeon_scratch_free(rdev, scratch);
2174 radeon_ib_free(rdev, &ib);
2175 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2178 r = radeon_fence_wait(ib->fence, false);
2180 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2183 for (i = 0; i < rdev->usec_timeout; i++) {
2184 tmp = RREG32(scratch);
2185 if (tmp == 0xDEADBEEF)
2189 if (i < rdev->usec_timeout) {
2190 DRM_INFO("ib test succeeded in %u usecs\n", i);
2192 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2196 radeon_scratch_free(rdev, scratch);
2197 radeon_ib_free(rdev, &ib);
2204 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2205 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2206 * writing to the ring and the GPU consuming, the GPU writes to the ring
2207 * and host consumes. As the host irq handler processes interrupts, it
2208 * increments the rptr. When the rptr catches up with the wptr, all the
2209 * current interrupts have been processed.
2212 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2216 /* Align ring size */
2217 rb_bufsz = drm_order(ring_size / 4);
2218 ring_size = (1 << rb_bufsz) * 4;
2219 rdev->ih.ring_size = ring_size;
2220 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2224 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2228 /* Allocate ring buffer */
2229 if (rdev->ih.ring_obj == NULL) {
2230 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2232 RADEON_GEM_DOMAIN_GTT,
2233 &rdev->ih.ring_obj);
2235 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2238 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2239 if (unlikely(r != 0))
2241 r = radeon_bo_pin(rdev->ih.ring_obj,
2242 RADEON_GEM_DOMAIN_GTT,
2243 &rdev->ih.gpu_addr);
2245 radeon_bo_unreserve(rdev->ih.ring_obj);
2246 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2249 r = radeon_bo_kmap(rdev->ih.ring_obj,
2250 (void **)&rdev->ih.ring);
2251 radeon_bo_unreserve(rdev->ih.ring_obj);
2253 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2260 static void r600_ih_ring_fini(struct radeon_device *rdev)
2263 if (rdev->ih.ring_obj) {
2264 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2265 if (likely(r == 0)) {
2266 radeon_bo_kunmap(rdev->ih.ring_obj);
2267 radeon_bo_unpin(rdev->ih.ring_obj);
2268 radeon_bo_unreserve(rdev->ih.ring_obj);
2270 radeon_bo_unref(&rdev->ih.ring_obj);
2271 rdev->ih.ring = NULL;
2272 rdev->ih.ring_obj = NULL;
2276 static void r600_rlc_stop(struct radeon_device *rdev)
2279 if (rdev->family >= CHIP_RV770) {
2280 /* r7xx asics need to soft reset RLC before halting */
2281 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2282 RREG32(SRBM_SOFT_RESET);
2284 WREG32(SRBM_SOFT_RESET, 0);
2285 RREG32(SRBM_SOFT_RESET);
2288 WREG32(RLC_CNTL, 0);
2291 static void r600_rlc_start(struct radeon_device *rdev)
2293 WREG32(RLC_CNTL, RLC_ENABLE);
2296 static int r600_rlc_init(struct radeon_device *rdev)
2299 const __be32 *fw_data;
2304 r600_rlc_stop(rdev);
2306 WREG32(RLC_HB_BASE, 0);
2307 WREG32(RLC_HB_CNTL, 0);
2308 WREG32(RLC_HB_RPTR, 0);
2309 WREG32(RLC_HB_WPTR, 0);
2310 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2311 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2312 WREG32(RLC_MC_CNTL, 0);
2313 WREG32(RLC_UCODE_CNTL, 0);
2315 fw_data = (const __be32 *)rdev->rlc_fw->data;
2316 if (rdev->family >= CHIP_RV770) {
2317 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2318 WREG32(RLC_UCODE_ADDR, i);
2319 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2322 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2323 WREG32(RLC_UCODE_ADDR, i);
2324 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2327 WREG32(RLC_UCODE_ADDR, 0);
2329 r600_rlc_start(rdev);
2334 static void r600_enable_interrupts(struct radeon_device *rdev)
2336 u32 ih_cntl = RREG32(IH_CNTL);
2337 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2339 ih_cntl |= ENABLE_INTR;
2340 ih_rb_cntl |= IH_RB_ENABLE;
2341 WREG32(IH_CNTL, ih_cntl);
2342 WREG32(IH_RB_CNTL, ih_rb_cntl);
2343 rdev->ih.enabled = true;
2346 static void r600_disable_interrupts(struct radeon_device *rdev)
2348 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2349 u32 ih_cntl = RREG32(IH_CNTL);
2351 ih_rb_cntl &= ~IH_RB_ENABLE;
2352 ih_cntl &= ~ENABLE_INTR;
2353 WREG32(IH_RB_CNTL, ih_rb_cntl);
2354 WREG32(IH_CNTL, ih_cntl);
2355 /* set rptr, wptr to 0 */
2356 WREG32(IH_RB_RPTR, 0);
2357 WREG32(IH_RB_WPTR, 0);
2358 rdev->ih.enabled = false;
2363 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2367 WREG32(CP_INT_CNTL, 0);
2368 WREG32(GRBM_INT_CNTL, 0);
2369 WREG32(DxMODE_INT_MASK, 0);
2370 if (ASIC_IS_DCE3(rdev)) {
2371 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2372 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2373 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2374 WREG32(DC_HPD1_INT_CONTROL, tmp);
2375 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2376 WREG32(DC_HPD2_INT_CONTROL, tmp);
2377 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2378 WREG32(DC_HPD3_INT_CONTROL, tmp);
2379 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2380 WREG32(DC_HPD4_INT_CONTROL, tmp);
2381 if (ASIC_IS_DCE32(rdev)) {
2382 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383 WREG32(DC_HPD5_INT_CONTROL, 0);
2384 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2385 WREG32(DC_HPD6_INT_CONTROL, 0);
2388 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2389 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2390 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2391 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2392 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2393 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2394 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2395 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2399 int r600_irq_init(struct radeon_device *rdev)
2403 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2406 ret = r600_ih_ring_alloc(rdev);
2411 r600_disable_interrupts(rdev);
2414 ret = r600_rlc_init(rdev);
2416 r600_ih_ring_fini(rdev);
2420 /* setup interrupt control */
2421 /* set dummy read address to ring address */
2422 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2423 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2424 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2425 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2427 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2428 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2429 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2430 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2432 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2433 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2435 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2436 IH_WPTR_OVERFLOW_CLEAR |
2438 /* WPTR writeback, not yet */
2439 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2440 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2441 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2443 WREG32(IH_RB_CNTL, ih_rb_cntl);
2445 /* set rptr, wptr to 0 */
2446 WREG32(IH_RB_RPTR, 0);
2447 WREG32(IH_RB_WPTR, 0);
2449 /* Default settings for IH_CNTL (disabled at first) */
2450 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2451 /* RPTR_REARM only works if msi's are enabled */
2452 if (rdev->msi_enabled)
2453 ih_cntl |= RPTR_REARM;
2456 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2458 WREG32(IH_CNTL, ih_cntl);
2460 /* force the active interrupt state to all disabled */
2461 r600_disable_interrupt_state(rdev);
2464 r600_enable_interrupts(rdev);
2469 void r600_irq_suspend(struct radeon_device *rdev)
2471 r600_disable_interrupts(rdev);
2472 r600_rlc_stop(rdev);
2475 void r600_irq_fini(struct radeon_device *rdev)
2477 r600_irq_suspend(rdev);
2478 r600_ih_ring_fini(rdev);
2481 int r600_irq_set(struct radeon_device *rdev)
2483 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2485 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2487 if (!rdev->irq.installed) {
2488 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2491 /* don't enable anything if the ih is disabled */
2492 if (!rdev->ih.enabled) {
2493 r600_disable_interrupts(rdev);
2494 /* force the active interrupt state to all disabled */
2495 r600_disable_interrupt_state(rdev);
2499 if (ASIC_IS_DCE3(rdev)) {
2500 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2501 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2502 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2503 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2504 if (ASIC_IS_DCE32(rdev)) {
2505 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2506 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2510 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2511 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2514 if (rdev->irq.sw_int) {
2515 DRM_DEBUG("r600_irq_set: sw int\n");
2516 cp_int_cntl |= RB_INT_ENABLE;
2518 if (rdev->irq.crtc_vblank_int[0]) {
2519 DRM_DEBUG("r600_irq_set: vblank 0\n");
2520 mode_int |= D1MODE_VBLANK_INT_MASK;
2522 if (rdev->irq.crtc_vblank_int[1]) {
2523 DRM_DEBUG("r600_irq_set: vblank 1\n");
2524 mode_int |= D2MODE_VBLANK_INT_MASK;
2526 if (rdev->irq.hpd[0]) {
2527 DRM_DEBUG("r600_irq_set: hpd 1\n");
2528 hpd1 |= DC_HPDx_INT_EN;
2530 if (rdev->irq.hpd[1]) {
2531 DRM_DEBUG("r600_irq_set: hpd 2\n");
2532 hpd2 |= DC_HPDx_INT_EN;
2534 if (rdev->irq.hpd[2]) {
2535 DRM_DEBUG("r600_irq_set: hpd 3\n");
2536 hpd3 |= DC_HPDx_INT_EN;
2538 if (rdev->irq.hpd[3]) {
2539 DRM_DEBUG("r600_irq_set: hpd 4\n");
2540 hpd4 |= DC_HPDx_INT_EN;
2542 if (rdev->irq.hpd[4]) {
2543 DRM_DEBUG("r600_irq_set: hpd 5\n");
2544 hpd5 |= DC_HPDx_INT_EN;
2546 if (rdev->irq.hpd[5]) {
2547 DRM_DEBUG("r600_irq_set: hpd 6\n");
2548 hpd6 |= DC_HPDx_INT_EN;
2551 WREG32(CP_INT_CNTL, cp_int_cntl);
2552 WREG32(DxMODE_INT_MASK, mode_int);
2553 if (ASIC_IS_DCE3(rdev)) {
2554 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2555 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2556 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2557 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2558 if (ASIC_IS_DCE32(rdev)) {
2559 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2560 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2563 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2564 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2565 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2571 static inline void r600_irq_ack(struct radeon_device *rdev,
2574 u32 *disp_int_cont2)
2578 if (ASIC_IS_DCE3(rdev)) {
2579 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2580 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2581 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2583 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2584 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2585 *disp_int_cont2 = 0;
2588 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2589 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2590 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2591 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2592 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2593 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2594 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2595 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2596 if (*disp_int & DC_HPD1_INTERRUPT) {
2597 if (ASIC_IS_DCE3(rdev)) {
2598 tmp = RREG32(DC_HPD1_INT_CONTROL);
2599 tmp |= DC_HPDx_INT_ACK;
2600 WREG32(DC_HPD1_INT_CONTROL, tmp);
2602 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2603 tmp |= DC_HPDx_INT_ACK;
2604 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2607 if (*disp_int & DC_HPD2_INTERRUPT) {
2608 if (ASIC_IS_DCE3(rdev)) {
2609 tmp = RREG32(DC_HPD2_INT_CONTROL);
2610 tmp |= DC_HPDx_INT_ACK;
2611 WREG32(DC_HPD2_INT_CONTROL, tmp);
2613 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2614 tmp |= DC_HPDx_INT_ACK;
2615 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2618 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2619 if (ASIC_IS_DCE3(rdev)) {
2620 tmp = RREG32(DC_HPD3_INT_CONTROL);
2621 tmp |= DC_HPDx_INT_ACK;
2622 WREG32(DC_HPD3_INT_CONTROL, tmp);
2624 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2625 tmp |= DC_HPDx_INT_ACK;
2626 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2629 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2630 tmp = RREG32(DC_HPD4_INT_CONTROL);
2631 tmp |= DC_HPDx_INT_ACK;
2632 WREG32(DC_HPD4_INT_CONTROL, tmp);
2634 if (ASIC_IS_DCE32(rdev)) {
2635 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2636 tmp = RREG32(DC_HPD5_INT_CONTROL);
2637 tmp |= DC_HPDx_INT_ACK;
2638 WREG32(DC_HPD5_INT_CONTROL, tmp);
2640 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2641 tmp = RREG32(DC_HPD5_INT_CONTROL);
2642 tmp |= DC_HPDx_INT_ACK;
2643 WREG32(DC_HPD6_INT_CONTROL, tmp);
2648 void r600_irq_disable(struct radeon_device *rdev)
2650 u32 disp_int, disp_int_cont, disp_int_cont2;
2652 r600_disable_interrupts(rdev);
2653 /* Wait and acknowledge irq */
2655 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2656 r600_disable_interrupt_state(rdev);
2659 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2663 /* XXX use writeback */
2664 wptr = RREG32(IH_RB_WPTR);
2666 if (wptr & RB_OVERFLOW) {
2667 /* When a ring buffer overflow happen start parsing interrupt
2668 * from the last not overwritten vector (wptr + 16). Hopefully
2669 * this should allow us to catchup.
2671 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2672 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2673 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2674 tmp = RREG32(IH_RB_CNTL);
2675 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2676 WREG32(IH_RB_CNTL, tmp);
2678 return (wptr & rdev->ih.ptr_mask);
2682 * Each IV ring entry is 128 bits:
2683 * [7:0] - interrupt source id
2685 * [59:32] - interrupt source data
2686 * [127:60] - reserved
2688 * The basic interrupt vector entries
2689 * are decoded as follows:
2690 * src_id src_data description
2695 * 19 0 FP Hot plug detection A
2696 * 19 1 FP Hot plug detection B
2697 * 19 2 DAC A auto-detection
2698 * 19 3 DAC B auto-detection
2702 * 181 - EOP Interrupt
2705 * Note, these are based on r600 and may need to be
2706 * adjusted or added to on newer asics
2709 int r600_irq_process(struct radeon_device *rdev)
2711 u32 wptr = r600_get_ih_wptr(rdev);
2712 u32 rptr = rdev->ih.rptr;
2713 u32 src_id, src_data;
2714 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2715 unsigned long flags;
2716 bool queue_hotplug = false;
2718 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2719 if (!rdev->ih.enabled)
2722 spin_lock_irqsave(&rdev->ih.lock, flags);
2725 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2728 if (rdev->shutdown) {
2729 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2734 /* display interrupts */
2735 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2737 rdev->ih.wptr = wptr;
2738 while (rptr != wptr) {
2739 /* wptr/rptr are in bytes! */
2740 ring_index = rptr / 4;
2741 src_id = rdev->ih.ring[ring_index] & 0xff;
2742 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2745 case 1: /* D1 vblank/vline */
2747 case 0: /* D1 vblank */
2748 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2749 drm_handle_vblank(rdev->ddev, 0);
2750 wake_up(&rdev->irq.vblank_queue);
2751 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2752 DRM_DEBUG("IH: D1 vblank\n");
2755 case 1: /* D1 vline */
2756 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2757 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2758 DRM_DEBUG("IH: D1 vline\n");
2762 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2766 case 5: /* D2 vblank/vline */
2768 case 0: /* D2 vblank */
2769 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2770 drm_handle_vblank(rdev->ddev, 1);
2771 wake_up(&rdev->irq.vblank_queue);
2772 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2773 DRM_DEBUG("IH: D2 vblank\n");
2776 case 1: /* D1 vline */
2777 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2778 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2779 DRM_DEBUG("IH: D2 vline\n");
2783 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2787 case 19: /* HPD/DAC hotplug */
2790 if (disp_int & DC_HPD1_INTERRUPT) {
2791 disp_int &= ~DC_HPD1_INTERRUPT;
2792 queue_hotplug = true;
2793 DRM_DEBUG("IH: HPD1\n");
2797 if (disp_int & DC_HPD2_INTERRUPT) {
2798 disp_int &= ~DC_HPD2_INTERRUPT;
2799 queue_hotplug = true;
2800 DRM_DEBUG("IH: HPD2\n");
2804 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2805 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2806 queue_hotplug = true;
2807 DRM_DEBUG("IH: HPD3\n");
2811 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2812 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2813 queue_hotplug = true;
2814 DRM_DEBUG("IH: HPD4\n");
2818 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2819 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2820 queue_hotplug = true;
2821 DRM_DEBUG("IH: HPD5\n");
2825 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2826 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2827 queue_hotplug = true;
2828 DRM_DEBUG("IH: HPD6\n");
2832 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2836 case 176: /* CP_INT in ring buffer */
2837 case 177: /* CP_INT in IB1 */
2838 case 178: /* CP_INT in IB2 */
2839 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2840 radeon_fence_process(rdev);
2842 case 181: /* CP EOP event */
2843 DRM_DEBUG("IH: CP EOP\n");
2846 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2850 /* wptr/rptr are in bytes! */
2852 rptr &= rdev->ih.ptr_mask;
2854 /* make sure wptr hasn't changed while processing */
2855 wptr = r600_get_ih_wptr(rdev);
2856 if (wptr != rdev->ih.wptr)
2859 queue_work(rdev->wq, &rdev->hotplug_work);
2860 rdev->ih.rptr = rptr;
2861 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2862 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2869 #if defined(CONFIG_DEBUG_FS)
2871 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2873 struct drm_info_node *node = (struct drm_info_node *) m->private;
2874 struct drm_device *dev = node->minor->dev;
2875 struct radeon_device *rdev = dev->dev_private;
2876 unsigned count, i, j;
2878 radeon_ring_free_size(rdev);
2879 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2880 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2881 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2882 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2883 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2884 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2885 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2886 seq_printf(m, "%u dwords in ring\n", count);
2888 for (j = 0; j <= count; j++) {
2889 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2890 i = (i + 1) & rdev->cp.ptr_mask;
2895 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2897 struct drm_info_node *node = (struct drm_info_node *) m->private;
2898 struct drm_device *dev = node->minor->dev;
2899 struct radeon_device *rdev = dev->dev_private;
2901 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2902 DREG32_SYS(m, rdev, VM_L2_STATUS);
2906 static struct drm_info_list r600_mc_info_list[] = {
2907 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2908 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2912 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2914 #if defined(CONFIG_DEBUG_FS)
2915 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2922 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2923 * rdev: radeon device structure
2924 * bo: buffer object struct which userspace is waiting for idle
2926 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2927 * through ring buffer, this leads to corruption in rendering, see
2928 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2929 * directly perform HDP flush by writing register through MMIO.
2931 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2933 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);