2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
34 /* r420,r423,rv410 depends on : */
35 void r100_pci_gart_disable(struct radeon_device *rdev);
36 void r100_hdp_reset(struct radeon_device *rdev);
37 void r100_mc_setup(struct radeon_device *rdev);
38 int r100_gui_wait_for_idle(struct radeon_device *rdev);
39 void r100_mc_disable_clients(struct radeon_device *rdev);
40 void r300_vram_info(struct radeon_device *rdev);
41 int r300_mc_wait_for_idle(struct radeon_device *rdev);
42 int rv370_pcie_gart_enable(struct radeon_device *rdev);
43 void rv370_pcie_gart_disable(struct radeon_device *rdev);
45 /* This files gather functions specifics to :
48 * Some of these functions might be used by newer ASICs.
50 void r420_gpu_init(struct radeon_device *rdev);
51 int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
57 int r420_mc_init(struct radeon_device *rdev)
61 if (r100_debugfs_rbbm_init(rdev)) {
62 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
64 if (r420_debugfs_pipes_info_init(rdev)) {
65 DRM_ERROR("Failed to register debugfs file for pipes !\n");
69 r100_pci_gart_disable(rdev);
70 if (rdev->flags & RADEON_IS_PCIE) {
71 rv370_pcie_gart_disable(rdev);
74 /* Setup GPU memory space */
75 rdev->mc.vram_location = 0xFFFFFFFFUL;
76 rdev->mc.gtt_location = 0xFFFFFFFFUL;
77 if (rdev->flags & RADEON_IS_AGP) {
78 r = radeon_agp_init(rdev);
80 printk(KERN_WARNING "[drm] Disabling AGP\n");
81 rdev->flags &= ~RADEON_IS_AGP;
82 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
84 rdev->mc.gtt_location = rdev->mc.agp_base;
87 r = radeon_mc_setup(rdev);
92 /* Program GPU memory space */
93 r100_mc_disable_clients(rdev);
94 if (r300_mc_wait_for_idle(rdev)) {
95 printk(KERN_WARNING "Failed to wait MC idle while "
96 "programming pipes. Bad things might happen.\n");
102 void r420_mc_fini(struct radeon_device *rdev)
104 if (rdev->flags & RADEON_IS_PCIE) {
105 rv370_pcie_gart_disable(rdev);
106 radeon_gart_table_vram_free(rdev);
108 r100_pci_gart_disable(rdev);
109 radeon_gart_table_ram_free(rdev);
111 radeon_gart_fini(rdev);
116 * Global GPU functions
118 void r420_errata(struct radeon_device *rdev)
120 rdev->pll_errata = 0;
123 void r420_pipes_init(struct radeon_device *rdev)
126 unsigned gb_pipe_select;
129 /* GA_ENHANCE workaround TCL deadlock issue */
130 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
131 /* get max number of pipes */
132 gb_pipe_select = RREG32(0x402C);
133 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
134 rdev->num_gb_pipes = num_pipes;
138 /* force to 1 pipe */
153 WREG32(0x42C8, (1 << num_pipes) - 1);
154 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
155 tmp |= (1 << 4) | (1 << 0);
157 if (r100_gui_wait_for_idle(rdev)) {
158 printk(KERN_WARNING "Failed to wait GUI idle while "
159 "programming pipes. Bad things might happen.\n");
162 tmp = RREG32(0x170C);
163 WREG32(0x170C, tmp | (1 << 31));
165 WREG32(R300_RB2D_DSTCACHE_MODE,
166 RREG32(R300_RB2D_DSTCACHE_MODE) |
167 R300_DC_AUTOFLUSH_ENABLE |
168 R300_DC_DC_DISABLE_IGNORE_PE);
170 if (r100_gui_wait_for_idle(rdev)) {
171 printk(KERN_WARNING "Failed to wait GUI idle while "
172 "programming pipes. Bad things might happen.\n");
175 if (rdev->family == CHIP_RV530) {
176 tmp = RREG32(RV530_GB_PIPE_SELECT2);
178 rdev->num_z_pipes = 2;
180 rdev->num_z_pipes = 1;
182 rdev->num_z_pipes = 1;
184 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
185 rdev->num_gb_pipes, rdev->num_z_pipes);
188 void r420_gpu_init(struct radeon_device *rdev)
190 r100_hdp_reset(rdev);
191 r420_pipes_init(rdev);
192 if (r300_mc_wait_for_idle(rdev)) {
193 printk(KERN_WARNING "Failed to wait MC idle while "
194 "programming pipes. Bad things might happen.\n");
200 * r420,r423,rv410 VRAM info
202 void r420_vram_info(struct radeon_device *rdev)
204 r300_vram_info(rdev);
211 #if defined(CONFIG_DEBUG_FS)
212 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
214 struct drm_info_node *node = (struct drm_info_node *) m->private;
215 struct drm_device *dev = node->minor->dev;
216 struct radeon_device *rdev = dev->dev_private;
219 tmp = RREG32(R400_GB_PIPE_SELECT);
220 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
221 tmp = RREG32(R300_GB_TILE_CONFIG);
222 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
223 tmp = RREG32(R300_DST_PIPE_CONFIG);
224 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
228 static struct drm_info_list r420_pipes_info_list[] = {
229 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
233 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
235 #if defined(CONFIG_DEBUG_FS)
236 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
242 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
246 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
247 r = RREG32(R_0001FC_MC_IND_DATA);
251 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
253 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
254 S_0001F8_MC_IND_WR_EN(1));
255 WREG32(R_0001FC_MC_IND_DATA, v);