SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "atom.h"
  33 #include "r420d.h"
  34
  35 int r420_mc_init(struct radeon_device *rdev)
  36 {
  37         int r;
  38
  39         /* Setup GPU memory space */
  40         rdev->mc.vram_location = 0xFFFFFFFFUL;
  41         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  42         if (rdev->flags & RADEON_IS_AGP) {
  43                 r = radeon_agp_init(rdev);
  44                 if (r) {
  45                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  46                         rdev->flags &= ~RADEON_IS_AGP;
  47                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  48                 } else {
  49                         rdev->mc.gtt_location = rdev->mc.agp_base;
  50                 }
  51         }
  52         r = radeon_mc_setup(rdev);
  53         if (r) {
  54                 return r;
  55         }
  56         return 0;
  57 }
  58
  59 void r420_pipes_init(struct radeon_device *rdev)
  60 {
  61         unsigned tmp;
  62         unsigned gb_pipe_select;
  63         unsigned num_pipes;
  64
  65         /* GA_ENHANCE workaround TCL deadlock issue */
  66         WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
  67         /* get max number of pipes */
  68         gb_pipe_select = RREG32(0x402C);
  69         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  70         rdev->num_gb_pipes = num_pipes;
  71         tmp = 0;
  72         switch (num_pipes) {
  73         default:
  74                 /* force to 1 pipe */
  75                 num_pipes = 1;
  76         case 1:
  77                 tmp = (0 << 1);
  78                 break;
  79         case 2:
  80                 tmp = (3 << 1);
  81                 break;
  82         case 3:
  83                 tmp = (6 << 1);
  84                 break;
  85         case 4:
  86                 tmp = (7 << 1);
  87                 break;
  88         }
  89         WREG32(0x42C8, (1 << num_pipes) - 1);
  90         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  91         tmp |= (1 << 4) | (1 << 0);
  92         WREG32(0x4018, tmp);
  93         if (r100_gui_wait_for_idle(rdev)) {
  94                 printk(KERN_WARNING "Failed to wait GUI idle while "
  95                        "programming pipes. Bad things might happen.\n");
  96         }
  97
  98         tmp = RREG32(0x170C);
  99         WREG32(0x170C, tmp | (1 << 31));
 100
 101         WREG32(R300_RB2D_DSTCACHE_MODE,
 102                RREG32(R300_RB2D_DSTCACHE_MODE) |
 103                R300_DC_AUTOFLUSH_ENABLE |
 104                R300_DC_DC_DISABLE_IGNORE_PE);
 105
 106         if (r100_gui_wait_for_idle(rdev)) {
 107                 printk(KERN_WARNING "Failed to wait GUI idle while "
 108                        "programming pipes. Bad things might happen.\n");
 109         }
 110
 111         if (rdev->family == CHIP_RV530) {
 112                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 113                 if ((tmp & 3) == 3)
 114                         rdev->num_z_pipes = 2;
 115                 else
 116                         rdev->num_z_pipes = 1;
 117         } else
 118                 rdev->num_z_pipes = 1;
 119
 120         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 121                  rdev->num_gb_pipes, rdev->num_z_pipes);
 122 }
 123
 124 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 125 {
 126         u32 r;
 127
 128         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 129         r = RREG32(R_0001FC_MC_IND_DATA);
 130         return r;
 131 }
 132
 133 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 134 {
 135         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 136                 S_0001F8_MC_IND_WR_EN(1));
 137         WREG32(R_0001FC_MC_IND_DATA, v);
 138 }
 139
 140 static void r420_debugfs(struct radeon_device *rdev)
 141 {
 142         if (r100_debugfs_rbbm_init(rdev)) {
 143                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 144         }
 145         if (r420_debugfs_pipes_info_init(rdev)) {
 146                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 147         }
 148 }
 149
 150 static void r420_clock_resume(struct radeon_device *rdev)
 151 {
 152         u32 sclk_cntl;
 153         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 154         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 155         if (rdev->family == CHIP_R420)
 156                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 157         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 158 }
 159
 160 int r420_resume(struct radeon_device *rdev)
 161 {
 162         int r;
 163
 164         /* Resume clock before doing reset */
 165         r420_clock_resume(rdev);
 166         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 167         if (radeon_gpu_reset(rdev)) {
 168                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 169                         RREG32(R_000E40_RBBM_STATUS),
 170                         RREG32(R_0007C0_CP_STAT));
 171         }
 172         /* check if cards are posted or not */
 173         if (rdev->is_atom_bios) {
 174                 atom_asic_init(rdev->mode_info.atom_context);
 175         } else {
 176                 radeon_combios_asic_init(rdev->ddev);
 177         }
 178         /* Resume clock after posting */
 179         r420_clock_resume(rdev);
 180         r300_mc_program(rdev);
 181         /* Initialize GART (initialize after TTM so we can allocate
 182          * memory through TTM but finalize after TTM) */
 183         r = radeon_gart_enable(rdev);
 184         if (r) {
 185                 dev_err(rdev->dev, "failled initializing GART (%d).\n", r);
 186                 return r;
 187         }
 188         r420_pipes_init(rdev);
 189         /* Enable IRQ */
 190         rdev->irq.sw_int = true;
 191         r100_irq_set(rdev);
 192         /* 1M ring buffer */
 193         r = r100_cp_init(rdev, 1024 * 1024);
 194         if (r) {
 195                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 196                 return r;
 197         }
 198         r = r100_wb_init(rdev);
 199         if (r) {
 200                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 201         }
 202         r = r100_ib_init(rdev);
 203         if (r) {
 204                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 205                 return r;
 206         }
 207         return 0;
 208 }
 209
 210 int r420_suspend(struct radeon_device *rdev)
 211 {
 212         r100_cp_disable(rdev);
 213         r100_wb_disable(rdev);
 214         r100_irq_disable(rdev);
 215         radeon_gart_disable(rdev);
 216         return 0;
 217 }
 218
 219 void r420_fini(struct radeon_device *rdev)
 220 {
 221         r100_cp_fini(rdev);
 222         r100_wb_fini(rdev);
 223         r100_ib_fini(rdev);
 224         radeon_gem_fini(rdev);
 225         if (rdev->flags & RADEON_IS_PCIE) {
 226                 rv370_pcie_gart_disable(rdev);
 227                 radeon_gart_table_vram_free(rdev);
 228         } else {
 229                 r100_pci_gart_disable(rdev);
 230                 radeon_gart_table_ram_free(rdev);
 231         }
 232         radeon_gart_fini(rdev);
 233         radeon_agp_fini(rdev);
 234         radeon_irq_kms_fini(rdev);
 235         radeon_fence_driver_fini(rdev);
 236         radeon_object_fini(rdev);
 237         if (rdev->is_atom_bios) {
 238                 radeon_atombios_fini(rdev);
 239         } else {
 240                 radeon_combios_fini(rdev);
 241         }
 242         kfree(rdev->bios);
 243         rdev->bios = NULL;
 244 }
 245
 246 int r420_init(struct radeon_device *rdev)
 247 {
 248         int r;
 249
 250         rdev->new_init_path = true;
 251         /* Initialize scratch registers */
 252         radeon_scratch_init(rdev);
 253         /* Initialize surface registers */
 254         radeon_surface_init(rdev);
 255         /* TODO: disable VGA need to use VGA request */
 256         /* BIOS*/
 257         if (!radeon_get_bios(rdev)) {
 258                 if (ASIC_IS_AVIVO(rdev))
 259                         return -EINVAL;
 260         }
 261         if (rdev->is_atom_bios) {
 262                 r = radeon_atombios_init(rdev);
 263                 if (r) {
 264                         return r;
 265                 }
 266         } else {
 267                 r = radeon_combios_init(rdev);
 268                 if (r) {
 269                         return r;
 270                 }
 271         }
 272         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 273         if (radeon_gpu_reset(rdev)) {
 274                 dev_warn(rdev->dev,
 275                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 276                         RREG32(R_000E40_RBBM_STATUS),
 277                         RREG32(R_0007C0_CP_STAT));
 278         }
 279         /* check if cards are posted or not */
 280         if (!radeon_card_posted(rdev) && rdev->bios) {
 281                 DRM_INFO("GPU not posted. posting now...\n");
 282                 if (rdev->is_atom_bios) {
 283                         atom_asic_init(rdev->mode_info.atom_context);
 284                 } else {
 285                         radeon_combios_asic_init(rdev->ddev);
 286                 }
 287         }
 288         /* Initialize clocks */
 289         radeon_get_clock_info(rdev->ddev);
 290         /* Get vram informations */
 291         r300_vram_info(rdev);
 292         /* Initialize memory controller (also test AGP) */
 293         r = r420_mc_init(rdev);
 294         if (r) {
 295                 return r;
 296         }
 297         r420_debugfs(rdev);
 298         /* Fence driver */
 299         r = radeon_fence_driver_init(rdev);
 300         if (r) {
 301                 return r;
 302         }
 303         r = radeon_irq_kms_init(rdev);
 304         if (r) {
 305                 return r;
 306         }
 307         /* Memory manager */
 308         r = radeon_object_init(rdev);
 309         if (r) {
 310                 return r;
 311         }
 312         r300_set_reg_safe(rdev);
 313         r = r420_resume(rdev);
 314         if (r) {
 315                 /* Somethings want wront with the accel init stop accel */
 316                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 317                 r420_suspend(rdev);
 318                 r100_cp_fini(rdev);
 319                 r100_wb_fini(rdev);
 320                 r100_ib_fini(rdev);
 321                 if (rdev->flags & RADEON_IS_PCIE) {
 322                         rv370_pcie_gart_disable(rdev);
 323                         radeon_gart_table_vram_free(rdev);
 324                 } else {
 325                         r100_pci_gart_disable(rdev);
 326                         radeon_gart_table_ram_free(rdev);
 327                 }
 328                 radeon_gart_fini(rdev);
 329                 radeon_agp_fini(rdev);
 330                 radeon_irq_kms_fini(rdev);
 331         }
 332         return 0;
 333 }
 334
 335 /*
 336  * Debugfs info
 337  */
 338 #if defined(CONFIG_DEBUG_FS)
 339 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 340 {
 341         struct drm_info_node *node = (struct drm_info_node *) m->private;
 342         struct drm_device *dev = node->minor->dev;
 343         struct radeon_device *rdev = dev->dev_private;
 344         uint32_t tmp;
 345
 346         tmp = RREG32(R400_GB_PIPE_SELECT);
 347         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 348         tmp = RREG32(R300_GB_TILE_CONFIG);
 349         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 350         tmp = RREG32(R300_DST_PIPE_CONFIG);
 351         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 352         return 0;
 353 }
 354
 355 static struct drm_info_list r420_pipes_info_list[] = {
 356         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 357 };
 358 #endif
 359
 360 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 361 {
 362 #if defined(CONFIG_DEBUG_FS)
 363         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 364 #else
 365         return 0;
 366 #endif
 367 }