SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_microcode.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35
  36 /* This files gather functions specifics to:
  37  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  38  *
  39  * Some of these functions might be used by newer ASICs.
  40  */
  41 void r100_hdp_reset(struct radeon_device *rdev);
  42 void r100_gpu_init(struct radeon_device *rdev);
  43 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  44 int r100_mc_wait_for_idle(struct radeon_device *rdev);
  45 void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
  46 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
  47 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  48
  49
  50 /*
  51  * PCI GART
  52  */
  53 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  54 {
  55         /* TODO: can we do somethings here ? */
  56         /* It seems hw only cache one entry so we should discard this
  57          * entry otherwise if first GPU GART read hit this entry it
  58          * could end up in wrong address. */
  59 }
  60
  61 int r100_pci_gart_enable(struct radeon_device *rdev)
  62 {
  63         uint32_t tmp;
  64         int r;
  65
  66         /* Initialize common gart structure */
  67         r = radeon_gart_init(rdev);
  68         if (r) {
  69                 return r;
  70         }
  71         if (rdev->gart.table.ram.ptr == NULL) {
  72                 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  73                 r = radeon_gart_table_ram_alloc(rdev);
  74                 if (r) {
  75                         return r;
  76                 }
  77         }
  78         /* discard memory request outside of configured range */
  79         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  80         WREG32(RADEON_AIC_CNTL, tmp);
  81         /* set address range for PCI address translate */
  82         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
  83         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  84         WREG32(RADEON_AIC_HI_ADDR, tmp);
  85         /* Enable bus mastering */
  86         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  87         WREG32(RADEON_BUS_CNTL, tmp);
  88         /* set PCI GART page-table base address */
  89         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  90         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  91         WREG32(RADEON_AIC_CNTL, tmp);
  92         r100_pci_gart_tlb_flush(rdev);
  93         rdev->gart.ready = true;
  94         return 0;
  95 }
  96
  97 void r100_pci_gart_disable(struct radeon_device *rdev)
  98 {
  99         uint32_t tmp;
 100
 101         /* discard memory request outside of configured range */
 102         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 103         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 104         WREG32(RADEON_AIC_LO_ADDR, 0);
 105         WREG32(RADEON_AIC_HI_ADDR, 0);
 106 }
 107
 108 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 109 {
 110         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 111                 return -EINVAL;
 112         }
 113         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 114         return 0;
 115 }
 116
 117 int r100_gart_enable(struct radeon_device *rdev)
 118 {
 119         if (rdev->flags & RADEON_IS_AGP) {
 120                 r100_pci_gart_disable(rdev);
 121                 return 0;
 122         }
 123         return r100_pci_gart_enable(rdev);
 124 }
 125
 126
 127 /*
 128  * MC
 129  */
 130 void r100_mc_disable_clients(struct radeon_device *rdev)
 131 {
 132         uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
 133
 134         /* FIXME: is this function correct for rs100,rs200,rs300 ? */
 135         if (r100_gui_wait_for_idle(rdev)) {
 136                 printk(KERN_WARNING "Failed to wait GUI idle while "
 137                        "programming pipes. Bad things might happen.\n");
 138         }
 139
 140         /* stop display and memory access */
 141         ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
 142         WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
 143         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 144         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
 145         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 146
 147         r100_gpu_wait_for_vsync(rdev);
 148
 149         WREG32(RADEON_CRTC_GEN_CNTL,
 150                (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
 151                RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
 152
 153         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 154                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 155
 156                 r100_gpu_wait_for_vsync2(rdev);
 157                 WREG32(RADEON_CRTC2_GEN_CNTL,
 158                        (crtc2_gen_cntl &
 159                         ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
 160                        RADEON_CRTC2_DISP_REQ_EN_B);
 161         }
 162
 163         udelay(500);
 164 }
 165
 166 void r100_mc_setup(struct radeon_device *rdev)
 167 {
 168         uint32_t tmp;
 169         int r;
 170
 171         r = r100_debugfs_mc_info_init(rdev);
 172         if (r) {
 173                 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
 174         }
 175         /* Write VRAM size in case we are limiting it */
 176         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
 177         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
 178         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
 179         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
 180         WREG32(RADEON_MC_FB_LOCATION, tmp);
 181
 182         /* Enable bus mastering */
 183         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 184         WREG32(RADEON_BUS_CNTL, tmp);
 185
 186         if (rdev->flags & RADEON_IS_AGP) {
 187                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 188                 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
 189                 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
 190                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 191                 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
 192         } else {
 193                 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
 194                 WREG32(RADEON_AGP_BASE, 0);
 195         }
 196
 197         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
 198         tmp |= (7 << 28);
 199         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
 200         (void)RREG32(RADEON_HOST_PATH_CNTL);
 201         WREG32(RADEON_HOST_PATH_CNTL, tmp);
 202         (void)RREG32(RADEON_HOST_PATH_CNTL);
 203 }
 204
 205 int r100_mc_init(struct radeon_device *rdev)
 206 {
 207         int r;
 208
 209         if (r100_debugfs_rbbm_init(rdev)) {
 210                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 211         }
 212
 213         r100_gpu_init(rdev);
 214         /* Disable gart which also disable out of gart access */
 215         r100_pci_gart_disable(rdev);
 216
 217         /* Setup GPU memory space */
 218         rdev->mc.gtt_location = 0xFFFFFFFFUL;
 219         if (rdev->flags & RADEON_IS_AGP) {
 220                 r = radeon_agp_init(rdev);
 221                 if (r) {
 222                         printk(KERN_WARNING "[drm] Disabling AGP\n");
 223                         rdev->flags &= ~RADEON_IS_AGP;
 224                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 225                 } else {
 226                         rdev->mc.gtt_location = rdev->mc.agp_base;
 227                 }
 228         }
 229         r = radeon_mc_setup(rdev);
 230         if (r) {
 231                 return r;
 232         }
 233
 234         r100_mc_disable_clients(rdev);
 235         if (r100_mc_wait_for_idle(rdev)) {
 236                 printk(KERN_WARNING "Failed to wait MC idle while "
 237                        "programming pipes. Bad things might happen.\n");
 238         }
 239
 240         r100_mc_setup(rdev);
 241         return 0;
 242 }
 243
 244 void r100_mc_fini(struct radeon_device *rdev)
 245 {
 246         r100_pci_gart_disable(rdev);
 247         radeon_gart_table_ram_free(rdev);
 248         radeon_gart_fini(rdev);
 249 }
 250
 251
 252 /*
 253  * Fence emission
 254  */
 255 void r100_fence_ring_emit(struct radeon_device *rdev,
 256                           struct radeon_fence *fence)
 257 {
 258         /* Who ever call radeon_fence_emit should call ring_lock and ask
 259          * for enough space (today caller are ib schedule and buffer move) */
 260         /* Wait until IDLE & CLEAN */
 261         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 262         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
 263         /* Emit fence sequence & fire IRQ */
 264         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 265         radeon_ring_write(rdev, fence->seq);
 266         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 267         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 268 }
 269
 270
 271 /*
 272  * Writeback
 273  */
 274 int r100_wb_init(struct radeon_device *rdev)
 275 {
 276         int r;
 277
 278         if (rdev->wb.wb_obj == NULL) {
 279                 r = radeon_object_create(rdev, NULL, 4096,
 280                                          true,
 281                                          RADEON_GEM_DOMAIN_GTT,
 282                                          false, &rdev->wb.wb_obj);
 283                 if (r) {
 284                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
 285                         return r;
 286                 }
 287                 r = radeon_object_pin(rdev->wb.wb_obj,
 288                                       RADEON_GEM_DOMAIN_GTT,
 289                                       &rdev->wb.gpu_addr);
 290                 if (r) {
 291                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
 292                         return r;
 293                 }
 294                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 295                 if (r) {
 296                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
 297                         return r;
 298                 }
 299         }
 300         WREG32(0x774, rdev->wb.gpu_addr);
 301         WREG32(0x70C, rdev->wb.gpu_addr + 1024);
 302         WREG32(0x770, 0xff);
 303         return 0;
 304 }
 305
 306 void r100_wb_fini(struct radeon_device *rdev)
 307 {
 308         if (rdev->wb.wb_obj) {
 309                 radeon_object_kunmap(rdev->wb.wb_obj);
 310                 radeon_object_unpin(rdev->wb.wb_obj);
 311                 radeon_object_unref(&rdev->wb.wb_obj);
 312                 rdev->wb.wb = NULL;
 313                 rdev->wb.wb_obj = NULL;
 314         }
 315 }
 316
 317 int r100_copy_blit(struct radeon_device *rdev,
 318                    uint64_t src_offset,
 319                    uint64_t dst_offset,
 320                    unsigned num_pages,
 321                    struct radeon_fence *fence)
 322 {
 323         uint32_t cur_pages;
 324         uint32_t stride_bytes = PAGE_SIZE;
 325         uint32_t pitch;
 326         uint32_t stride_pixels;
 327         unsigned ndw;
 328         int num_loops;
 329         int r = 0;
 330
 331         /* radeon limited to 16k stride */
 332         stride_bytes &= 0x3fff;
 333         /* radeon pitch is /64 */
 334         pitch = stride_bytes / 64;
 335         stride_pixels = stride_bytes / 4;
 336         num_loops = DIV_ROUND_UP(num_pages, 8191);
 337
 338         /* Ask for enough room for blit + flush + fence */
 339         ndw = 64 + (10 * num_loops);
 340         r = radeon_ring_lock(rdev, ndw);
 341         if (r) {
 342                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 343                 return -EINVAL;
 344         }
 345         while (num_pages > 0) {
 346                 cur_pages = num_pages;
 347                 if (cur_pages > 8191) {
 348                         cur_pages = 8191;
 349                 }
 350                 num_pages -= cur_pages;
 351
 352                 /* pages are in Y direction - height
 353                    page width in X direction - width */
 354                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 355                 radeon_ring_write(rdev,
 356                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 357                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 358                                   RADEON_GMC_SRC_CLIPPING |
 359                                   RADEON_GMC_DST_CLIPPING |
 360                                   RADEON_GMC_BRUSH_NONE |
 361                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 362                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 363                                   RADEON_ROP3_S |
 364                                   RADEON_DP_SRC_SOURCE_MEMORY |
 365                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 366                                   RADEON_GMC_WR_MSK_DIS);
 367                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 368                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 369                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 370                 radeon_ring_write(rdev, 0);
 371                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 372                 radeon_ring_write(rdev, num_pages);
 373                 radeon_ring_write(rdev, num_pages);
 374                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 375         }
 376         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 377         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 378         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 379         radeon_ring_write(rdev,
 380                           RADEON_WAIT_2D_IDLECLEAN |
 381                           RADEON_WAIT_HOST_IDLECLEAN |
 382                           RADEON_WAIT_DMA_GUI_IDLE);
 383         if (fence) {
 384                 r = radeon_fence_emit(rdev, fence);
 385         }
 386         radeon_ring_unlock_commit(rdev);
 387         return r;
 388 }
 389
 390
 391 /*
 392  * CP
 393  */
 394 void r100_ring_start(struct radeon_device *rdev)
 395 {
 396         int r;
 397
 398         r = radeon_ring_lock(rdev, 2);
 399         if (r) {
 400                 return;
 401         }
 402         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 403         radeon_ring_write(rdev,
 404                           RADEON_ISYNC_ANY2D_IDLE3D |
 405                           RADEON_ISYNC_ANY3D_IDLE2D |
 406                           RADEON_ISYNC_WAIT_IDLEGUI |
 407                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 408         radeon_ring_unlock_commit(rdev);
 409 }
 410
 411 static void r100_cp_load_microcode(struct radeon_device *rdev)
 412 {
 413         int i;
 414
 415         if (r100_gui_wait_for_idle(rdev)) {
 416                 printk(KERN_WARNING "Failed to wait GUI idle while "
 417                        "programming pipes. Bad things might happen.\n");
 418         }
 419
 420         WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 421         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 422             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 423             (rdev->family == CHIP_RS200)) {
 424                 DRM_INFO("Loading R100 Microcode\n");
 425                 for (i = 0; i < 256; i++) {
 426                         WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
 427                         WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
 428                 }
 429         } else if ((rdev->family == CHIP_R200) ||
 430                    (rdev->family == CHIP_RV250) ||
 431                    (rdev->family == CHIP_RV280) ||
 432                    (rdev->family == CHIP_RS300)) {
 433                 DRM_INFO("Loading R200 Microcode\n");
 434                 for (i = 0; i < 256; i++) {
 435                         WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
 436                         WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
 437                 }
 438         } else if ((rdev->family == CHIP_R300) ||
 439                    (rdev->family == CHIP_R350) ||
 440                    (rdev->family == CHIP_RV350) ||
 441                    (rdev->family == CHIP_RV380) ||
 442                    (rdev->family == CHIP_RS400) ||
 443                    (rdev->family == CHIP_RS480)) {
 444                 DRM_INFO("Loading R300 Microcode\n");
 445                 for (i = 0; i < 256; i++) {
 446                         WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
 447                         WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
 448                 }
 449         } else if ((rdev->family == CHIP_R420) ||
 450                    (rdev->family == CHIP_R423) ||
 451                    (rdev->family == CHIP_RV410)) {
 452                 DRM_INFO("Loading R400 Microcode\n");
 453                 for (i = 0; i < 256; i++) {
 454                         WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
 455                         WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
 456                 }
 457         } else if ((rdev->family == CHIP_RS690) ||
 458                    (rdev->family == CHIP_RS740)) {
 459                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 460                 for (i = 0; i < 256; i++) {
 461                         WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
 462                         WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
 463                 }
 464         } else if (rdev->family == CHIP_RS600) {
 465                 DRM_INFO("Loading RS600 Microcode\n");
 466                 for (i = 0; i < 256; i++) {
 467                         WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
 468                         WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
 469                 }
 470         } else if ((rdev->family == CHIP_RV515) ||
 471                    (rdev->family == CHIP_R520) ||
 472                    (rdev->family == CHIP_RV530) ||
 473                    (rdev->family == CHIP_R580) ||
 474                    (rdev->family == CHIP_RV560) ||
 475                    (rdev->family == CHIP_RV570)) {
 476                 DRM_INFO("Loading R500 Microcode\n");
 477                 for (i = 0; i < 256; i++) {
 478                         WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
 479                         WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
 480                 }
 481         }
 482 }
 483
 484 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 485 {
 486         unsigned rb_bufsz;
 487         unsigned rb_blksz;
 488         unsigned max_fetch;
 489         unsigned pre_write_timer;
 490         unsigned pre_write_limit;
 491         unsigned indirect2_start;
 492         unsigned indirect1_start;
 493         uint32_t tmp;
 494         int r;
 495
 496         if (r100_debugfs_cp_init(rdev)) {
 497                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 498         }
 499         /* Reset CP */
 500         tmp = RREG32(RADEON_CP_CSQ_STAT);
 501         if ((tmp & (1 << 31))) {
 502                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 503                 WREG32(RADEON_CP_CSQ_MODE, 0);
 504                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 505                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 506                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 507                 mdelay(2);
 508                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 509                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 510                 mdelay(2);
 511                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 512                 if ((tmp & (1 << 31))) {
 513                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 514                 }
 515         } else {
 516                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 517         }
 518         /* Align ring size */
 519         rb_bufsz = drm_order(ring_size / 8);
 520         ring_size = (1 << (rb_bufsz + 1)) * 4;
 521         r100_cp_load_microcode(rdev);
 522         r = radeon_ring_init(rdev, ring_size);
 523         if (r) {
 524                 return r;
 525         }
 526         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 527          * the rptr copy in system ram */
 528         rb_blksz = 9;
 529         /* cp will read 128bytes at a time (4 dwords) */
 530         max_fetch = 1;
 531         rdev->cp.align_mask = 16 - 1;
 532         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 533         pre_write_timer = 64;
 534         /* Force CP_RB_WPTR write if written more than one time before the
 535          * delay expire
 536          */
 537         pre_write_limit = 0;
 538         /* Setup the cp cache like this (cache size is 96 dwords) :
 539          *      RING            0  to 15
 540          *      INDIRECT1       16 to 79
 541          *      INDIRECT2       80 to 95
 542          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 543          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 544          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 545          * Idea being that most of the gpu cmd will be through indirect1 buffer
 546          * so it gets the bigger cache.
 547          */
 548         indirect2_start = 80;
 549         indirect1_start = 16;
 550         /* cp setup */
 551         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 552         WREG32(RADEON_CP_RB_CNTL,
 553 #ifdef __BIG_ENDIAN
 554                RADEON_BUF_SWAP_32BIT |
 555 #endif
 556                REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 557                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 558                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 559                RADEON_RB_NO_UPDATE);
 560         /* Set ring address */
 561         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 562         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 563         /* Force read & write ptr to 0 */
 564         tmp = RREG32(RADEON_CP_RB_CNTL);
 565         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 566         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 567         WREG32(RADEON_CP_RB_WPTR, 0);
 568         WREG32(RADEON_CP_RB_CNTL, tmp);
 569         udelay(10);
 570         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 571         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 572         /* Set cp mode to bus mastering & enable cp*/
 573         WREG32(RADEON_CP_CSQ_MODE,
 574                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 575                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 576         WREG32(0x718, 0);
 577         WREG32(0x744, 0x00004D4D);
 578         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 579         radeon_ring_start(rdev);
 580         r = radeon_ring_test(rdev);
 581         if (r) {
 582                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 583                 return r;
 584         }
 585         rdev->cp.ready = true;
 586         return 0;
 587 }
 588
 589 void r100_cp_fini(struct radeon_device *rdev)
 590 {
 591         /* Disable ring */
 592         rdev->cp.ready = false;
 593         WREG32(RADEON_CP_CSQ_CNTL, 0);
 594         radeon_ring_fini(rdev);
 595         DRM_INFO("radeon: cp finalized\n");
 596 }
 597
 598 void r100_cp_disable(struct radeon_device *rdev)
 599 {
 600         /* Disable ring */
 601         rdev->cp.ready = false;
 602         WREG32(RADEON_CP_CSQ_MODE, 0);
 603         WREG32(RADEON_CP_CSQ_CNTL, 0);
 604         if (r100_gui_wait_for_idle(rdev)) {
 605                 printk(KERN_WARNING "Failed to wait GUI idle while "
 606                        "programming pipes. Bad things might happen.\n");
 607         }
 608 }
 609
 610 int r100_cp_reset(struct radeon_device *rdev)
 611 {
 612         uint32_t tmp;
 613         bool reinit_cp;
 614         int i;
 615
 616         reinit_cp = rdev->cp.ready;
 617         rdev->cp.ready = false;
 618         WREG32(RADEON_CP_CSQ_MODE, 0);
 619         WREG32(RADEON_CP_CSQ_CNTL, 0);
 620         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 621         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 622         udelay(200);
 623         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 624         /* Wait to prevent race in RBBM_STATUS */
 625         mdelay(1);
 626         for (i = 0; i < rdev->usec_timeout; i++) {
 627                 tmp = RREG32(RADEON_RBBM_STATUS);
 628                 if (!(tmp & (1 << 16))) {
 629                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 630                                  tmp);
 631                         if (reinit_cp) {
 632                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 633                         }
 634                         return 0;
 635                 }
 636                 DRM_UDELAY(1);
 637         }
 638         tmp = RREG32(RADEON_RBBM_STATUS);
 639         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 640         return -1;
 641 }
 642
 643
 644 /*
 645  * CS functions
 646  */
 647 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 648                           struct radeon_cs_packet *pkt,
 649                           const unsigned *auth, unsigned n,
 650                           radeon_packet0_check_t check)
 651 {
 652         unsigned reg;
 653         unsigned i, j, m;
 654         unsigned idx;
 655         int r;
 656
 657         idx = pkt->idx + 1;
 658         reg = pkt->reg;
 659         /* Check that register fall into register range
 660          * determined by the number of entry (n) in the
 661          * safe register bitmap.
 662          */
 663         if (pkt->one_reg_wr) {
 664                 if ((reg >> 7) > n) {
 665                         return -EINVAL;
 666                 }
 667         } else {
 668                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 669                         return -EINVAL;
 670                 }
 671         }
 672         for (i = 0; i <= pkt->count; i++, idx++) {
 673                 j = (reg >> 7);
 674                 m = 1 << ((reg >> 2) & 31);
 675                 if (auth[j] & m) {
 676                         r = check(p, pkt, idx, reg);
 677                         if (r) {
 678                                 return r;
 679                         }
 680                 }
 681                 if (pkt->one_reg_wr) {
 682                         if (!(auth[j] & m)) {
 683                                 break;
 684                         }
 685                 } else {
 686                         reg += 4;
 687                 }
 688         }
 689         return 0;
 690 }
 691
 692 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 693                          struct radeon_cs_packet *pkt)
 694 {
 695         struct radeon_cs_chunk *ib_chunk;
 696         volatile uint32_t *ib;
 697         unsigned i;
 698         unsigned idx;
 699
 700         ib = p->ib->ptr;
 701         ib_chunk = &p->chunks[p->chunk_ib_idx];
 702         idx = pkt->idx;
 703         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 704                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 705         }
 706 }
 707
 708 /**
 709  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 710  * @parser:     parser structure holding parsing context.
 711  * @pkt:        where to store packet informations
 712  *
 713  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 714  * if packet is bigger than remaining ib size. or if packets is unknown.
 715  **/
 716 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 717                          struct radeon_cs_packet *pkt,
 718                          unsigned idx)
 719 {
 720         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 721         uint32_t header = ib_chunk->kdata[idx];
 722
 723         if (idx >= ib_chunk->length_dw) {
 724                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 725                           idx, ib_chunk->length_dw);
 726                 return -EINVAL;
 727         }
 728         pkt->idx = idx;
 729         pkt->type = CP_PACKET_GET_TYPE(header);
 730         pkt->count = CP_PACKET_GET_COUNT(header);
 731         switch (pkt->type) {
 732         case PACKET_TYPE0:
 733                 pkt->reg = CP_PACKET0_GET_REG(header);
 734                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 735                 break;
 736         case PACKET_TYPE3:
 737                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 738                 break;
 739         case PACKET_TYPE2:
 740                 pkt->count = -1;
 741                 break;
 742         default:
 743                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 744                 return -EINVAL;
 745         }
 746         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 747                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 748                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 749                 return -EINVAL;
 750         }
 751         return 0;
 752 }
 753
 754 /**
 755  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 756  * @parser:             parser structure holding parsing context.
 757  *
 758  * Userspace sends a special sequence for VLINE waits.
 759  * PACKET0 - VLINE_START_END + value
 760  * PACKET0 - WAIT_UNTIL +_value
 761  * RELOC (P3) - crtc_id in reloc.
 762  *
 763  * This function parses this and relocates the VLINE START END
 764  * and WAIT UNTIL packets to the correct crtc.
 765  * It also detects a switched off crtc and nulls out the
 766  * wait in that case.
 767  */
 768 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 769 {
 770         struct radeon_cs_chunk *ib_chunk;
 771         struct drm_mode_object *obj;
 772         struct drm_crtc *crtc;
 773         struct radeon_crtc *radeon_crtc;
 774         struct radeon_cs_packet p3reloc, waitreloc;
 775         int crtc_id;
 776         int r;
 777         uint32_t header, h_idx, reg;
 778
 779         ib_chunk = &p->chunks[p->chunk_ib_idx];
 780
 781         /* parse the wait until */
 782         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 783         if (r)
 784                 return r;
 785
 786         /* check its a wait until and only 1 count */
 787         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 788             waitreloc.count != 0) {
 789                 DRM_ERROR("vline wait had illegal wait until segment\n");
 790                 r = -EINVAL;
 791                 return r;
 792         }
 793
 794         if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
 795                 DRM_ERROR("vline wait had illegal wait until\n");
 796                 r = -EINVAL;
 797                 return r;
 798         }
 799
 800         /* jump over the NOP */
 801         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 802         if (r)
 803                 return r;
 804
 805         h_idx = p->idx - 2;
 806         p->idx += waitreloc.count;
 807         p->idx += p3reloc.count;
 808
 809         header = ib_chunk->kdata[h_idx];
 810         crtc_id = ib_chunk->kdata[h_idx + 5];
 811         reg = ib_chunk->kdata[h_idx] >> 2;
 812         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 813         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 814         if (!obj) {
 815                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 816                 r = -EINVAL;
 817                 goto out;
 818         }
 819         crtc = obj_to_crtc(obj);
 820         radeon_crtc = to_radeon_crtc(crtc);
 821         crtc_id = radeon_crtc->crtc_id;
 822
 823         if (!crtc->enabled) {
 824                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 825                 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
 826                 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
 827         } else if (crtc_id == 1) {
 828                 switch (reg) {
 829                 case AVIVO_D1MODE_VLINE_START_END:
 830                         header &= R300_CP_PACKET0_REG_MASK;
 831                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 832                         break;
 833                 case RADEON_CRTC_GUI_TRIG_VLINE:
 834                         header &= R300_CP_PACKET0_REG_MASK;
 835                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 836                         break;
 837                 default:
 838                         DRM_ERROR("unknown crtc reloc\n");
 839                         r = -EINVAL;
 840                         goto out;
 841                 }
 842                 ib_chunk->kdata[h_idx] = header;
 843                 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 844         }
 845 out:
 846         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
 847         return r;
 848 }
 849
 850 /**
 851  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 852  * @parser:             parser structure holding parsing context.
 853  * @data:               pointer to relocation data
 854  * @offset_start:       starting offset
 855  * @offset_mask:        offset mask (to align start offset on)
 856  * @reloc:              reloc informations
 857  *
 858  * Check next packet is relocation packet3, do bo validation and compute
 859  * GPU offset using the provided start.
 860  **/
 861 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 862                               struct radeon_cs_reloc **cs_reloc)
 863 {
 864         struct radeon_cs_chunk *ib_chunk;
 865         struct radeon_cs_chunk *relocs_chunk;
 866         struct radeon_cs_packet p3reloc;
 867         unsigned idx;
 868         int r;
 869
 870         if (p->chunk_relocs_idx == -1) {
 871                 DRM_ERROR("No relocation chunk !\n");
 872                 return -EINVAL;
 873         }
 874         *cs_reloc = NULL;
 875         ib_chunk = &p->chunks[p->chunk_ib_idx];
 876         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 877         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 878         if (r) {
 879                 return r;
 880         }
 881         p->idx += p3reloc.count + 2;
 882         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 883                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 884                           p3reloc.idx);
 885                 r100_cs_dump_packet(p, &p3reloc);
 886                 return -EINVAL;
 887         }
 888         idx = ib_chunk->kdata[p3reloc.idx + 1];
 889         if (idx >= relocs_chunk->length_dw) {
 890                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 891                           idx, relocs_chunk->length_dw);
 892                 r100_cs_dump_packet(p, &p3reloc);
 893                 return -EINVAL;
 894         }
 895         /* FIXME: we assume reloc size is 4 dwords */
 896         *cs_reloc = p->relocs_ptr[(idx / 4)];
 897         return 0;
 898 }
 899
 900 static int r100_packet0_check(struct radeon_cs_parser *p,
 901                               struct radeon_cs_packet *pkt)
 902 {
 903         struct radeon_cs_chunk *ib_chunk;
 904         struct radeon_cs_reloc *reloc;
 905         volatile uint32_t *ib;
 906         uint32_t tmp;
 907         unsigned reg;
 908         unsigned i;
 909         unsigned idx;
 910         bool onereg;
 911         int r;
 912
 913         ib = p->ib->ptr;
 914         ib_chunk = &p->chunks[p->chunk_ib_idx];
 915         idx = pkt->idx + 1;
 916         reg = pkt->reg;
 917         onereg = false;
 918         if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
 919                 onereg = true;
 920         }
 921         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 922                 switch (reg) {
 923                 case RADEON_CRTC_GUI_TRIG_VLINE:
 924                         r = r100_cs_packet_parse_vline(p);
 925                         if (r) {
 926                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 927                                                 idx, reg);
 928                                 r100_cs_dump_packet(p, pkt);
 929                                 return r;
 930                         }
 931                         break;
 932                 /* FIXME: only allow PACKET3 blit? easier to check for out of
 933                  * range access */
 934                 case RADEON_DST_PITCH_OFFSET:
 935                 case RADEON_SRC_PITCH_OFFSET:
 936                         r = r100_cs_packet_next_reloc(p, &reloc);
 937                         if (r) {
 938                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 939                                           idx, reg);
 940                                 r100_cs_dump_packet(p, pkt);
 941                                 return r;
 942                         }
 943                         tmp = ib_chunk->kdata[idx] & 0x003fffff;
 944                         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
 945                         ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
 946                         break;
 947                 case RADEON_RB3D_DEPTHOFFSET:
 948                 case RADEON_RB3D_COLOROFFSET:
 949                 case R300_RB3D_COLOROFFSET0:
 950                 case R300_ZB_DEPTHOFFSET:
 951                 case R200_PP_TXOFFSET_0:
 952                 case R200_PP_TXOFFSET_1:
 953                 case R200_PP_TXOFFSET_2:
 954                 case R200_PP_TXOFFSET_3:
 955                 case R200_PP_TXOFFSET_4:
 956                 case R200_PP_TXOFFSET_5:
 957                 case RADEON_PP_TXOFFSET_0:
 958                 case RADEON_PP_TXOFFSET_1:
 959                 case RADEON_PP_TXOFFSET_2:
 960                 case R300_TX_OFFSET_0:
 961                 case R300_TX_OFFSET_0+4:
 962                 case R300_TX_OFFSET_0+8:
 963                 case R300_TX_OFFSET_0+12:
 964                 case R300_TX_OFFSET_0+16:
 965                 case R300_TX_OFFSET_0+20:
 966                 case R300_TX_OFFSET_0+24:
 967                 case R300_TX_OFFSET_0+28:
 968                 case R300_TX_OFFSET_0+32:
 969                 case R300_TX_OFFSET_0+36:
 970                 case R300_TX_OFFSET_0+40:
 971                 case R300_TX_OFFSET_0+44:
 972                 case R300_TX_OFFSET_0+48:
 973                 case R300_TX_OFFSET_0+52:
 974                 case R300_TX_OFFSET_0+56:
 975                 case R300_TX_OFFSET_0+60:
 976                         /* rn50 has no 3D engine so fail on any 3d setup */
 977                         if (ASIC_IS_RN50(p->rdev)) {
 978                                 DRM_ERROR("attempt to use RN50 3D engine failed\n");
 979                                 return -EINVAL;
 980                         }
 981                         r = r100_cs_packet_next_reloc(p, &reloc);
 982                         if (r) {
 983                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 984                                           idx, reg);
 985                                 r100_cs_dump_packet(p, pkt);
 986                                 return r;
 987                         }
 988                         ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
 989                         break;
 990                 default:
 991                         /* FIXME: we don't want to allow anyothers packet */
 992                         break;
 993                 }
 994                 if (onereg) {
 995                         /* FIXME: forbid onereg write to register on relocate */
 996                         break;
 997                 }
 998         }
 999         return 0;
1000 }
1001
1002 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1003                                          struct radeon_cs_packet *pkt,
1004                                          struct radeon_object *robj)
1005 {
1006         struct radeon_cs_chunk *ib_chunk;
1007         unsigned idx;
1008
1009         ib_chunk = &p->chunks[p->chunk_ib_idx];
1010         idx = pkt->idx + 1;
1011         if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1012                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1013                           "(need %u have %lu) !\n",
1014                           ib_chunk->kdata[idx+2] + 1,
1015                           radeon_object_size(robj));
1016                 return -EINVAL;
1017         }
1018         return 0;
1019 }
1020
1021 static int r100_packet3_check(struct radeon_cs_parser *p,
1022                               struct radeon_cs_packet *pkt)
1023 {
1024         struct radeon_cs_chunk *ib_chunk;
1025         struct radeon_cs_reloc *reloc;
1026         unsigned idx;
1027         unsigned i, c;
1028         volatile uint32_t *ib;
1029         int r;
1030
1031         ib = p->ib->ptr;
1032         ib_chunk = &p->chunks[p->chunk_ib_idx];
1033         idx = pkt->idx + 1;
1034         switch (pkt->opcode) {
1035         case PACKET3_3D_LOAD_VBPNTR:
1036                 c = ib_chunk->kdata[idx++];
1037                 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1038                         r = r100_cs_packet_next_reloc(p, &reloc);
1039                         if (r) {
1040                                 DRM_ERROR("No reloc for packet3 %d\n",
1041                                           pkt->opcode);
1042                                 r100_cs_dump_packet(p, pkt);
1043                                 return r;
1044                         }
1045                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1046                         r = r100_cs_packet_next_reloc(p, &reloc);
1047                         if (r) {
1048                                 DRM_ERROR("No reloc for packet3 %d\n",
1049                                           pkt->opcode);
1050                                 r100_cs_dump_packet(p, pkt);
1051                                 return r;
1052                         }
1053                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1054                 }
1055                 if (c & 1) {
1056                         r = r100_cs_packet_next_reloc(p, &reloc);
1057                         if (r) {
1058                                 DRM_ERROR("No reloc for packet3 %d\n",
1059                                           pkt->opcode);
1060                                 r100_cs_dump_packet(p, pkt);
1061                                 return r;
1062                         }
1063                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1064                 }
1065                 break;
1066         case PACKET3_INDX_BUFFER:
1067                 r = r100_cs_packet_next_reloc(p, &reloc);
1068                 if (r) {
1069                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1070                         r100_cs_dump_packet(p, pkt);
1071                         return r;
1072                 }
1073                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1074                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1075                 if (r) {
1076                         return r;
1077                 }
1078                 break;
1079         case 0x23:
1080                 /* FIXME: cleanup */
1081                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1082                 r = r100_cs_packet_next_reloc(p, &reloc);
1083                 if (r) {
1084                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1085                         r100_cs_dump_packet(p, pkt);
1086                         return r;
1087                 }
1088                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1089                 break;
1090         case PACKET3_3D_DRAW_IMMD:
1091                 /* triggers drawing using in-packet vertex data */
1092         case PACKET3_3D_DRAW_IMMD_2:
1093                 /* triggers drawing using in-packet vertex data */
1094         case PACKET3_3D_DRAW_VBUF_2:
1095                 /* triggers drawing of vertex buffers setup elsewhere */
1096         case PACKET3_3D_DRAW_INDX_2:
1097                 /* triggers drawing using indices to vertex buffer */
1098         case PACKET3_3D_DRAW_VBUF:
1099                 /* triggers drawing of vertex buffers setup elsewhere */
1100         case PACKET3_3D_DRAW_INDX:
1101                 /* triggers drawing using indices to vertex buffer */
1102         case PACKET3_NOP:
1103                 break;
1104         default:
1105                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1106                 return -EINVAL;
1107         }
1108         return 0;
1109 }
1110
1111 int r100_cs_parse(struct radeon_cs_parser *p)
1112 {
1113         struct radeon_cs_packet pkt;
1114         int r;
1115
1116         do {
1117                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1118                 if (r) {
1119                         return r;
1120                 }
1121                 p->idx += pkt.count + 2;
1122                 switch (pkt.type) {
1123                         case PACKET_TYPE0:
1124                                 r = r100_packet0_check(p, &pkt);
1125                                 break;
1126                         case PACKET_TYPE2:
1127                                 break;
1128                         case PACKET_TYPE3:
1129                                 r = r100_packet3_check(p, &pkt);
1130                                 break;
1131                         default:
1132                                 DRM_ERROR("Unknown packet type %d !\n",
1133                                           pkt.type);
1134                                 return -EINVAL;
1135                 }
1136                 if (r) {
1137                         return r;
1138                 }
1139         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1140         return 0;
1141 }
1142
1143
1144 /*
1145  * Global GPU functions
1146  */
1147 void r100_errata(struct radeon_device *rdev)
1148 {
1149         rdev->pll_errata = 0;
1150
1151         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1152                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1153         }
1154
1155         if (rdev->family == CHIP_RV100 ||
1156             rdev->family == CHIP_RS100 ||
1157             rdev->family == CHIP_RS200) {
1158                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1159         }
1160 }
1161
1162 /* Wait for vertical sync on primary CRTC */
1163 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1164 {
1165         uint32_t crtc_gen_cntl, tmp;
1166         int i;
1167
1168         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1169         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1170             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1171                 return;
1172         }
1173         /* Clear the CRTC_VBLANK_SAVE bit */
1174         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1175         for (i = 0; i < rdev->usec_timeout; i++) {
1176                 tmp = RREG32(RADEON_CRTC_STATUS);
1177                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1178                         return;
1179                 }
1180                 DRM_UDELAY(1);
1181         }
1182 }
1183
1184 /* Wait for vertical sync on secondary CRTC */
1185 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1186 {
1187         uint32_t crtc2_gen_cntl, tmp;
1188         int i;
1189
1190         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1191         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1192             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1193                 return;
1194
1195         /* Clear the CRTC_VBLANK_SAVE bit */
1196         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1197         for (i = 0; i < rdev->usec_timeout; i++) {
1198                 tmp = RREG32(RADEON_CRTC2_STATUS);
1199                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1200                         return;
1201                 }
1202                 DRM_UDELAY(1);
1203         }
1204 }
1205
1206 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1207 {
1208         unsigned i;
1209         uint32_t tmp;
1210
1211         for (i = 0; i < rdev->usec_timeout; i++) {
1212                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1213                 if (tmp >= n) {
1214                         return 0;
1215                 }
1216                 DRM_UDELAY(1);
1217         }
1218         return -1;
1219 }
1220
1221 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1222 {
1223         unsigned i;
1224         uint32_t tmp;
1225
1226         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1227                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1228                        " Bad things might happen.\n");
1229         }
1230         for (i = 0; i < rdev->usec_timeout; i++) {
1231                 tmp = RREG32(RADEON_RBBM_STATUS);
1232                 if (!(tmp & (1 << 31))) {
1233                         return 0;
1234                 }
1235                 DRM_UDELAY(1);
1236         }
1237         return -1;
1238 }
1239
1240 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1241 {
1242         unsigned i;
1243         uint32_t tmp;
1244
1245         for (i = 0; i < rdev->usec_timeout; i++) {
1246                 /* read MC_STATUS */
1247                 tmp = RREG32(0x0150);
1248                 if (tmp & (1 << 2)) {
1249                         return 0;
1250                 }
1251                 DRM_UDELAY(1);
1252         }
1253         return -1;
1254 }
1255
1256 void r100_gpu_init(struct radeon_device *rdev)
1257 {
1258         /* TODO: anythings to do here ? pipes ? */
1259         r100_hdp_reset(rdev);
1260 }
1261
1262 void r100_hdp_reset(struct radeon_device *rdev)
1263 {
1264         uint32_t tmp;
1265
1266         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1267         tmp |= (7 << 28);
1268         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1269         (void)RREG32(RADEON_HOST_PATH_CNTL);
1270         udelay(200);
1271         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1272         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1273         (void)RREG32(RADEON_HOST_PATH_CNTL);
1274 }
1275
1276 int r100_rb2d_reset(struct radeon_device *rdev)
1277 {
1278         uint32_t tmp;
1279         int i;
1280
1281         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1282         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1283         udelay(200);
1284         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1285         /* Wait to prevent race in RBBM_STATUS */
1286         mdelay(1);
1287         for (i = 0; i < rdev->usec_timeout; i++) {
1288                 tmp = RREG32(RADEON_RBBM_STATUS);
1289                 if (!(tmp & (1 << 26))) {
1290                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1291                                  tmp);
1292                         return 0;
1293                 }
1294                 DRM_UDELAY(1);
1295         }
1296         tmp = RREG32(RADEON_RBBM_STATUS);
1297         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1298         return -1;
1299 }
1300
1301 int r100_gpu_reset(struct radeon_device *rdev)
1302 {
1303         uint32_t status;
1304
1305         /* reset order likely matter */
1306         status = RREG32(RADEON_RBBM_STATUS);
1307         /* reset HDP */
1308         r100_hdp_reset(rdev);
1309         /* reset rb2d */
1310         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1311                 r100_rb2d_reset(rdev);
1312         }
1313         /* TODO: reset 3D engine */
1314         /* reset CP */
1315         status = RREG32(RADEON_RBBM_STATUS);
1316         if (status & (1 << 16)) {
1317                 r100_cp_reset(rdev);
1318         }
1319         /* Check if GPU is idle */
1320         status = RREG32(RADEON_RBBM_STATUS);
1321         if (status & (1 << 31)) {
1322                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1323                 return -1;
1324         }
1325         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1326         return 0;
1327 }
1328
1329
1330 /*
1331  * VRAM info
1332  */
1333 static void r100_vram_get_type(struct radeon_device *rdev)
1334 {
1335         uint32_t tmp;
1336
1337         rdev->mc.vram_is_ddr = false;
1338         if (rdev->flags & RADEON_IS_IGP)
1339                 rdev->mc.vram_is_ddr = true;
1340         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1341                 rdev->mc.vram_is_ddr = true;
1342         if ((rdev->family == CHIP_RV100) ||
1343             (rdev->family == CHIP_RS100) ||
1344             (rdev->family == CHIP_RS200)) {
1345                 tmp = RREG32(RADEON_MEM_CNTL);
1346                 if (tmp & RV100_HALF_MODE) {
1347                         rdev->mc.vram_width = 32;
1348                 } else {
1349                         rdev->mc.vram_width = 64;
1350                 }
1351                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1352                         rdev->mc.vram_width /= 4;
1353                         rdev->mc.vram_is_ddr = true;
1354                 }
1355         } else if (rdev->family <= CHIP_RV280) {
1356                 tmp = RREG32(RADEON_MEM_CNTL);
1357                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1358                         rdev->mc.vram_width = 128;
1359                 } else {
1360                         rdev->mc.vram_width = 64;
1361                 }
1362         } else {
1363                 /* newer IGPs */
1364                 rdev->mc.vram_width = 128;
1365         }
1366 }
1367
1368 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1369 {
1370         u32 aper_size;
1371         u8 byte;
1372
1373         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1374
1375         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1376          * that is has the 2nd generation multifunction PCI interface
1377          */
1378         if (rdev->family == CHIP_RV280 ||
1379             rdev->family >= CHIP_RV350) {
1380                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1381                        ~RADEON_HDP_APER_CNTL);
1382                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1383                 return aper_size * 2;
1384         }
1385
1386         /* Older cards have all sorts of funny issues to deal with. First
1387          * check if it's a multifunction card by reading the PCI config
1388          * header type... Limit those to one aperture size
1389          */
1390         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1391         if (byte & 0x80) {
1392                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1393                 DRM_INFO("Limiting VRAM to one aperture\n");
1394                 return aper_size;
1395         }
1396
1397         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1398          * have set it up. We don't write this as it's broken on some ASICs but
1399          * we expect the BIOS to have done the right thing (might be too optimistic...)
1400          */
1401         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1402                 return aper_size * 2;
1403         return aper_size;
1404 }
1405
1406 void r100_vram_init_sizes(struct radeon_device *rdev)
1407 {
1408         u64 config_aper_size;
1409         u32 accessible;
1410
1411         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1412
1413         if (rdev->flags & RADEON_IS_IGP) {
1414                 uint32_t tom;
1415                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1416                 tom = RREG32(RADEON_NB_TOM);
1417                 rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1418                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1419                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1420                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1421         } else {
1422                 rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1423                 /* Some production boards of m6 will report 0
1424                  * if it's 8 MB
1425                  */
1426                 if (rdev->mc.vram_size == 0) {
1427                         rdev->mc.vram_size = 8192 * 1024;
1428                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1429                 }
1430                 /* let driver place VRAM */
1431                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1432                  /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1433                   * Novell bug 204882 + along with lots of ubuntu ones */
1434                 if (config_aper_size > rdev->mc.vram_size)
1435                         rdev->mc.vram_size = config_aper_size;
1436         }
1437
1438         /* work out accessible VRAM */
1439         accessible = r100_get_accessible_vram(rdev);
1440
1441         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1442         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1443
1444         if (accessible > rdev->mc.aper_size)
1445                 accessible = rdev->mc.aper_size;
1446
1447         if (rdev->mc.vram_size > rdev->mc.aper_size)
1448                 rdev->mc.vram_size = rdev->mc.aper_size;
1449 }
1450
1451 void r100_vram_info(struct radeon_device *rdev)
1452 {
1453         r100_vram_get_type(rdev);
1454
1455         r100_vram_init_sizes(rdev);
1456 }
1457
1458
1459 /*
1460  * Indirect registers accessor
1461  */
1462 void r100_pll_errata_after_index(struct radeon_device *rdev)
1463 {
1464         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1465                 return;
1466         }
1467         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1468         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1469 }
1470
1471 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1472 {
1473         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1474          * or the chip could hang on a subsequent access
1475          */
1476         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1477                 udelay(5000);
1478         }
1479
1480         /* This function is required to workaround a hardware bug in some (all?)
1481          * revisions of the R300.  This workaround should be called after every
1482          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1483          * may not be correct.
1484          */
1485         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1486                 uint32_t save, tmp;
1487
1488                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1489                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1490                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1491                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1492                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1493         }
1494 }
1495
1496 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1497 {
1498         uint32_t data;
1499
1500         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1501         r100_pll_errata_after_index(rdev);
1502         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1503         r100_pll_errata_after_data(rdev);
1504         return data;
1505 }
1506
1507 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1508 {
1509         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1510         r100_pll_errata_after_index(rdev);
1511         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1512         r100_pll_errata_after_data(rdev);
1513 }
1514
1515 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1516 {
1517         if (reg < 0x10000)
1518                 return readl(((void __iomem *)rdev->rmmio) + reg);
1519         else {
1520                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1521                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1522         }
1523 }
1524
1525 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1526 {
1527         if (reg < 0x10000)
1528                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1529         else {
1530                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1531                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1532         }
1533 }
1534
1535 int r100_init(struct radeon_device *rdev)
1536 {
1537         return 0;
1538 }
1539
1540 /*
1541  * Debugfs info
1542  */
1543 #if defined(CONFIG_DEBUG_FS)
1544 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1545 {
1546         struct drm_info_node *node = (struct drm_info_node *) m->private;
1547         struct drm_device *dev = node->minor->dev;
1548         struct radeon_device *rdev = dev->dev_private;
1549         uint32_t reg, value;
1550         unsigned i;
1551
1552         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1553         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1554         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1555         for (i = 0; i < 64; i++) {
1556                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1557                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1558                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1559                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1560                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1561         }
1562         return 0;
1563 }
1564
1565 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1566 {
1567         struct drm_info_node *node = (struct drm_info_node *) m->private;
1568         struct drm_device *dev = node->minor->dev;
1569         struct radeon_device *rdev = dev->dev_private;
1570         uint32_t rdp, wdp;
1571         unsigned count, i, j;
1572
1573         radeon_ring_free_size(rdev);
1574         rdp = RREG32(RADEON_CP_RB_RPTR);
1575         wdp = RREG32(RADEON_CP_RB_WPTR);
1576         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1577         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1578         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1579         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1580         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1581         seq_printf(m, "%u dwords in ring\n", count);
1582         for (j = 0; j <= count; j++) {
1583                 i = (rdp + j) & rdev->cp.ptr_mask;
1584                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1585         }
1586         return 0;
1587 }
1588
1589
1590 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1591 {
1592         struct drm_info_node *node = (struct drm_info_node *) m->private;
1593         struct drm_device *dev = node->minor->dev;
1594         struct radeon_device *rdev = dev->dev_private;
1595         uint32_t csq_stat, csq2_stat, tmp;
1596         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1597         unsigned i;
1598
1599         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1600         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1601         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1602         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1603         r_rptr = (csq_stat >> 0) & 0x3ff;
1604         r_wptr = (csq_stat >> 10) & 0x3ff;
1605         ib1_rptr = (csq_stat >> 20) & 0x3ff;
1606         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1607         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1608         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1609         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1610         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1611         seq_printf(m, "Ring rptr %u\n", r_rptr);
1612         seq_printf(m, "Ring wptr %u\n", r_wptr);
1613         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1614         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1615         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1616         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1617         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1618          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1619         seq_printf(m, "Ring fifo:\n");
1620         for (i = 0; i < 256; i++) {
1621                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1622                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1623                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1624         }
1625         seq_printf(m, "Indirect1 fifo:\n");
1626         for (i = 256; i <= 512; i++) {
1627                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1628                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1629                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1630         }
1631         seq_printf(m, "Indirect2 fifo:\n");
1632         for (i = 640; i < ib1_wptr; i++) {
1633                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1634                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1635                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1636         }
1637         return 0;
1638 }
1639
1640 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1641 {
1642         struct drm_info_node *node = (struct drm_info_node *) m->private;
1643         struct drm_device *dev = node->minor->dev;
1644         struct radeon_device *rdev = dev->dev_private;
1645         uint32_t tmp;
1646
1647         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1648         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1649         tmp = RREG32(RADEON_MC_FB_LOCATION);
1650         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1651         tmp = RREG32(RADEON_BUS_CNTL);
1652         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1653         tmp = RREG32(RADEON_MC_AGP_LOCATION);
1654         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1655         tmp = RREG32(RADEON_AGP_BASE);
1656         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1657         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1658         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1659         tmp = RREG32(0x01D0);
1660         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1661         tmp = RREG32(RADEON_AIC_LO_ADDR);
1662         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1663         tmp = RREG32(RADEON_AIC_HI_ADDR);
1664         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1665         tmp = RREG32(0x01E4);
1666         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1667         return 0;
1668 }
1669
1670 static struct drm_info_list r100_debugfs_rbbm_list[] = {
1671         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1672 };
1673
1674 static struct drm_info_list r100_debugfs_cp_list[] = {
1675         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1676         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1677 };
1678
1679 static struct drm_info_list r100_debugfs_mc_info_list[] = {
1680         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1681 };
1682 #endif
1683
1684 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1685 {
1686 #if defined(CONFIG_DEBUG_FS)
1687         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1688 #else
1689         return 0;
1690 #endif
1691 }
1692
1693 int r100_debugfs_cp_init(struct radeon_device *rdev)
1694 {
1695 #if defined(CONFIG_DEBUG_FS)
1696         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1697 #else
1698         return 0;
1699 #endif
1700 }
1701
1702 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1703 {
1704 #if defined(CONFIG_DEBUG_FS)
1705         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1706 #else
1707         return 0;
1708 #endif
1709 }