SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "r100d.h"
  35 #include "rs100d.h"
  36 #include "rv200d.h"
  37 #include "rv250d.h"
  38
  39 #include <linux/firmware.h>
  40 #include <linux/platform_device.h>
  41
  42 #include "r100_reg_safe.h"
  43 #include "rn50_reg_safe.h"
  44
  45 /* Firmware Names */
  46 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  47 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  48 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  49 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  50 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  51 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  52 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  53
  54 MODULE_FIRMWARE(FIRMWARE_R100);
  55 MODULE_FIRMWARE(FIRMWARE_R200);
  56 MODULE_FIRMWARE(FIRMWARE_R300);
  57 MODULE_FIRMWARE(FIRMWARE_R420);
  58 MODULE_FIRMWARE(FIRMWARE_RS690);
  59 MODULE_FIRMWARE(FIRMWARE_RS600);
  60 MODULE_FIRMWARE(FIRMWARE_R520);
  61
  62 #include "r100_track.h"
  63
  64 /* This files gather functions specifics to:
  65  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  66  */
  67
  68 /*
  69  * PCI GART
  70  */
  71 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  72 {
  73         /* TODO: can we do somethings here ? */
  74         /* It seems hw only cache one entry so we should discard this
  75          * entry otherwise if first GPU GART read hit this entry it
  76          * could end up in wrong address. */
  77 }
  78
  79 int r100_pci_gart_init(struct radeon_device *rdev)
  80 {
  81         int r;
  82
  83         if (rdev->gart.table.ram.ptr) {
  84                 WARN(1, "R100 PCI GART already initialized.\n");
  85                 return 0;
  86         }
  87         /* Initialize common gart structure */
  88         r = radeon_gart_init(rdev);
  89         if (r)
  90                 return r;
  91         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  92         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  93         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  94         return radeon_gart_table_ram_alloc(rdev);
  95 }
  96
  97 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
  98 void r100_enable_bm(struct radeon_device *rdev)
  99 {
 100         uint32_t tmp;
 101         /* Enable bus mastering */
 102         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 103         WREG32(RADEON_BUS_CNTL, tmp);
 104 }
 105
 106 int r100_pci_gart_enable(struct radeon_device *rdev)
 107 {
 108         uint32_t tmp;
 109
 110         /* discard memory request outside of configured range */
 111         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 112         WREG32(RADEON_AIC_CNTL, tmp);
 113         /* set address range for PCI address translate */
 114         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
 115         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 116         WREG32(RADEON_AIC_HI_ADDR, tmp);
 117         /* set PCI GART page-table base address */
 118         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 119         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 120         WREG32(RADEON_AIC_CNTL, tmp);
 121         r100_pci_gart_tlb_flush(rdev);
 122         rdev->gart.ready = true;
 123         return 0;
 124 }
 125
 126 void r100_pci_gart_disable(struct radeon_device *rdev)
 127 {
 128         uint32_t tmp;
 129
 130         /* discard memory request outside of configured range */
 131         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 132         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 133         WREG32(RADEON_AIC_LO_ADDR, 0);
 134         WREG32(RADEON_AIC_HI_ADDR, 0);
 135 }
 136
 137 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 138 {
 139         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 140                 return -EINVAL;
 141         }
 142         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 143         return 0;
 144 }
 145
 146 void r100_pci_gart_fini(struct radeon_device *rdev)
 147 {
 148         r100_pci_gart_disable(rdev);
 149         radeon_gart_table_ram_free(rdev);
 150         radeon_gart_fini(rdev);
 151 }
 152
 153 int r100_irq_set(struct radeon_device *rdev)
 154 {
 155         uint32_t tmp = 0;
 156
 157         if (rdev->irq.sw_int) {
 158                 tmp |= RADEON_SW_INT_ENABLE;
 159         }
 160         if (rdev->irq.crtc_vblank_int[0]) {
 161                 tmp |= RADEON_CRTC_VBLANK_MASK;
 162         }
 163         if (rdev->irq.crtc_vblank_int[1]) {
 164                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 165         }
 166         WREG32(RADEON_GEN_INT_CNTL, tmp);
 167         return 0;
 168 }
 169
 170 void r100_irq_disable(struct radeon_device *rdev)
 171 {
 172         u32 tmp;
 173
 174         WREG32(R_000040_GEN_INT_CNTL, 0);
 175         /* Wait and acknowledge irq */
 176         mdelay(1);
 177         tmp = RREG32(R_000044_GEN_INT_STATUS);
 178         WREG32(R_000044_GEN_INT_STATUS, tmp);
 179 }
 180
 181 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 182 {
 183         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 184         uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
 185                 RADEON_CRTC2_VBLANK_STAT;
 186
 187         if (irqs) {
 188                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 189         }
 190         return irqs & irq_mask;
 191 }
 192
 193 int r100_irq_process(struct radeon_device *rdev)
 194 {
 195         uint32_t status, msi_rearm;
 196
 197         status = r100_irq_ack(rdev);
 198         if (!status) {
 199                 return IRQ_NONE;
 200         }
 201         if (rdev->shutdown) {
 202                 return IRQ_NONE;
 203         }
 204         while (status) {
 205                 /* SW interrupt */
 206                 if (status & RADEON_SW_INT_TEST) {
 207                         radeon_fence_process(rdev);
 208                 }
 209                 /* Vertical blank interrupts */
 210                 if (status & RADEON_CRTC_VBLANK_STAT) {
 211                         drm_handle_vblank(rdev->ddev, 0);
 212                 }
 213                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 214                         drm_handle_vblank(rdev->ddev, 1);
 215                 }
 216                 status = r100_irq_ack(rdev);
 217         }
 218         if (rdev->msi_enabled) {
 219                 switch (rdev->family) {
 220                 case CHIP_RS400:
 221                 case CHIP_RS480:
 222                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 223                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 224                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 225                         break;
 226                 default:
 227                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 228                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 229                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 230                         break;
 231                 }
 232         }
 233         return IRQ_HANDLED;
 234 }
 235
 236 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 237 {
 238         if (crtc == 0)
 239                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 240         else
 241                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 242 }
 243
 244 void r100_fence_ring_emit(struct radeon_device *rdev,
 245                           struct radeon_fence *fence)
 246 {
 247         /* Who ever call radeon_fence_emit should call ring_lock and ask
 248          * for enough space (today caller are ib schedule and buffer move) */
 249         /* Wait until IDLE & CLEAN */
 250         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 251         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
 252         /* Emit fence sequence & fire IRQ */
 253         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 254         radeon_ring_write(rdev, fence->seq);
 255         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 256         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 257 }
 258
 259 int r100_wb_init(struct radeon_device *rdev)
 260 {
 261         int r;
 262
 263         if (rdev->wb.wb_obj == NULL) {
 264                 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
 265                                          true,
 266                                          RADEON_GEM_DOMAIN_GTT,
 267                                          false, &rdev->wb.wb_obj);
 268                 if (r) {
 269                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
 270                         return r;
 271                 }
 272                 r = radeon_object_pin(rdev->wb.wb_obj,
 273                                       RADEON_GEM_DOMAIN_GTT,
 274                                       &rdev->wb.gpu_addr);
 275                 if (r) {
 276                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
 277                         return r;
 278                 }
 279                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 280                 if (r) {
 281                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
 282                         return r;
 283                 }
 284         }
 285         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 286         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 287                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 288         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 289         return 0;
 290 }
 291
 292 void r100_wb_disable(struct radeon_device *rdev)
 293 {
 294         WREG32(R_000770_SCRATCH_UMSK, 0);
 295 }
 296
 297 void r100_wb_fini(struct radeon_device *rdev)
 298 {
 299         r100_wb_disable(rdev);
 300         if (rdev->wb.wb_obj) {
 301                 radeon_object_kunmap(rdev->wb.wb_obj);
 302                 radeon_object_unpin(rdev->wb.wb_obj);
 303                 radeon_object_unref(&rdev->wb.wb_obj);
 304                 rdev->wb.wb = NULL;
 305                 rdev->wb.wb_obj = NULL;
 306         }
 307 }
 308
 309 int r100_copy_blit(struct radeon_device *rdev,
 310                    uint64_t src_offset,
 311                    uint64_t dst_offset,
 312                    unsigned num_pages,
 313                    struct radeon_fence *fence)
 314 {
 315         uint32_t cur_pages;
 316         uint32_t stride_bytes = PAGE_SIZE;
 317         uint32_t pitch;
 318         uint32_t stride_pixels;
 319         unsigned ndw;
 320         int num_loops;
 321         int r = 0;
 322
 323         /* radeon limited to 16k stride */
 324         stride_bytes &= 0x3fff;
 325         /* radeon pitch is /64 */
 326         pitch = stride_bytes / 64;
 327         stride_pixels = stride_bytes / 4;
 328         num_loops = DIV_ROUND_UP(num_pages, 8191);
 329
 330         /* Ask for enough room for blit + flush + fence */
 331         ndw = 64 + (10 * num_loops);
 332         r = radeon_ring_lock(rdev, ndw);
 333         if (r) {
 334                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 335                 return -EINVAL;
 336         }
 337         while (num_pages > 0) {
 338                 cur_pages = num_pages;
 339                 if (cur_pages > 8191) {
 340                         cur_pages = 8191;
 341                 }
 342                 num_pages -= cur_pages;
 343
 344                 /* pages are in Y direction - height
 345                    page width in X direction - width */
 346                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 347                 radeon_ring_write(rdev,
 348                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 349                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 350                                   RADEON_GMC_SRC_CLIPPING |
 351                                   RADEON_GMC_DST_CLIPPING |
 352                                   RADEON_GMC_BRUSH_NONE |
 353                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 354                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 355                                   RADEON_ROP3_S |
 356                                   RADEON_DP_SRC_SOURCE_MEMORY |
 357                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 358                                   RADEON_GMC_WR_MSK_DIS);
 359                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 360                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 361                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 362                 radeon_ring_write(rdev, 0);
 363                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 364                 radeon_ring_write(rdev, num_pages);
 365                 radeon_ring_write(rdev, num_pages);
 366                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 367         }
 368         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 369         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 370         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 371         radeon_ring_write(rdev,
 372                           RADEON_WAIT_2D_IDLECLEAN |
 373                           RADEON_WAIT_HOST_IDLECLEAN |
 374                           RADEON_WAIT_DMA_GUI_IDLE);
 375         if (fence) {
 376                 r = radeon_fence_emit(rdev, fence);
 377         }
 378         radeon_ring_unlock_commit(rdev);
 379         return r;
 380 }
 381
 382 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 383 {
 384         unsigned i;
 385         u32 tmp;
 386
 387         for (i = 0; i < rdev->usec_timeout; i++) {
 388                 tmp = RREG32(R_000E40_RBBM_STATUS);
 389                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 390                         return 0;
 391                 }
 392                 udelay(1);
 393         }
 394         return -1;
 395 }
 396
 397 void r100_ring_start(struct radeon_device *rdev)
 398 {
 399         int r;
 400
 401         r = radeon_ring_lock(rdev, 2);
 402         if (r) {
 403                 return;
 404         }
 405         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 406         radeon_ring_write(rdev,
 407                           RADEON_ISYNC_ANY2D_IDLE3D |
 408                           RADEON_ISYNC_ANY3D_IDLE2D |
 409                           RADEON_ISYNC_WAIT_IDLEGUI |
 410                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 411         radeon_ring_unlock_commit(rdev);
 412 }
 413
 414
 415 /* Load the microcode for the CP */
 416 static int r100_cp_init_microcode(struct radeon_device *rdev)
 417 {
 418         struct platform_device *pdev;
 419         const char *fw_name = NULL;
 420         int err;
 421
 422         DRM_DEBUG("\n");
 423
 424         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 425         err = IS_ERR(pdev);
 426         if (err) {
 427                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 428                 return -EINVAL;
 429         }
 430         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 431             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 432             (rdev->family == CHIP_RS200)) {
 433                 DRM_INFO("Loading R100 Microcode\n");
 434                 fw_name = FIRMWARE_R100;
 435         } else if ((rdev->family == CHIP_R200) ||
 436                    (rdev->family == CHIP_RV250) ||
 437                    (rdev->family == CHIP_RV280) ||
 438                    (rdev->family == CHIP_RS300)) {
 439                 DRM_INFO("Loading R200 Microcode\n");
 440                 fw_name = FIRMWARE_R200;
 441         } else if ((rdev->family == CHIP_R300) ||
 442                    (rdev->family == CHIP_R350) ||
 443                    (rdev->family == CHIP_RV350) ||
 444                    (rdev->family == CHIP_RV380) ||
 445                    (rdev->family == CHIP_RS400) ||
 446                    (rdev->family == CHIP_RS480)) {
 447                 DRM_INFO("Loading R300 Microcode\n");
 448                 fw_name = FIRMWARE_R300;
 449         } else if ((rdev->family == CHIP_R420) ||
 450                    (rdev->family == CHIP_R423) ||
 451                    (rdev->family == CHIP_RV410)) {
 452                 DRM_INFO("Loading R400 Microcode\n");
 453                 fw_name = FIRMWARE_R420;
 454         } else if ((rdev->family == CHIP_RS690) ||
 455                    (rdev->family == CHIP_RS740)) {
 456                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 457                 fw_name = FIRMWARE_RS690;
 458         } else if (rdev->family == CHIP_RS600) {
 459                 DRM_INFO("Loading RS600 Microcode\n");
 460                 fw_name = FIRMWARE_RS600;
 461         } else if ((rdev->family == CHIP_RV515) ||
 462                    (rdev->family == CHIP_R520) ||
 463                    (rdev->family == CHIP_RV530) ||
 464                    (rdev->family == CHIP_R580) ||
 465                    (rdev->family == CHIP_RV560) ||
 466                    (rdev->family == CHIP_RV570)) {
 467                 DRM_INFO("Loading R500 Microcode\n");
 468                 fw_name = FIRMWARE_R520;
 469         }
 470
 471         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 472         platform_device_unregister(pdev);
 473         if (err) {
 474                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 475                        fw_name);
 476         } else if (rdev->me_fw->size % 8) {
 477                 printk(KERN_ERR
 478                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 479                        rdev->me_fw->size, fw_name);
 480                 err = -EINVAL;
 481                 release_firmware(rdev->me_fw);
 482                 rdev->me_fw = NULL;
 483         }
 484         return err;
 485 }
 486
 487 static void r100_cp_load_microcode(struct radeon_device *rdev)
 488 {
 489         const __be32 *fw_data;
 490         int i, size;
 491
 492         if (r100_gui_wait_for_idle(rdev)) {
 493                 printk(KERN_WARNING "Failed to wait GUI idle while "
 494                        "programming pipes. Bad things might happen.\n");
 495         }
 496
 497         if (rdev->me_fw) {
 498                 size = rdev->me_fw->size / 4;
 499                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 500                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 501                 for (i = 0; i < size; i += 2) {
 502                         WREG32(RADEON_CP_ME_RAM_DATAH,
 503                                be32_to_cpup(&fw_data[i]));
 504                         WREG32(RADEON_CP_ME_RAM_DATAL,
 505                                be32_to_cpup(&fw_data[i + 1]));
 506                 }
 507         }
 508 }
 509
 510 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 511 {
 512         unsigned rb_bufsz;
 513         unsigned rb_blksz;
 514         unsigned max_fetch;
 515         unsigned pre_write_timer;
 516         unsigned pre_write_limit;
 517         unsigned indirect2_start;
 518         unsigned indirect1_start;
 519         uint32_t tmp;
 520         int r;
 521
 522         if (r100_debugfs_cp_init(rdev)) {
 523                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 524         }
 525         /* Reset CP */
 526         tmp = RREG32(RADEON_CP_CSQ_STAT);
 527         if ((tmp & (1 << 31))) {
 528                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 529                 WREG32(RADEON_CP_CSQ_MODE, 0);
 530                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 531                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 532                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 533                 mdelay(2);
 534                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 535                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 536                 mdelay(2);
 537                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 538                 if ((tmp & (1 << 31))) {
 539                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 540                 }
 541         } else {
 542                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 543         }
 544
 545         if (!rdev->me_fw) {
 546                 r = r100_cp_init_microcode(rdev);
 547                 if (r) {
 548                         DRM_ERROR("Failed to load firmware!\n");
 549                         return r;
 550                 }
 551         }
 552
 553         /* Align ring size */
 554         rb_bufsz = drm_order(ring_size / 8);
 555         ring_size = (1 << (rb_bufsz + 1)) * 4;
 556         r100_cp_load_microcode(rdev);
 557         r = radeon_ring_init(rdev, ring_size);
 558         if (r) {
 559                 return r;
 560         }
 561         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 562          * the rptr copy in system ram */
 563         rb_blksz = 9;
 564         /* cp will read 128bytes at a time (4 dwords) */
 565         max_fetch = 1;
 566         rdev->cp.align_mask = 16 - 1;
 567         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 568         pre_write_timer = 64;
 569         /* Force CP_RB_WPTR write if written more than one time before the
 570          * delay expire
 571          */
 572         pre_write_limit = 0;
 573         /* Setup the cp cache like this (cache size is 96 dwords) :
 574          *      RING            0  to 15
 575          *      INDIRECT1       16 to 79
 576          *      INDIRECT2       80 to 95
 577          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 578          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 579          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 580          * Idea being that most of the gpu cmd will be through indirect1 buffer
 581          * so it gets the bigger cache.
 582          */
 583         indirect2_start = 80;
 584         indirect1_start = 16;
 585         /* cp setup */
 586         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 587         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 588                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 589                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 590                RADEON_RB_NO_UPDATE);
 591 #ifdef __BIG_ENDIAN
 592         tmp |= RADEON_BUF_SWAP_32BIT;
 593 #endif
 594         WREG32(RADEON_CP_RB_CNTL, tmp);
 595
 596         /* Set ring address */
 597         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 598         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 599         /* Force read & write ptr to 0 */
 600         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 601         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 602         WREG32(RADEON_CP_RB_WPTR, 0);
 603         WREG32(RADEON_CP_RB_CNTL, tmp);
 604         udelay(10);
 605         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 606         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 607         /* Set cp mode to bus mastering & enable cp*/
 608         WREG32(RADEON_CP_CSQ_MODE,
 609                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 610                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 611         WREG32(0x718, 0);
 612         WREG32(0x744, 0x00004D4D);
 613         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 614         radeon_ring_start(rdev);
 615         r = radeon_ring_test(rdev);
 616         if (r) {
 617                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 618                 return r;
 619         }
 620         rdev->cp.ready = true;
 621         return 0;
 622 }
 623
 624 void r100_cp_fini(struct radeon_device *rdev)
 625 {
 626         if (r100_cp_wait_for_idle(rdev)) {
 627                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 628         }
 629         /* Disable ring */
 630         r100_cp_disable(rdev);
 631         radeon_ring_fini(rdev);
 632         DRM_INFO("radeon: cp finalized\n");
 633 }
 634
 635 void r100_cp_disable(struct radeon_device *rdev)
 636 {
 637         /* Disable ring */
 638         rdev->cp.ready = false;
 639         WREG32(RADEON_CP_CSQ_MODE, 0);
 640         WREG32(RADEON_CP_CSQ_CNTL, 0);
 641         if (r100_gui_wait_for_idle(rdev)) {
 642                 printk(KERN_WARNING "Failed to wait GUI idle while "
 643                        "programming pipes. Bad things might happen.\n");
 644         }
 645 }
 646
 647 int r100_cp_reset(struct radeon_device *rdev)
 648 {
 649         uint32_t tmp;
 650         bool reinit_cp;
 651         int i;
 652
 653         reinit_cp = rdev->cp.ready;
 654         rdev->cp.ready = false;
 655         WREG32(RADEON_CP_CSQ_MODE, 0);
 656         WREG32(RADEON_CP_CSQ_CNTL, 0);
 657         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 658         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 659         udelay(200);
 660         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 661         /* Wait to prevent race in RBBM_STATUS */
 662         mdelay(1);
 663         for (i = 0; i < rdev->usec_timeout; i++) {
 664                 tmp = RREG32(RADEON_RBBM_STATUS);
 665                 if (!(tmp & (1 << 16))) {
 666                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 667                                  tmp);
 668                         if (reinit_cp) {
 669                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 670                         }
 671                         return 0;
 672                 }
 673                 DRM_UDELAY(1);
 674         }
 675         tmp = RREG32(RADEON_RBBM_STATUS);
 676         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 677         return -1;
 678 }
 679
 680 void r100_cp_commit(struct radeon_device *rdev)
 681 {
 682         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 683         (void)RREG32(RADEON_CP_RB_WPTR);
 684 }
 685
 686
 687 /*
 688  * CS functions
 689  */
 690 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 691                           struct radeon_cs_packet *pkt,
 692                           const unsigned *auth, unsigned n,
 693                           radeon_packet0_check_t check)
 694 {
 695         unsigned reg;
 696         unsigned i, j, m;
 697         unsigned idx;
 698         int r;
 699
 700         idx = pkt->idx + 1;
 701         reg = pkt->reg;
 702         /* Check that register fall into register range
 703          * determined by the number of entry (n) in the
 704          * safe register bitmap.
 705          */
 706         if (pkt->one_reg_wr) {
 707                 if ((reg >> 7) > n) {
 708                         return -EINVAL;
 709                 }
 710         } else {
 711                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 712                         return -EINVAL;
 713                 }
 714         }
 715         for (i = 0; i <= pkt->count; i++, idx++) {
 716                 j = (reg >> 7);
 717                 m = 1 << ((reg >> 2) & 31);
 718                 if (auth[j] & m) {
 719                         r = check(p, pkt, idx, reg);
 720                         if (r) {
 721                                 return r;
 722                         }
 723                 }
 724                 if (pkt->one_reg_wr) {
 725                         if (!(auth[j] & m)) {
 726                                 break;
 727                         }
 728                 } else {
 729                         reg += 4;
 730                 }
 731         }
 732         return 0;
 733 }
 734
 735 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 736                          struct radeon_cs_packet *pkt)
 737 {
 738         volatile uint32_t *ib;
 739         unsigned i;
 740         unsigned idx;
 741
 742         ib = p->ib->ptr;
 743         idx = pkt->idx;
 744         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 745                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 746         }
 747 }
 748
 749 /**
 750  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 751  * @parser:     parser structure holding parsing context.
 752  * @pkt:        where to store packet informations
 753  *
 754  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 755  * if packet is bigger than remaining ib size. or if packets is unknown.
 756  **/
 757 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 758                          struct radeon_cs_packet *pkt,
 759                          unsigned idx)
 760 {
 761         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 762         uint32_t header;
 763
 764         if (idx >= ib_chunk->length_dw) {
 765                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 766                           idx, ib_chunk->length_dw);
 767                 return -EINVAL;
 768         }
 769         header = radeon_get_ib_value(p, idx);
 770         pkt->idx = idx;
 771         pkt->type = CP_PACKET_GET_TYPE(header);
 772         pkt->count = CP_PACKET_GET_COUNT(header);
 773         switch (pkt->type) {
 774         case PACKET_TYPE0:
 775                 pkt->reg = CP_PACKET0_GET_REG(header);
 776                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 777                 break;
 778         case PACKET_TYPE3:
 779                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 780                 break;
 781         case PACKET_TYPE2:
 782                 pkt->count = -1;
 783                 break;
 784         default:
 785                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 786                 return -EINVAL;
 787         }
 788         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 789                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 790                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 791                 return -EINVAL;
 792         }
 793         return 0;
 794 }
 795
 796 /**
 797  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 798  * @parser:             parser structure holding parsing context.
 799  *
 800  * Userspace sends a special sequence for VLINE waits.
 801  * PACKET0 - VLINE_START_END + value
 802  * PACKET0 - WAIT_UNTIL +_value
 803  * RELOC (P3) - crtc_id in reloc.
 804  *
 805  * This function parses this and relocates the VLINE START END
 806  * and WAIT UNTIL packets to the correct crtc.
 807  * It also detects a switched off crtc and nulls out the
 808  * wait in that case.
 809  */
 810 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 811 {
 812         struct drm_mode_object *obj;
 813         struct drm_crtc *crtc;
 814         struct radeon_crtc *radeon_crtc;
 815         struct radeon_cs_packet p3reloc, waitreloc;
 816         int crtc_id;
 817         int r;
 818         uint32_t header, h_idx, reg;
 819         volatile uint32_t *ib;
 820
 821         ib = p->ib->ptr;
 822
 823         /* parse the wait until */
 824         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 825         if (r)
 826                 return r;
 827
 828         /* check its a wait until and only 1 count */
 829         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 830             waitreloc.count != 0) {
 831                 DRM_ERROR("vline wait had illegal wait until segment\n");
 832                 r = -EINVAL;
 833                 return r;
 834         }
 835
 836         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 837                 DRM_ERROR("vline wait had illegal wait until\n");
 838                 r = -EINVAL;
 839                 return r;
 840         }
 841
 842         /* jump over the NOP */
 843         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 844         if (r)
 845                 return r;
 846
 847         h_idx = p->idx - 2;
 848         p->idx += waitreloc.count + 2;
 849         p->idx += p3reloc.count + 2;
 850
 851         header = radeon_get_ib_value(p, h_idx);
 852         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 853         reg = CP_PACKET0_GET_REG(header);
 854         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 855         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 856         if (!obj) {
 857                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 858                 r = -EINVAL;
 859                 goto out;
 860         }
 861         crtc = obj_to_crtc(obj);
 862         radeon_crtc = to_radeon_crtc(crtc);
 863         crtc_id = radeon_crtc->crtc_id;
 864
 865         if (!crtc->enabled) {
 866                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 867                 ib[h_idx + 2] = PACKET2(0);
 868                 ib[h_idx + 3] = PACKET2(0);
 869         } else if (crtc_id == 1) {
 870                 switch (reg) {
 871                 case AVIVO_D1MODE_VLINE_START_END:
 872                         header &= ~R300_CP_PACKET0_REG_MASK;
 873                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 874                         break;
 875                 case RADEON_CRTC_GUI_TRIG_VLINE:
 876                         header &= ~R300_CP_PACKET0_REG_MASK;
 877                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 878                         break;
 879                 default:
 880                         DRM_ERROR("unknown crtc reloc\n");
 881                         r = -EINVAL;
 882                         goto out;
 883                 }
 884                 ib[h_idx] = header;
 885                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 886         }
 887 out:
 888         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
 889         return r;
 890 }
 891
 892 /**
 893  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 894  * @parser:             parser structure holding parsing context.
 895  * @data:               pointer to relocation data
 896  * @offset_start:       starting offset
 897  * @offset_mask:        offset mask (to align start offset on)
 898  * @reloc:              reloc informations
 899  *
 900  * Check next packet is relocation packet3, do bo validation and compute
 901  * GPU offset using the provided start.
 902  **/
 903 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 904                               struct radeon_cs_reloc **cs_reloc)
 905 {
 906         struct radeon_cs_chunk *relocs_chunk;
 907         struct radeon_cs_packet p3reloc;
 908         unsigned idx;
 909         int r;
 910
 911         if (p->chunk_relocs_idx == -1) {
 912                 DRM_ERROR("No relocation chunk !\n");
 913                 return -EINVAL;
 914         }
 915         *cs_reloc = NULL;
 916         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 917         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
 918         if (r) {
 919                 return r;
 920         }
 921         p->idx += p3reloc.count + 2;
 922         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 923                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 924                           p3reloc.idx);
 925                 r100_cs_dump_packet(p, &p3reloc);
 926                 return -EINVAL;
 927         }
 928         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 929         if (idx >= relocs_chunk->length_dw) {
 930                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 931                           idx, relocs_chunk->length_dw);
 932                 r100_cs_dump_packet(p, &p3reloc);
 933                 return -EINVAL;
 934         }
 935         /* FIXME: we assume reloc size is 4 dwords */
 936         *cs_reloc = p->relocs_ptr[(idx / 4)];
 937         return 0;
 938 }
 939
 940 static int r100_get_vtx_size(uint32_t vtx_fmt)
 941 {
 942         int vtx_size;
 943         vtx_size = 2;
 944         /* ordered according to bits in spec */
 945         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
 946                 vtx_size++;
 947         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
 948                 vtx_size += 3;
 949         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
 950                 vtx_size++;
 951         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
 952                 vtx_size++;
 953         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
 954                 vtx_size += 3;
 955         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
 956                 vtx_size++;
 957         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
 958                 vtx_size++;
 959         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
 960                 vtx_size += 2;
 961         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
 962                 vtx_size += 2;
 963         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
 964                 vtx_size++;
 965         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
 966                 vtx_size += 2;
 967         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
 968                 vtx_size++;
 969         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
 970                 vtx_size += 2;
 971         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
 972                 vtx_size++;
 973         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
 974                 vtx_size++;
 975         /* blend weight */
 976         if (vtx_fmt & (0x7 << 15))
 977                 vtx_size += (vtx_fmt >> 15) & 0x7;
 978         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
 979                 vtx_size += 3;
 980         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
 981                 vtx_size += 2;
 982         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
 983                 vtx_size++;
 984         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
 985                 vtx_size++;
 986         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
 987                 vtx_size++;
 988         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
 989                 vtx_size++;
 990         return vtx_size;
 991 }
 992
 993 static int r100_packet0_check(struct radeon_cs_parser *p,
 994                               struct radeon_cs_packet *pkt,
 995                               unsigned idx, unsigned reg)
 996 {
 997         struct radeon_cs_reloc *reloc;
 998         struct r100_cs_track *track;
 999         volatile uint32_t *ib;
1000         uint32_t tmp;
1001         int r;
1002         int i, face;
1003         u32 tile_flags = 0;
1004         u32 idx_value;
1005
1006         ib = p->ib->ptr;
1007         track = (struct r100_cs_track *)p->track;
1008
1009         idx_value = radeon_get_ib_value(p, idx);
1010
1011         switch (reg) {
1012         case RADEON_CRTC_GUI_TRIG_VLINE:
1013                 r = r100_cs_packet_parse_vline(p);
1014                 if (r) {
1015                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1016                                   idx, reg);
1017                         r100_cs_dump_packet(p, pkt);
1018                         return r;
1019                 }
1020                 break;
1021                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1022                  * range access */
1023         case RADEON_DST_PITCH_OFFSET:
1024         case RADEON_SRC_PITCH_OFFSET:
1025                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1026                 if (r)
1027                         return r;
1028                 break;
1029         case RADEON_RB3D_DEPTHOFFSET:
1030                 r = r100_cs_packet_next_reloc(p, &reloc);
1031                 if (r) {
1032                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1033                                   idx, reg);
1034                         r100_cs_dump_packet(p, pkt);
1035                         return r;
1036                 }
1037                 track->zb.robj = reloc->robj;
1038                 track->zb.offset = idx_value;
1039                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1040                 break;
1041         case RADEON_RB3D_COLOROFFSET:
1042                 r = r100_cs_packet_next_reloc(p, &reloc);
1043                 if (r) {
1044                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1045                                   idx, reg);
1046                         r100_cs_dump_packet(p, pkt);
1047                         return r;
1048                 }
1049                 track->cb[0].robj = reloc->robj;
1050                 track->cb[0].offset = idx_value;
1051                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1052                 break;
1053         case RADEON_PP_TXOFFSET_0:
1054         case RADEON_PP_TXOFFSET_1:
1055         case RADEON_PP_TXOFFSET_2:
1056                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1057                 r = r100_cs_packet_next_reloc(p, &reloc);
1058                 if (r) {
1059                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1060                                   idx, reg);
1061                         r100_cs_dump_packet(p, pkt);
1062                         return r;
1063                 }
1064                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1065                 track->textures[i].robj = reloc->robj;
1066                 break;
1067         case RADEON_PP_CUBIC_OFFSET_T0_0:
1068         case RADEON_PP_CUBIC_OFFSET_T0_1:
1069         case RADEON_PP_CUBIC_OFFSET_T0_2:
1070         case RADEON_PP_CUBIC_OFFSET_T0_3:
1071         case RADEON_PP_CUBIC_OFFSET_T0_4:
1072                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1073                 r = r100_cs_packet_next_reloc(p, &reloc);
1074                 if (r) {
1075                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1076                                   idx, reg);
1077                         r100_cs_dump_packet(p, pkt);
1078                         return r;
1079                 }
1080                 track->textures[0].cube_info[i].offset = idx_value;
1081                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1082                 track->textures[0].cube_info[i].robj = reloc->robj;
1083                 break;
1084         case RADEON_PP_CUBIC_OFFSET_T1_0:
1085         case RADEON_PP_CUBIC_OFFSET_T1_1:
1086         case RADEON_PP_CUBIC_OFFSET_T1_2:
1087         case RADEON_PP_CUBIC_OFFSET_T1_3:
1088         case RADEON_PP_CUBIC_OFFSET_T1_4:
1089                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1090                 r = r100_cs_packet_next_reloc(p, &reloc);
1091                 if (r) {
1092                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1093                                   idx, reg);
1094                         r100_cs_dump_packet(p, pkt);
1095                         return r;
1096                 }
1097                 track->textures[1].cube_info[i].offset = idx_value;
1098                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1099                 track->textures[1].cube_info[i].robj = reloc->robj;
1100                 break;
1101         case RADEON_PP_CUBIC_OFFSET_T2_0:
1102         case RADEON_PP_CUBIC_OFFSET_T2_1:
1103         case RADEON_PP_CUBIC_OFFSET_T2_2:
1104         case RADEON_PP_CUBIC_OFFSET_T2_3:
1105         case RADEON_PP_CUBIC_OFFSET_T2_4:
1106                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1107                 r = r100_cs_packet_next_reloc(p, &reloc);
1108                 if (r) {
1109                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1110                                   idx, reg);
1111                         r100_cs_dump_packet(p, pkt);
1112                         return r;
1113                 }
1114                 track->textures[2].cube_info[i].offset = idx_value;
1115                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1116                 track->textures[2].cube_info[i].robj = reloc->robj;
1117                 break;
1118         case RADEON_RE_WIDTH_HEIGHT:
1119                 track->maxy = ((idx_value >> 16) & 0x7FF);
1120                 break;
1121         case RADEON_RB3D_COLORPITCH:
1122                 r = r100_cs_packet_next_reloc(p, &reloc);
1123                 if (r) {
1124                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1125                                   idx, reg);
1126                         r100_cs_dump_packet(p, pkt);
1127                         return r;
1128                 }
1129
1130                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1131                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1132                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1133                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1134
1135                 tmp = idx_value & ~(0x7 << 16);
1136                 tmp |= tile_flags;
1137                 ib[idx] = tmp;
1138
1139                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1140                 break;
1141         case RADEON_RB3D_DEPTHPITCH:
1142                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1143                 break;
1144         case RADEON_RB3D_CNTL:
1145                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1146                 case 7:
1147                 case 8:
1148                 case 9:
1149                 case 11:
1150                 case 12:
1151                         track->cb[0].cpp = 1;
1152                         break;
1153                 case 3:
1154                 case 4:
1155                 case 15:
1156                         track->cb[0].cpp = 2;
1157                         break;
1158                 case 6:
1159                         track->cb[0].cpp = 4;
1160                         break;
1161                 default:
1162                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1163                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1164                         return -EINVAL;
1165                 }
1166                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1167                 break;
1168         case RADEON_RB3D_ZSTENCILCNTL:
1169                 switch (idx_value & 0xf) {
1170                 case 0:
1171                         track->zb.cpp = 2;
1172                         break;
1173                 case 2:
1174                 case 3:
1175                 case 4:
1176                 case 5:
1177                 case 9:
1178                 case 11:
1179                         track->zb.cpp = 4;
1180                         break;
1181                 default:
1182                         break;
1183                 }
1184                 break;
1185         case RADEON_RB3D_ZPASS_ADDR:
1186                 r = r100_cs_packet_next_reloc(p, &reloc);
1187                 if (r) {
1188                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1189                                   idx, reg);
1190                         r100_cs_dump_packet(p, pkt);
1191                         return r;
1192                 }
1193                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1194                 break;
1195         case RADEON_PP_CNTL:
1196                 {
1197                         uint32_t temp = idx_value >> 4;
1198                         for (i = 0; i < track->num_texture; i++)
1199                                 track->textures[i].enabled = !!(temp & (1 << i));
1200                 }
1201                 break;
1202         case RADEON_SE_VF_CNTL:
1203                 track->vap_vf_cntl = idx_value;
1204                 break;
1205         case RADEON_SE_VTX_FMT:
1206                 track->vtx_size = r100_get_vtx_size(idx_value);
1207                 break;
1208         case RADEON_PP_TEX_SIZE_0:
1209         case RADEON_PP_TEX_SIZE_1:
1210         case RADEON_PP_TEX_SIZE_2:
1211                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1212                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1213                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1214                 break;
1215         case RADEON_PP_TEX_PITCH_0:
1216         case RADEON_PP_TEX_PITCH_1:
1217         case RADEON_PP_TEX_PITCH_2:
1218                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1219                 track->textures[i].pitch = idx_value + 32;
1220                 break;
1221         case RADEON_PP_TXFILTER_0:
1222         case RADEON_PP_TXFILTER_1:
1223         case RADEON_PP_TXFILTER_2:
1224                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1225                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1226                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1227                 tmp = (idx_value >> 23) & 0x7;
1228                 if (tmp == 2 || tmp == 6)
1229                         track->textures[i].roundup_w = false;
1230                 tmp = (idx_value >> 27) & 0x7;
1231                 if (tmp == 2 || tmp == 6)
1232                         track->textures[i].roundup_h = false;
1233                 break;
1234         case RADEON_PP_TXFORMAT_0:
1235         case RADEON_PP_TXFORMAT_1:
1236         case RADEON_PP_TXFORMAT_2:
1237                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1238                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1239                         track->textures[i].use_pitch = 1;
1240                 } else {
1241                         track->textures[i].use_pitch = 0;
1242                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1243                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1244                 }
1245                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1246                         track->textures[i].tex_coord_type = 2;
1247                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1248                 case RADEON_TXFORMAT_I8:
1249                 case RADEON_TXFORMAT_RGB332:
1250                 case RADEON_TXFORMAT_Y8:
1251                         track->textures[i].cpp = 1;
1252                         break;
1253                 case RADEON_TXFORMAT_AI88:
1254                 case RADEON_TXFORMAT_ARGB1555:
1255                 case RADEON_TXFORMAT_RGB565:
1256                 case RADEON_TXFORMAT_ARGB4444:
1257                 case RADEON_TXFORMAT_VYUY422:
1258                 case RADEON_TXFORMAT_YVYU422:
1259                 case RADEON_TXFORMAT_DXT1:
1260                 case RADEON_TXFORMAT_SHADOW16:
1261                 case RADEON_TXFORMAT_LDUDV655:
1262                 case RADEON_TXFORMAT_DUDV88:
1263                         track->textures[i].cpp = 2;
1264                         break;
1265                 case RADEON_TXFORMAT_ARGB8888:
1266                 case RADEON_TXFORMAT_RGBA8888:
1267                 case RADEON_TXFORMAT_DXT23:
1268                 case RADEON_TXFORMAT_DXT45:
1269                 case RADEON_TXFORMAT_SHADOW32:
1270                 case RADEON_TXFORMAT_LDUDUV8888:
1271                         track->textures[i].cpp = 4;
1272                         break;
1273                 }
1274                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1275                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1276                 break;
1277         case RADEON_PP_CUBIC_FACES_0:
1278         case RADEON_PP_CUBIC_FACES_1:
1279         case RADEON_PP_CUBIC_FACES_2:
1280                 tmp = idx_value;
1281                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1282                 for (face = 0; face < 4; face++) {
1283                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1284                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1285                 }
1286                 break;
1287         default:
1288                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1289                        reg, idx);
1290                 return -EINVAL;
1291         }
1292         return 0;
1293 }
1294
1295 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1296                                          struct radeon_cs_packet *pkt,
1297                                          struct radeon_object *robj)
1298 {
1299         unsigned idx;
1300         u32 value;
1301         idx = pkt->idx + 1;
1302         value = radeon_get_ib_value(p, idx + 2);
1303         if ((value + 1) > radeon_object_size(robj)) {
1304                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1305                           "(need %u have %lu) !\n",
1306                           value + 1,
1307                           radeon_object_size(robj));
1308                 return -EINVAL;
1309         }
1310         return 0;
1311 }
1312
1313 static int r100_packet3_check(struct radeon_cs_parser *p,
1314                               struct radeon_cs_packet *pkt)
1315 {
1316         struct radeon_cs_reloc *reloc;
1317         struct r100_cs_track *track;
1318         unsigned idx;
1319         volatile uint32_t *ib;
1320         int r;
1321
1322         ib = p->ib->ptr;
1323         idx = pkt->idx + 1;
1324         track = (struct r100_cs_track *)p->track;
1325         switch (pkt->opcode) {
1326         case PACKET3_3D_LOAD_VBPNTR:
1327                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1328                 if (r)
1329                         return r;
1330                 break;
1331         case PACKET3_INDX_BUFFER:
1332                 r = r100_cs_packet_next_reloc(p, &reloc);
1333                 if (r) {
1334                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1335                         r100_cs_dump_packet(p, pkt);
1336                         return r;
1337                 }
1338                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1339                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1340                 if (r) {
1341                         return r;
1342                 }
1343                 break;
1344         case 0x23:
1345                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1346                 r = r100_cs_packet_next_reloc(p, &reloc);
1347                 if (r) {
1348                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1349                         r100_cs_dump_packet(p, pkt);
1350                         return r;
1351                 }
1352                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1353                 track->num_arrays = 1;
1354                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1355
1356                 track->arrays[0].robj = reloc->robj;
1357                 track->arrays[0].esize = track->vtx_size;
1358
1359                 track->max_indx = radeon_get_ib_value(p, idx+1);
1360
1361                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1362                 track->immd_dwords = pkt->count - 1;
1363                 r = r100_cs_track_check(p->rdev, track);
1364                 if (r)
1365                         return r;
1366                 break;
1367         case PACKET3_3D_DRAW_IMMD:
1368                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1369                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1370                         return -EINVAL;
1371                 }
1372                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1373                 track->immd_dwords = pkt->count - 1;
1374                 r = r100_cs_track_check(p->rdev, track);
1375                 if (r)
1376                         return r;
1377                 break;
1378                 /* triggers drawing using in-packet vertex data */
1379         case PACKET3_3D_DRAW_IMMD_2:
1380                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1381                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1382                         return -EINVAL;
1383                 }
1384                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1385                 track->immd_dwords = pkt->count;
1386                 r = r100_cs_track_check(p->rdev, track);
1387                 if (r)
1388                         return r;
1389                 break;
1390                 /* triggers drawing using in-packet vertex data */
1391         case PACKET3_3D_DRAW_VBUF_2:
1392                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1393                 r = r100_cs_track_check(p->rdev, track);
1394                 if (r)
1395                         return r;
1396                 break;
1397                 /* triggers drawing of vertex buffers setup elsewhere */
1398         case PACKET3_3D_DRAW_INDX_2:
1399                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1400                 r = r100_cs_track_check(p->rdev, track);
1401                 if (r)
1402                         return r;
1403                 break;
1404                 /* triggers drawing using indices to vertex buffer */
1405         case PACKET3_3D_DRAW_VBUF:
1406                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1407                 r = r100_cs_track_check(p->rdev, track);
1408                 if (r)
1409                         return r;
1410                 break;
1411                 /* triggers drawing of vertex buffers setup elsewhere */
1412         case PACKET3_3D_DRAW_INDX:
1413                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1414                 r = r100_cs_track_check(p->rdev, track);
1415                 if (r)
1416                         return r;
1417                 break;
1418                 /* triggers drawing using indices to vertex buffer */
1419         case PACKET3_NOP:
1420                 break;
1421         default:
1422                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1423                 return -EINVAL;
1424         }
1425         return 0;
1426 }
1427
1428 int r100_cs_parse(struct radeon_cs_parser *p)
1429 {
1430         struct radeon_cs_packet pkt;
1431         struct r100_cs_track *track;
1432         int r;
1433
1434         track = kzalloc(sizeof(*track), GFP_KERNEL);
1435         r100_cs_track_clear(p->rdev, track);
1436         p->track = track;
1437         do {
1438                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1439                 if (r) {
1440                         return r;
1441                 }
1442                 p->idx += pkt.count + 2;
1443                 switch (pkt.type) {
1444                         case PACKET_TYPE0:
1445                                 if (p->rdev->family >= CHIP_R200)
1446                                         r = r100_cs_parse_packet0(p, &pkt,
1447                                                                   p->rdev->config.r100.reg_safe_bm,
1448                                                                   p->rdev->config.r100.reg_safe_bm_size,
1449                                                                   &r200_packet0_check);
1450                                 else
1451                                         r = r100_cs_parse_packet0(p, &pkt,
1452                                                                   p->rdev->config.r100.reg_safe_bm,
1453                                                                   p->rdev->config.r100.reg_safe_bm_size,
1454                                                                   &r100_packet0_check);
1455                                 break;
1456                         case PACKET_TYPE2:
1457                                 break;
1458                         case PACKET_TYPE3:
1459                                 r = r100_packet3_check(p, &pkt);
1460                                 break;
1461                         default:
1462                                 DRM_ERROR("Unknown packet type %d !\n",
1463                                           pkt.type);
1464                                 return -EINVAL;
1465                 }
1466                 if (r) {
1467                         return r;
1468                 }
1469         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1470         return 0;
1471 }
1472
1473
1474 /*
1475  * Global GPU functions
1476  */
1477 void r100_errata(struct radeon_device *rdev)
1478 {
1479         rdev->pll_errata = 0;
1480
1481         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1482                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1483         }
1484
1485         if (rdev->family == CHIP_RV100 ||
1486             rdev->family == CHIP_RS100 ||
1487             rdev->family == CHIP_RS200) {
1488                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1489         }
1490 }
1491
1492 /* Wait for vertical sync on primary CRTC */
1493 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1494 {
1495         uint32_t crtc_gen_cntl, tmp;
1496         int i;
1497
1498         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1499         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1500             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1501                 return;
1502         }
1503         /* Clear the CRTC_VBLANK_SAVE bit */
1504         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1505         for (i = 0; i < rdev->usec_timeout; i++) {
1506                 tmp = RREG32(RADEON_CRTC_STATUS);
1507                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1508                         return;
1509                 }
1510                 DRM_UDELAY(1);
1511         }
1512 }
1513
1514 /* Wait for vertical sync on secondary CRTC */
1515 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1516 {
1517         uint32_t crtc2_gen_cntl, tmp;
1518         int i;
1519
1520         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1521         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1522             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1523                 return;
1524
1525         /* Clear the CRTC_VBLANK_SAVE bit */
1526         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1527         for (i = 0; i < rdev->usec_timeout; i++) {
1528                 tmp = RREG32(RADEON_CRTC2_STATUS);
1529                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1530                         return;
1531                 }
1532                 DRM_UDELAY(1);
1533         }
1534 }
1535
1536 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1537 {
1538         unsigned i;
1539         uint32_t tmp;
1540
1541         for (i = 0; i < rdev->usec_timeout; i++) {
1542                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1543                 if (tmp >= n) {
1544                         return 0;
1545                 }
1546                 DRM_UDELAY(1);
1547         }
1548         return -1;
1549 }
1550
1551 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1552 {
1553         unsigned i;
1554         uint32_t tmp;
1555
1556         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1557                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1558                        " Bad things might happen.\n");
1559         }
1560         for (i = 0; i < rdev->usec_timeout; i++) {
1561                 tmp = RREG32(RADEON_RBBM_STATUS);
1562                 if (!(tmp & (1 << 31))) {
1563                         return 0;
1564                 }
1565                 DRM_UDELAY(1);
1566         }
1567         return -1;
1568 }
1569
1570 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1571 {
1572         unsigned i;
1573         uint32_t tmp;
1574
1575         for (i = 0; i < rdev->usec_timeout; i++) {
1576                 /* read MC_STATUS */
1577                 tmp = RREG32(0x0150);
1578                 if (tmp & (1 << 2)) {
1579                         return 0;
1580                 }
1581                 DRM_UDELAY(1);
1582         }
1583         return -1;
1584 }
1585
1586 void r100_gpu_init(struct radeon_device *rdev)
1587 {
1588         /* TODO: anythings to do here ? pipes ? */
1589         r100_hdp_reset(rdev);
1590 }
1591
1592 void r100_hdp_reset(struct radeon_device *rdev)
1593 {
1594         uint32_t tmp;
1595
1596         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1597         tmp |= (7 << 28);
1598         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1599         (void)RREG32(RADEON_HOST_PATH_CNTL);
1600         udelay(200);
1601         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1602         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1603         (void)RREG32(RADEON_HOST_PATH_CNTL);
1604 }
1605
1606 int r100_rb2d_reset(struct radeon_device *rdev)
1607 {
1608         uint32_t tmp;
1609         int i;
1610
1611         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1612         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1613         udelay(200);
1614         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1615         /* Wait to prevent race in RBBM_STATUS */
1616         mdelay(1);
1617         for (i = 0; i < rdev->usec_timeout; i++) {
1618                 tmp = RREG32(RADEON_RBBM_STATUS);
1619                 if (!(tmp & (1 << 26))) {
1620                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1621                                  tmp);
1622                         return 0;
1623                 }
1624                 DRM_UDELAY(1);
1625         }
1626         tmp = RREG32(RADEON_RBBM_STATUS);
1627         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1628         return -1;
1629 }
1630
1631 int r100_gpu_reset(struct radeon_device *rdev)
1632 {
1633         uint32_t status;
1634
1635         /* reset order likely matter */
1636         status = RREG32(RADEON_RBBM_STATUS);
1637         /* reset HDP */
1638         r100_hdp_reset(rdev);
1639         /* reset rb2d */
1640         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1641                 r100_rb2d_reset(rdev);
1642         }
1643         /* TODO: reset 3D engine */
1644         /* reset CP */
1645         status = RREG32(RADEON_RBBM_STATUS);
1646         if (status & (1 << 16)) {
1647                 r100_cp_reset(rdev);
1648         }
1649         /* Check if GPU is idle */
1650         status = RREG32(RADEON_RBBM_STATUS);
1651         if (status & (1 << 31)) {
1652                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1653                 return -1;
1654         }
1655         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1656         return 0;
1657 }
1658
1659
1660 /*
1661  * VRAM info
1662  */
1663 static void r100_vram_get_type(struct radeon_device *rdev)
1664 {
1665         uint32_t tmp;
1666
1667         rdev->mc.vram_is_ddr = false;
1668         if (rdev->flags & RADEON_IS_IGP)
1669                 rdev->mc.vram_is_ddr = true;
1670         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1671                 rdev->mc.vram_is_ddr = true;
1672         if ((rdev->family == CHIP_RV100) ||
1673             (rdev->family == CHIP_RS100) ||
1674             (rdev->family == CHIP_RS200)) {
1675                 tmp = RREG32(RADEON_MEM_CNTL);
1676                 if (tmp & RV100_HALF_MODE) {
1677                         rdev->mc.vram_width = 32;
1678                 } else {
1679                         rdev->mc.vram_width = 64;
1680                 }
1681                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1682                         rdev->mc.vram_width /= 4;
1683                         rdev->mc.vram_is_ddr = true;
1684                 }
1685         } else if (rdev->family <= CHIP_RV280) {
1686                 tmp = RREG32(RADEON_MEM_CNTL);
1687                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1688                         rdev->mc.vram_width = 128;
1689                 } else {
1690                         rdev->mc.vram_width = 64;
1691                 }
1692         } else {
1693                 /* newer IGPs */
1694                 rdev->mc.vram_width = 128;
1695         }
1696 }
1697
1698 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1699 {
1700         u32 aper_size;
1701         u8 byte;
1702
1703         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1704
1705         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1706          * that is has the 2nd generation multifunction PCI interface
1707          */
1708         if (rdev->family == CHIP_RV280 ||
1709             rdev->family >= CHIP_RV350) {
1710                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1711                        ~RADEON_HDP_APER_CNTL);
1712                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1713                 return aper_size * 2;
1714         }
1715
1716         /* Older cards have all sorts of funny issues to deal with. First
1717          * check if it's a multifunction card by reading the PCI config
1718          * header type... Limit those to one aperture size
1719          */
1720         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1721         if (byte & 0x80) {
1722                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1723                 DRM_INFO("Limiting VRAM to one aperture\n");
1724                 return aper_size;
1725         }
1726
1727         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1728          * have set it up. We don't write this as it's broken on some ASICs but
1729          * we expect the BIOS to have done the right thing (might be too optimistic...)
1730          */
1731         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1732                 return aper_size * 2;
1733         return aper_size;
1734 }
1735
1736 void r100_vram_init_sizes(struct radeon_device *rdev)
1737 {
1738         u64 config_aper_size;
1739         u32 accessible;
1740
1741         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1742
1743         if (rdev->flags & RADEON_IS_IGP) {
1744                 uint32_t tom;
1745                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1746                 tom = RREG32(RADEON_NB_TOM);
1747                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1748                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1749                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1750                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1751                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1752         } else {
1753                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1754                 /* Some production boards of m6 will report 0
1755                  * if it's 8 MB
1756                  */
1757                 if (rdev->mc.real_vram_size == 0) {
1758                         rdev->mc.real_vram_size = 8192 * 1024;
1759                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1760                 }
1761                 /* let driver place VRAM */
1762                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1763                  /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1764                   * Novell bug 204882 + along with lots of ubuntu ones */
1765                 if (config_aper_size > rdev->mc.real_vram_size)
1766                         rdev->mc.mc_vram_size = config_aper_size;
1767                 else
1768                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1769         }
1770
1771         /* work out accessible VRAM */
1772         accessible = r100_get_accessible_vram(rdev);
1773
1774         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1775         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1776
1777         if (accessible > rdev->mc.aper_size)
1778                 accessible = rdev->mc.aper_size;
1779
1780         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1781                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1782
1783         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1784                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1785 }
1786
1787 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1788 {
1789         uint32_t temp;
1790
1791         temp = RREG32(RADEON_CONFIG_CNTL);
1792         if (state == false) {
1793                 temp &= ~(1<<8);
1794                 temp |= (1<<9);
1795         } else {
1796                 temp &= ~(1<<9);
1797         }
1798         WREG32(RADEON_CONFIG_CNTL, temp);
1799 }
1800
1801 void r100_vram_info(struct radeon_device *rdev)
1802 {
1803         r100_vram_get_type(rdev);
1804
1805         r100_vram_init_sizes(rdev);
1806 }
1807
1808
1809 /*
1810  * Indirect registers accessor
1811  */
1812 void r100_pll_errata_after_index(struct radeon_device *rdev)
1813 {
1814         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1815                 return;
1816         }
1817         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1818         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1819 }
1820
1821 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1822 {
1823         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1824          * or the chip could hang on a subsequent access
1825          */
1826         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1827                 udelay(5000);
1828         }
1829
1830         /* This function is required to workaround a hardware bug in some (all?)
1831          * revisions of the R300.  This workaround should be called after every
1832          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1833          * may not be correct.
1834          */
1835         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1836                 uint32_t save, tmp;
1837
1838                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1839                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1840                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1841                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1842                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1843         }
1844 }
1845
1846 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1847 {
1848         uint32_t data;
1849
1850         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1851         r100_pll_errata_after_index(rdev);
1852         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1853         r100_pll_errata_after_data(rdev);
1854         return data;
1855 }
1856
1857 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1858 {
1859         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1860         r100_pll_errata_after_index(rdev);
1861         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1862         r100_pll_errata_after_data(rdev);
1863 }
1864
1865 void r100_set_safe_registers(struct radeon_device *rdev)
1866 {
1867         if (ASIC_IS_RN50(rdev)) {
1868                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1869                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1870         } else if (rdev->family < CHIP_R200) {
1871                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1872                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1873         } else {
1874                 r200_set_safe_registers(rdev);
1875         }
1876 }
1877
1878 /*
1879  * Debugfs info
1880  */
1881 #if defined(CONFIG_DEBUG_FS)
1882 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1883 {
1884         struct drm_info_node *node = (struct drm_info_node *) m->private;
1885         struct drm_device *dev = node->minor->dev;
1886         struct radeon_device *rdev = dev->dev_private;
1887         uint32_t reg, value;
1888         unsigned i;
1889
1890         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1891         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1892         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1893         for (i = 0; i < 64; i++) {
1894                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1895                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1896                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1897                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1898                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1899         }
1900         return 0;
1901 }
1902
1903 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1904 {
1905         struct drm_info_node *node = (struct drm_info_node *) m->private;
1906         struct drm_device *dev = node->minor->dev;
1907         struct radeon_device *rdev = dev->dev_private;
1908         uint32_t rdp, wdp;
1909         unsigned count, i, j;
1910
1911         radeon_ring_free_size(rdev);
1912         rdp = RREG32(RADEON_CP_RB_RPTR);
1913         wdp = RREG32(RADEON_CP_RB_WPTR);
1914         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1915         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1916         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1917         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1918         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1919         seq_printf(m, "%u dwords in ring\n", count);
1920         for (j = 0; j <= count; j++) {
1921                 i = (rdp + j) & rdev->cp.ptr_mask;
1922                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1923         }
1924         return 0;
1925 }
1926
1927
1928 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1929 {
1930         struct drm_info_node *node = (struct drm_info_node *) m->private;
1931         struct drm_device *dev = node->minor->dev;
1932         struct radeon_device *rdev = dev->dev_private;
1933         uint32_t csq_stat, csq2_stat, tmp;
1934         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1935         unsigned i;
1936
1937         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1938         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1939         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1940         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1941         r_rptr = (csq_stat >> 0) & 0x3ff;
1942         r_wptr = (csq_stat >> 10) & 0x3ff;
1943         ib1_rptr = (csq_stat >> 20) & 0x3ff;
1944         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1945         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1946         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1947         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1948         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1949         seq_printf(m, "Ring rptr %u\n", r_rptr);
1950         seq_printf(m, "Ring wptr %u\n", r_wptr);
1951         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1952         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1953         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1954         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1955         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1956          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1957         seq_printf(m, "Ring fifo:\n");
1958         for (i = 0; i < 256; i++) {
1959                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1960                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1961                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1962         }
1963         seq_printf(m, "Indirect1 fifo:\n");
1964         for (i = 256; i <= 512; i++) {
1965                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1966                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1967                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1968         }
1969         seq_printf(m, "Indirect2 fifo:\n");
1970         for (i = 640; i < ib1_wptr; i++) {
1971                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1972                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1973                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1974         }
1975         return 0;
1976 }
1977
1978 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1979 {
1980         struct drm_info_node *node = (struct drm_info_node *) m->private;
1981         struct drm_device *dev = node->minor->dev;
1982         struct radeon_device *rdev = dev->dev_private;
1983         uint32_t tmp;
1984
1985         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1986         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1987         tmp = RREG32(RADEON_MC_FB_LOCATION);
1988         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1989         tmp = RREG32(RADEON_BUS_CNTL);
1990         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1991         tmp = RREG32(RADEON_MC_AGP_LOCATION);
1992         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1993         tmp = RREG32(RADEON_AGP_BASE);
1994         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1995         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1996         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1997         tmp = RREG32(0x01D0);
1998         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1999         tmp = RREG32(RADEON_AIC_LO_ADDR);
2000         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2001         tmp = RREG32(RADEON_AIC_HI_ADDR);
2002         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2003         tmp = RREG32(0x01E4);
2004         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2005         return 0;
2006 }
2007
2008 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2009         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2010 };
2011
2012 static struct drm_info_list r100_debugfs_cp_list[] = {
2013         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2014         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2015 };
2016
2017 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2018         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2019 };
2020 #endif
2021
2022 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2023 {
2024 #if defined(CONFIG_DEBUG_FS)
2025         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2026 #else
2027         return 0;
2028 #endif
2029 }
2030
2031 int r100_debugfs_cp_init(struct radeon_device *rdev)
2032 {
2033 #if defined(CONFIG_DEBUG_FS)
2034         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2035 #else
2036         return 0;
2037 #endif
2038 }
2039
2040 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2041 {
2042 #if defined(CONFIG_DEBUG_FS)
2043         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2044 #else
2045         return 0;
2046 #endif
2047 }
2048
2049 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2050                          uint32_t tiling_flags, uint32_t pitch,
2051                          uint32_t offset, uint32_t obj_size)
2052 {
2053         int surf_index = reg * 16;
2054         int flags = 0;
2055
2056         /* r100/r200 divide by 16 */
2057         if (rdev->family < CHIP_R300)
2058                 flags = pitch / 16;
2059         else
2060                 flags = pitch / 8;
2061
2062         if (rdev->family <= CHIP_RS200) {
2063                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2064                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2065                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2066                 if (tiling_flags & RADEON_TILING_MACRO)
2067                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2068         } else if (rdev->family <= CHIP_RV280) {
2069                 if (tiling_flags & (RADEON_TILING_MACRO))
2070                         flags |= R200_SURF_TILE_COLOR_MACRO;
2071                 if (tiling_flags & RADEON_TILING_MICRO)
2072                         flags |= R200_SURF_TILE_COLOR_MICRO;
2073         } else {
2074                 if (tiling_flags & RADEON_TILING_MACRO)
2075                         flags |= R300_SURF_TILE_MACRO;
2076                 if (tiling_flags & RADEON_TILING_MICRO)
2077                         flags |= R300_SURF_TILE_MICRO;
2078         }
2079
2080         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2081                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2082         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2083                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2084
2085         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2086         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2087         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2088         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2089         return 0;
2090 }
2091
2092 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2093 {
2094         int surf_index = reg * 16;
2095         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2096 }
2097
2098 void r100_bandwidth_update(struct radeon_device *rdev)
2099 {
2100         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2101         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2102         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2103         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2104         fixed20_12 memtcas_ff[8] = {
2105                 fixed_init(1),
2106                 fixed_init(2),
2107                 fixed_init(3),
2108                 fixed_init(0),
2109                 fixed_init_half(1),
2110                 fixed_init_half(2),
2111                 fixed_init(0),
2112         };
2113         fixed20_12 memtcas_rs480_ff[8] = {
2114                 fixed_init(0),
2115                 fixed_init(1),
2116                 fixed_init(2),
2117                 fixed_init(3),
2118                 fixed_init(0),
2119                 fixed_init_half(1),
2120                 fixed_init_half(2),
2121                 fixed_init_half(3),
2122         };
2123         fixed20_12 memtcas2_ff[8] = {
2124                 fixed_init(0),
2125                 fixed_init(1),
2126                 fixed_init(2),
2127                 fixed_init(3),
2128                 fixed_init(4),
2129                 fixed_init(5),
2130                 fixed_init(6),
2131                 fixed_init(7),
2132         };
2133         fixed20_12 memtrbs[8] = {
2134                 fixed_init(1),
2135                 fixed_init_half(1),
2136                 fixed_init(2),
2137                 fixed_init_half(2),
2138                 fixed_init(3),
2139                 fixed_init_half(3),
2140                 fixed_init(4),
2141                 fixed_init_half(4)
2142         };
2143         fixed20_12 memtrbs_r4xx[8] = {
2144                 fixed_init(4),
2145                 fixed_init(5),
2146                 fixed_init(6),
2147                 fixed_init(7),
2148                 fixed_init(8),
2149                 fixed_init(9),
2150                 fixed_init(10),
2151                 fixed_init(11)
2152         };
2153         fixed20_12 min_mem_eff;
2154         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2155         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2156         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2157                 disp_drain_rate2, read_return_rate;
2158         fixed20_12 time_disp1_drop_priority;
2159         int c;
2160         int cur_size = 16;       /* in octawords */
2161         int critical_point = 0, critical_point2;
2162 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2163         int stop_req, max_stop_req;
2164         struct drm_display_mode *mode1 = NULL;
2165         struct drm_display_mode *mode2 = NULL;
2166         uint32_t pixel_bytes1 = 0;
2167         uint32_t pixel_bytes2 = 0;
2168
2169         if (rdev->mode_info.crtcs[0]->base.enabled) {
2170                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2171                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2172         }
2173         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2174                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2175                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2176                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2177                 }
2178         }
2179
2180         min_mem_eff.full = rfixed_const_8(0);
2181         /* get modes */
2182         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2183                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2184                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2185                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2186                 /* check crtc enables */
2187                 if (mode2)
2188                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2189                 if (mode1)
2190                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2191                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2192         }
2193
2194         /*
2195          * determine is there is enough bw for current mode
2196          */
2197         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2198         temp_ff.full = rfixed_const(100);
2199         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2200         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2201         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2202
2203         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2204         temp_ff.full = rfixed_const(temp);
2205         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2206
2207         pix_clk.full = 0;
2208         pix_clk2.full = 0;
2209         peak_disp_bw.full = 0;
2210         if (mode1) {
2211                 temp_ff.full = rfixed_const(1000);
2212                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2213                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2214                 temp_ff.full = rfixed_const(pixel_bytes1);
2215                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2216         }
2217         if (mode2) {
2218                 temp_ff.full = rfixed_const(1000);
2219                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2220                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2221                 temp_ff.full = rfixed_const(pixel_bytes2);
2222                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2223         }
2224
2225         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2226         if (peak_disp_bw.full >= mem_bw.full) {
2227                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2228                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2229         }
2230
2231         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2232         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2233         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2234                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2235                 mem_trp  = ((temp & 0x3)) + 1;
2236                 mem_tras = ((temp & 0x70) >> 4) + 1;
2237         } else if (rdev->family == CHIP_R300 ||
2238                    rdev->family == CHIP_R350) { /* r300, r350 */
2239                 mem_trcd = (temp & 0x7) + 1;
2240                 mem_trp = ((temp >> 8) & 0x7) + 1;
2241                 mem_tras = ((temp >> 11) & 0xf) + 4;
2242         } else if (rdev->family == CHIP_RV350 ||
2243                    rdev->family <= CHIP_RV380) {
2244                 /* rv3x0 */
2245                 mem_trcd = (temp & 0x7) + 3;
2246                 mem_trp = ((temp >> 8) & 0x7) + 3;
2247                 mem_tras = ((temp >> 11) & 0xf) + 6;
2248         } else if (rdev->family == CHIP_R420 ||
2249                    rdev->family == CHIP_R423 ||
2250                    rdev->family == CHIP_RV410) {
2251                 /* r4xx */
2252                 mem_trcd = (temp & 0xf) + 3;
2253                 if (mem_trcd > 15)
2254                         mem_trcd = 15;
2255                 mem_trp = ((temp >> 8) & 0xf) + 3;
2256                 if (mem_trp > 15)
2257                         mem_trp = 15;
2258                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2259                 if (mem_tras > 31)
2260                         mem_tras = 31;
2261         } else { /* RV200, R200 */
2262                 mem_trcd = (temp & 0x7) + 1;
2263                 mem_trp = ((temp >> 8) & 0x7) + 1;
2264                 mem_tras = ((temp >> 12) & 0xf) + 4;
2265         }
2266         /* convert to FF */
2267         trcd_ff.full = rfixed_const(mem_trcd);
2268         trp_ff.full = rfixed_const(mem_trp);
2269         tras_ff.full = rfixed_const(mem_tras);
2270
2271         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2272         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2273         data = (temp & (7 << 20)) >> 20;
2274         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2275                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2276                         tcas_ff = memtcas_rs480_ff[data];
2277                 else
2278                         tcas_ff = memtcas_ff[data];
2279         } else
2280                 tcas_ff = memtcas2_ff[data];
2281
2282         if (rdev->family == CHIP_RS400 ||
2283             rdev->family == CHIP_RS480) {
2284                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2285                 data = (temp >> 23) & 0x7;
2286                 if (data < 5)
2287                         tcas_ff.full += rfixed_const(data);
2288         }
2289
2290         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2291                 /* on the R300, Tcas is included in Trbs.
2292                  */
2293                 temp = RREG32(RADEON_MEM_CNTL);
2294                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2295                 if (data == 1) {
2296                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2297                                 temp = RREG32(R300_MC_IND_INDEX);
2298                                 temp &= ~R300_MC_IND_ADDR_MASK;
2299                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2300                                 WREG32(R300_MC_IND_INDEX, temp);
2301                                 temp = RREG32(R300_MC_IND_DATA);
2302                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2303                         } else {
2304                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2305                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2306                         }
2307                 } else {
2308                         temp = RREG32(R300_MC_READ_CNTL_AB);
2309                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2310                 }
2311                 if (rdev->family == CHIP_RV410 ||
2312                     rdev->family == CHIP_R420 ||
2313                     rdev->family == CHIP_R423)
2314                         trbs_ff = memtrbs_r4xx[data];
2315                 else
2316                         trbs_ff = memtrbs[data];
2317                 tcas_ff.full += trbs_ff.full;
2318         }
2319
2320         sclk_eff_ff.full = sclk_ff.full;
2321
2322         if (rdev->flags & RADEON_IS_AGP) {
2323                 fixed20_12 agpmode_ff;
2324                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2325                 temp_ff.full = rfixed_const_666(16);
2326                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2327         }
2328         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2329
2330         if (ASIC_IS_R300(rdev)) {
2331                 sclk_delay_ff.full = rfixed_const(250);
2332         } else {
2333                 if ((rdev->family == CHIP_RV100) ||
2334                     rdev->flags & RADEON_IS_IGP) {
2335                         if (rdev->mc.vram_is_ddr)
2336                                 sclk_delay_ff.full = rfixed_const(41);
2337                         else
2338                                 sclk_delay_ff.full = rfixed_const(33);
2339                 } else {
2340                         if (rdev->mc.vram_width == 128)
2341                                 sclk_delay_ff.full = rfixed_const(57);
2342                         else
2343                                 sclk_delay_ff.full = rfixed_const(41);
2344                 }
2345         }
2346
2347         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2348
2349         if (rdev->mc.vram_is_ddr) {
2350                 if (rdev->mc.vram_width == 32) {
2351                         k1.full = rfixed_const(40);
2352                         c  = 3;
2353                 } else {
2354                         k1.full = rfixed_const(20);
2355                         c  = 1;
2356                 }
2357         } else {
2358                 k1.full = rfixed_const(40);
2359                 c  = 3;
2360         }
2361
2362         temp_ff.full = rfixed_const(2);
2363         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2364         temp_ff.full = rfixed_const(c);
2365         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2366         temp_ff.full = rfixed_const(4);
2367         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2368         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2369         mc_latency_mclk.full += k1.full;
2370
2371         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2372         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2373
2374         /*
2375           HW cursor time assuming worst case of full size colour cursor.
2376         */
2377         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2378         temp_ff.full += trcd_ff.full;
2379         if (temp_ff.full < tras_ff.full)
2380                 temp_ff.full = tras_ff.full;
2381         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2382
2383         temp_ff.full = rfixed_const(cur_size);
2384         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2385         /*
2386           Find the total latency for the display data.
2387         */
2388         disp_latency_overhead.full = rfixed_const(8);
2389         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2390         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2391         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2392
2393         if (mc_latency_mclk.full > mc_latency_sclk.full)
2394                 disp_latency.full = mc_latency_mclk.full;
2395         else
2396                 disp_latency.full = mc_latency_sclk.full;
2397
2398         /* setup Max GRPH_STOP_REQ default value */
2399         if (ASIC_IS_RV100(rdev))
2400                 max_stop_req = 0x5c;
2401         else
2402                 max_stop_req = 0x7c;
2403
2404         if (mode1) {
2405                 /*  CRTC1
2406                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2407                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2408                 */
2409                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2410
2411                 if (stop_req > max_stop_req)
2412                         stop_req = max_stop_req;
2413
2414                 /*
2415                   Find the drain rate of the display buffer.
2416                 */
2417                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2418                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2419
2420                 /*
2421                   Find the critical point of the display buffer.
2422                 */
2423                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2424                 crit_point_ff.full += rfixed_const_half(0);
2425
2426                 critical_point = rfixed_trunc(crit_point_ff);
2427
2428                 if (rdev->disp_priority == 2) {
2429                         critical_point = 0;
2430                 }
2431
2432                 /*
2433                   The critical point should never be above max_stop_req-4.  Setting
2434                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2435                 */
2436                 if (max_stop_req - critical_point < 4)
2437                         critical_point = 0;
2438
2439                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2440                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2441                         critical_point = 0x10;
2442                 }
2443
2444                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2445                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2446                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2447                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2448                 if ((rdev->family == CHIP_R350) &&
2449                     (stop_req > 0x15)) {
2450                         stop_req -= 0x10;
2451                 }
2452                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2453                 temp |= RADEON_GRPH_BUFFER_SIZE;
2454                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2455                           RADEON_GRPH_CRITICAL_AT_SOF |
2456                           RADEON_GRPH_STOP_CNTL);
2457                 /*
2458                   Write the result into the register.
2459                 */
2460                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2461                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2462
2463 #if 0
2464                 if ((rdev->family == CHIP_RS400) ||
2465                     (rdev->family == CHIP_RS480)) {
2466                         /* attempt to program RS400 disp regs correctly ??? */
2467                         temp = RREG32(RS400_DISP1_REG_CNTL);
2468                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2469                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2470                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2471                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2472                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2473                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2474                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2475                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2476                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2477                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2478                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2479                 }
2480 #endif
2481
2482                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2483                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2484                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2485         }
2486
2487         if (mode2) {
2488                 u32 grph2_cntl;
2489                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2490
2491                 if (stop_req > max_stop_req)
2492                         stop_req = max_stop_req;
2493
2494                 /*
2495                   Find the drain rate of the display buffer.
2496                 */
2497                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2498                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2499
2500                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2501                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2502                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2503                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2504                 if ((rdev->family == CHIP_R350) &&
2505                     (stop_req > 0x15)) {
2506                         stop_req -= 0x10;
2507                 }
2508                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2509                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2510                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2511                           RADEON_GRPH_CRITICAL_AT_SOF |
2512                           RADEON_GRPH_STOP_CNTL);
2513
2514                 if ((rdev->family == CHIP_RS100) ||
2515                     (rdev->family == CHIP_RS200))
2516                         critical_point2 = 0;
2517                 else {
2518                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2519                         temp_ff.full = rfixed_const(temp);
2520                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2521                         if (sclk_ff.full < temp_ff.full)
2522                                 temp_ff.full = sclk_ff.full;
2523
2524                         read_return_rate.full = temp_ff.full;
2525
2526                         if (mode1) {
2527                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2528                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2529                         } else {
2530                                 time_disp1_drop_priority.full = 0;
2531                         }
2532                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2533                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2534                         crit_point_ff.full += rfixed_const_half(0);
2535
2536                         critical_point2 = rfixed_trunc(crit_point_ff);
2537
2538                         if (rdev->disp_priority == 2) {
2539                                 critical_point2 = 0;
2540                         }
2541
2542                         if (max_stop_req - critical_point2 < 4)
2543                                 critical_point2 = 0;
2544
2545                 }
2546
2547                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2548                         /* some R300 cards have problem with this set to 0 */
2549                         critical_point2 = 0x10;
2550                 }
2551
2552                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2553                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2554
2555                 if ((rdev->family == CHIP_RS400) ||
2556                     (rdev->family == CHIP_RS480)) {
2557 #if 0
2558                         /* attempt to program RS400 disp2 regs correctly ??? */
2559                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2560                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2561                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2562                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2563                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2564                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2565                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2566                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2567                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2568                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2569                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2570                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2571 #endif
2572                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2573                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2574                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2575                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2576                 }
2577
2578                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2579                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2580         }
2581 }
2582
2583 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2584 {
2585         DRM_ERROR("pitch                      %d\n", t->pitch);
2586         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2587         DRM_ERROR("width                      %d\n", t->width);
2588         DRM_ERROR("width_11                   %d\n", t->width_11);
2589         DRM_ERROR("height                     %d\n", t->height);
2590         DRM_ERROR("height_11                  %d\n", t->height_11);
2591         DRM_ERROR("num levels                 %d\n", t->num_levels);
2592         DRM_ERROR("depth                      %d\n", t->txdepth);
2593         DRM_ERROR("bpp                        %d\n", t->cpp);
2594         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2595         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2596         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2597 }
2598
2599 static int r100_cs_track_cube(struct radeon_device *rdev,
2600                               struct r100_cs_track *track, unsigned idx)
2601 {
2602         unsigned face, w, h;
2603         struct radeon_object *cube_robj;
2604         unsigned long size;
2605
2606         for (face = 0; face < 5; face++) {
2607                 cube_robj = track->textures[idx].cube_info[face].robj;
2608                 w = track->textures[idx].cube_info[face].width;
2609                 h = track->textures[idx].cube_info[face].height;
2610
2611                 size = w * h;
2612                 size *= track->textures[idx].cpp;
2613
2614                 size += track->textures[idx].cube_info[face].offset;
2615
2616                 if (size > radeon_object_size(cube_robj)) {
2617                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2618                                   size, radeon_object_size(cube_robj));
2619                         r100_cs_track_texture_print(&track->textures[idx]);
2620                         return -1;
2621                 }
2622         }
2623         return 0;
2624 }
2625
2626 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2627                                        struct r100_cs_track *track)
2628 {
2629         struct radeon_object *robj;
2630         unsigned long size;
2631         unsigned u, i, w, h;
2632         int ret;
2633
2634         for (u = 0; u < track->num_texture; u++) {
2635                 if (!track->textures[u].enabled)
2636                         continue;
2637                 robj = track->textures[u].robj;
2638                 if (robj == NULL) {
2639                         DRM_ERROR("No texture bound to unit %u\n", u);
2640                         return -EINVAL;
2641                 }
2642                 size = 0;
2643                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2644                         if (track->textures[u].use_pitch) {
2645                                 if (rdev->family < CHIP_R300)
2646                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2647                                 else
2648                                         w = track->textures[u].pitch / (1 << i);
2649                         } else {
2650                                 w = track->textures[u].width;
2651                                 if (rdev->family >= CHIP_RV515)
2652                                         w |= track->textures[u].width_11;
2653                                 w = w / (1 << i);
2654                                 if (track->textures[u].roundup_w)
2655                                         w = roundup_pow_of_two(w);
2656                         }
2657                         h = track->textures[u].height;
2658                         if (rdev->family >= CHIP_RV515)
2659                                 h |= track->textures[u].height_11;
2660                         h = h / (1 << i);
2661                         if (track->textures[u].roundup_h)
2662                                 h = roundup_pow_of_two(h);
2663                         size += w * h;
2664                 }
2665                 size *= track->textures[u].cpp;
2666                 switch (track->textures[u].tex_coord_type) {
2667                 case 0:
2668                         break;
2669                 case 1:
2670                         size *= (1 << track->textures[u].txdepth);
2671                         break;
2672                 case 2:
2673                         if (track->separate_cube) {
2674                                 ret = r100_cs_track_cube(rdev, track, u);
2675                                 if (ret)
2676                                         return ret;
2677                         } else
2678                                 size *= 6;
2679                         break;
2680                 default:
2681                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2682                                   "%u\n", track->textures[u].tex_coord_type, u);
2683                         return -EINVAL;
2684                 }
2685                 if (size > radeon_object_size(robj)) {
2686                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2687                                   "%lu\n", u, size, radeon_object_size(robj));
2688                         r100_cs_track_texture_print(&track->textures[u]);
2689                         return -EINVAL;
2690                 }
2691         }
2692         return 0;
2693 }
2694
2695 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2696 {
2697         unsigned i;
2698         unsigned long size;
2699         unsigned prim_walk;
2700         unsigned nverts;
2701
2702         for (i = 0; i < track->num_cb; i++) {
2703                 if (track->cb[i].robj == NULL) {
2704                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2705                         return -EINVAL;
2706                 }
2707                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2708                 size += track->cb[i].offset;
2709                 if (size > radeon_object_size(track->cb[i].robj)) {
2710                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2711                                   "(need %lu have %lu) !\n", i, size,
2712                                   radeon_object_size(track->cb[i].robj));
2713                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2714                                   i, track->cb[i].pitch, track->cb[i].cpp,
2715                                   track->cb[i].offset, track->maxy);
2716                         return -EINVAL;
2717                 }
2718         }
2719         if (track->z_enabled) {
2720                 if (track->zb.robj == NULL) {
2721                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2722                         return -EINVAL;
2723                 }
2724                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2725                 size += track->zb.offset;
2726                 if (size > radeon_object_size(track->zb.robj)) {
2727                         DRM_ERROR("[drm] Buffer too small for z buffer "
2728                                   "(need %lu have %lu) !\n", size,
2729                                   radeon_object_size(track->zb.robj));
2730                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2731                                   track->zb.pitch, track->zb.cpp,
2732                                   track->zb.offset, track->maxy);
2733                         return -EINVAL;
2734                 }
2735         }
2736         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2737         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2738         switch (prim_walk) {
2739         case 1:
2740                 for (i = 0; i < track->num_arrays; i++) {
2741                         size = track->arrays[i].esize * track->max_indx * 4;
2742                         if (track->arrays[i].robj == NULL) {
2743                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2744                                           "bound\n", prim_walk, i);
2745                                 return -EINVAL;
2746                         }
2747                         if (size > radeon_object_size(track->arrays[i].robj)) {
2748                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2749                                            "have %lu dwords\n", prim_walk, i,
2750                                            size >> 2,
2751                                            radeon_object_size(track->arrays[i].robj) >> 2);
2752                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2753                                 return -EINVAL;
2754                         }
2755                 }
2756                 break;
2757         case 2:
2758                 for (i = 0; i < track->num_arrays; i++) {
2759                         size = track->arrays[i].esize * (nverts - 1) * 4;
2760                         if (track->arrays[i].robj == NULL) {
2761                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2762                                           "bound\n", prim_walk, i);
2763                                 return -EINVAL;
2764                         }
2765                         if (size > radeon_object_size(track->arrays[i].robj)) {
2766                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2767                                            "have %lu dwords\n", prim_walk, i, size >> 2,
2768                                            radeon_object_size(track->arrays[i].robj) >> 2);
2769                                 return -EINVAL;
2770                         }
2771                 }
2772                 break;
2773         case 3:
2774                 size = track->vtx_size * nverts;
2775                 if (size != track->immd_dwords) {
2776                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2777                                   track->immd_dwords, size);
2778                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2779                                   nverts, track->vtx_size);
2780                         return -EINVAL;
2781                 }
2782                 break;
2783         default:
2784                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2785                           prim_walk);
2786                 return -EINVAL;
2787         }
2788         return r100_cs_track_texture_check(rdev, track);
2789 }
2790
2791 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2792 {
2793         unsigned i, face;
2794
2795         if (rdev->family < CHIP_R300) {
2796                 track->num_cb = 1;
2797                 if (rdev->family <= CHIP_RS200)
2798                         track->num_texture = 3;
2799                 else
2800                         track->num_texture = 6;
2801                 track->maxy = 2048;
2802                 track->separate_cube = 1;
2803         } else {
2804                 track->num_cb = 4;
2805                 track->num_texture = 16;
2806                 track->maxy = 4096;
2807                 track->separate_cube = 0;
2808         }
2809
2810         for (i = 0; i < track->num_cb; i++) {
2811                 track->cb[i].robj = NULL;
2812                 track->cb[i].pitch = 8192;
2813                 track->cb[i].cpp = 16;
2814                 track->cb[i].offset = 0;
2815         }
2816         track->z_enabled = true;
2817         track->zb.robj = NULL;
2818         track->zb.pitch = 8192;
2819         track->zb.cpp = 4;
2820         track->zb.offset = 0;
2821         track->vtx_size = 0x7F;
2822         track->immd_dwords = 0xFFFFFFFFUL;
2823         track->num_arrays = 11;
2824         track->max_indx = 0x00FFFFFFUL;
2825         for (i = 0; i < track->num_arrays; i++) {
2826                 track->arrays[i].robj = NULL;
2827                 track->arrays[i].esize = 0x7F;
2828         }
2829         for (i = 0; i < track->num_texture; i++) {
2830                 track->textures[i].pitch = 16536;
2831                 track->textures[i].width = 16536;
2832                 track->textures[i].height = 16536;
2833                 track->textures[i].width_11 = 1 << 11;
2834                 track->textures[i].height_11 = 1 << 11;
2835                 track->textures[i].num_levels = 12;
2836                 if (rdev->family <= CHIP_RS200) {
2837                         track->textures[i].tex_coord_type = 0;
2838                         track->textures[i].txdepth = 0;
2839                 } else {
2840                         track->textures[i].txdepth = 16;
2841                         track->textures[i].tex_coord_type = 1;
2842                 }
2843                 track->textures[i].cpp = 64;
2844                 track->textures[i].robj = NULL;
2845                 /* CS IB emission code makes sure texture unit are disabled */
2846                 track->textures[i].enabled = false;
2847                 track->textures[i].roundup_w = true;
2848                 track->textures[i].roundup_h = true;
2849                 if (track->separate_cube)
2850                         for (face = 0; face < 5; face++) {
2851                                 track->textures[i].cube_info[face].robj = NULL;
2852                                 track->textures[i].cube_info[face].width = 16536;
2853                                 track->textures[i].cube_info[face].height = 16536;
2854                                 track->textures[i].cube_info[face].offset = 0;
2855                         }
2856         }
2857 }
2858
2859 int r100_ring_test(struct radeon_device *rdev)
2860 {
2861         uint32_t scratch;
2862         uint32_t tmp = 0;
2863         unsigned i;
2864         int r;
2865
2866         r = radeon_scratch_get(rdev, &scratch);
2867         if (r) {
2868                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2869                 return r;
2870         }
2871         WREG32(scratch, 0xCAFEDEAD);
2872         r = radeon_ring_lock(rdev, 2);
2873         if (r) {
2874                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2875                 radeon_scratch_free(rdev, scratch);
2876                 return r;
2877         }
2878         radeon_ring_write(rdev, PACKET0(scratch, 0));
2879         radeon_ring_write(rdev, 0xDEADBEEF);
2880         radeon_ring_unlock_commit(rdev);
2881         for (i = 0; i < rdev->usec_timeout; i++) {
2882                 tmp = RREG32(scratch);
2883                 if (tmp == 0xDEADBEEF) {
2884                         break;
2885                 }
2886                 DRM_UDELAY(1);
2887         }
2888         if (i < rdev->usec_timeout) {
2889                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2890         } else {
2891                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
2892                           scratch, tmp);
2893                 r = -EINVAL;
2894         }
2895         radeon_scratch_free(rdev, scratch);
2896         return r;
2897 }
2898
2899 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2900 {
2901         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
2902         radeon_ring_write(rdev, ib->gpu_addr);
2903         radeon_ring_write(rdev, ib->length_dw);
2904 }
2905
2906 int r100_ib_test(struct radeon_device *rdev)
2907 {
2908         struct radeon_ib *ib;
2909         uint32_t scratch;
2910         uint32_t tmp = 0;
2911         unsigned i;
2912         int r;
2913
2914         r = radeon_scratch_get(rdev, &scratch);
2915         if (r) {
2916                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2917                 return r;
2918         }
2919         WREG32(scratch, 0xCAFEDEAD);
2920         r = radeon_ib_get(rdev, &ib);
2921         if (r) {
2922                 return r;
2923         }
2924         ib->ptr[0] = PACKET0(scratch, 0);
2925         ib->ptr[1] = 0xDEADBEEF;
2926         ib->ptr[2] = PACKET2(0);
2927         ib->ptr[3] = PACKET2(0);
2928         ib->ptr[4] = PACKET2(0);
2929         ib->ptr[5] = PACKET2(0);
2930         ib->ptr[6] = PACKET2(0);
2931         ib->ptr[7] = PACKET2(0);
2932         ib->length_dw = 8;
2933         r = radeon_ib_schedule(rdev, ib);
2934         if (r) {
2935                 radeon_scratch_free(rdev, scratch);
2936                 radeon_ib_free(rdev, &ib);
2937                 return r;
2938         }
2939         r = radeon_fence_wait(ib->fence, false);
2940         if (r) {
2941                 return r;
2942         }
2943         for (i = 0; i < rdev->usec_timeout; i++) {
2944                 tmp = RREG32(scratch);
2945                 if (tmp == 0xDEADBEEF) {
2946                         break;
2947                 }
2948                 DRM_UDELAY(1);
2949         }
2950         if (i < rdev->usec_timeout) {
2951                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2952         } else {
2953                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2954                           scratch, tmp);
2955                 r = -EINVAL;
2956         }
2957         radeon_scratch_free(rdev, scratch);
2958         radeon_ib_free(rdev, &ib);
2959         return r;
2960 }
2961
2962 void r100_ib_fini(struct radeon_device *rdev)
2963 {
2964         radeon_ib_pool_fini(rdev);
2965 }
2966
2967 int r100_ib_init(struct radeon_device *rdev)
2968 {
2969         int r;
2970
2971         r = radeon_ib_pool_init(rdev);
2972         if (r) {
2973                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
2974                 r100_ib_fini(rdev);
2975                 return r;
2976         }
2977         r = r100_ib_test(rdev);
2978         if (r) {
2979                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
2980                 r100_ib_fini(rdev);
2981                 return r;
2982         }
2983         return 0;
2984 }
2985
2986 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
2987 {
2988         /* Shutdown CP we shouldn't need to do that but better be safe than
2989          * sorry
2990          */
2991         rdev->cp.ready = false;
2992         WREG32(R_000740_CP_CSQ_CNTL, 0);
2993
2994         /* Save few CRTC registers */
2995         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
2996         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
2997         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
2998         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
2999         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3000                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3001                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3002         }
3003
3004         /* Disable VGA aperture access */
3005         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3006         /* Disable cursor, overlay, crtc */
3007         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3008         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3009                                         S_000054_CRTC_DISPLAY_DIS(1));
3010         WREG32(R_000050_CRTC_GEN_CNTL,
3011                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3012                         S_000050_CRTC_DISP_REQ_EN_B(1));
3013         WREG32(R_000420_OV0_SCALE_CNTL,
3014                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3015         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3016         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3017                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3018                                                 S_000360_CUR2_LOCK(1));
3019                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3020                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3021                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3022                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3023                 WREG32(R_000360_CUR2_OFFSET,
3024                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3025         }
3026 }
3027
3028 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3029 {
3030         /* Update base address for crtc */
3031         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3032         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3033                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3034                                 rdev->mc.vram_location);
3035         }
3036         /* Restore CRTC registers */
3037         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3038         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3039         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3040         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3041                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3042         }
3043 }
3044
3045 void r100_vga_render_disable(struct radeon_device *rdev)
3046 {
3047         u32 tmp;
3048
3049         tmp = RREG8(R_0003C2_GENMO_WT);
3050         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3051 }
3052
3053 static void r100_debugfs(struct radeon_device *rdev)
3054 {
3055         int r;
3056
3057         r = r100_debugfs_mc_info_init(rdev);
3058         if (r)
3059                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3060 }
3061
3062 static void r100_mc_program(struct radeon_device *rdev)
3063 {
3064         struct r100_mc_save save;
3065
3066         /* Stops all mc clients */
3067         r100_mc_stop(rdev, &save);
3068         if (rdev->flags & RADEON_IS_AGP) {
3069                 WREG32(R_00014C_MC_AGP_LOCATION,
3070                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3071                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3072                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3073                 if (rdev->family > CHIP_RV200)
3074                         WREG32(R_00015C_AGP_BASE_2,
3075                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3076         } else {
3077                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3078                 WREG32(R_000170_AGP_BASE, 0);
3079                 if (rdev->family > CHIP_RV200)
3080                         WREG32(R_00015C_AGP_BASE_2, 0);
3081         }
3082         /* Wait for mc idle */
3083         if (r100_mc_wait_for_idle(rdev))
3084                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3085         /* Program MC, should be a 32bits limited address space */
3086         WREG32(R_000148_MC_FB_LOCATION,
3087                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3088                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3089         r100_mc_resume(rdev, &save);
3090 }
3091
3092 void r100_clock_startup(struct radeon_device *rdev)
3093 {
3094         u32 tmp;
3095
3096         if (radeon_dynclks != -1 && radeon_dynclks)
3097                 radeon_legacy_set_clock_gating(rdev, 1);
3098         /* We need to force on some of the block */
3099         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3100         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3101         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3102                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3103         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3104 }
3105
3106 static int r100_startup(struct radeon_device *rdev)
3107 {
3108         int r;
3109
3110         r100_mc_program(rdev);
3111         /* Resume clock */
3112         r100_clock_startup(rdev);
3113         /* Initialize GPU configuration (# pipes, ...) */
3114         r100_gpu_init(rdev);
3115         /* Initialize GART (initialize after TTM so we can allocate
3116          * memory through TTM but finalize after TTM) */
3117         r100_enable_bm(rdev);
3118         if (rdev->flags & RADEON_IS_PCI) {
3119                 r = r100_pci_gart_enable(rdev);
3120                 if (r)
3121                         return r;
3122         }
3123         /* Enable IRQ */
3124         rdev->irq.sw_int = true;
3125         r100_irq_set(rdev);
3126         /* 1M ring buffer */
3127         r = r100_cp_init(rdev, 1024 * 1024);
3128         if (r) {
3129                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3130                 return r;
3131         }
3132         r = r100_wb_init(rdev);
3133         if (r)
3134                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3135         r = r100_ib_init(rdev);
3136         if (r) {
3137                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3138                 return r;
3139         }
3140         return 0;
3141 }
3142
3143 int r100_resume(struct radeon_device *rdev)
3144 {
3145         /* Make sur GART are not working */
3146         if (rdev->flags & RADEON_IS_PCI)
3147                 r100_pci_gart_disable(rdev);
3148         /* Resume clock before doing reset */
3149         r100_clock_startup(rdev);
3150         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3151         if (radeon_gpu_reset(rdev)) {
3152                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3153                         RREG32(R_000E40_RBBM_STATUS),
3154                         RREG32(R_0007C0_CP_STAT));
3155         }
3156         /* post */
3157         radeon_combios_asic_init(rdev->ddev);
3158         /* Resume clock after posting */
3159         r100_clock_startup(rdev);
3160         return r100_startup(rdev);
3161 }
3162
3163 int r100_suspend(struct radeon_device *rdev)
3164 {
3165         r100_cp_disable(rdev);
3166         r100_wb_disable(rdev);
3167         r100_irq_disable(rdev);
3168         if (rdev->flags & RADEON_IS_PCI)
3169                 r100_pci_gart_disable(rdev);
3170         return 0;
3171 }
3172
3173 void r100_fini(struct radeon_device *rdev)
3174 {
3175         r100_suspend(rdev);
3176         r100_cp_fini(rdev);
3177         r100_wb_fini(rdev);
3178         r100_ib_fini(rdev);
3179         radeon_gem_fini(rdev);
3180         if (rdev->flags & RADEON_IS_PCI)
3181                 r100_pci_gart_fini(rdev);
3182         radeon_irq_kms_fini(rdev);
3183         radeon_fence_driver_fini(rdev);
3184         radeon_object_fini(rdev);
3185         radeon_atombios_fini(rdev);
3186         kfree(rdev->bios);
3187         rdev->bios = NULL;
3188 }
3189
3190 int r100_mc_init(struct radeon_device *rdev)
3191 {
3192         int r;
3193         u32 tmp;
3194
3195         /* Setup GPU memory space */
3196         rdev->mc.vram_location = 0xFFFFFFFFUL;
3197         rdev->mc.gtt_location = 0xFFFFFFFFUL;
3198         if (rdev->flags & RADEON_IS_IGP) {
3199                 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3200                 rdev->mc.vram_location = tmp << 16;
3201         }
3202         if (rdev->flags & RADEON_IS_AGP) {
3203                 r = radeon_agp_init(rdev);
3204                 if (r) {
3205                         printk(KERN_WARNING "[drm] Disabling AGP\n");
3206                         rdev->flags &= ~RADEON_IS_AGP;
3207                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3208                 } else {
3209                         rdev->mc.gtt_location = rdev->mc.agp_base;
3210                 }
3211         }
3212         r = radeon_mc_setup(rdev);
3213         if (r)
3214                 return r;
3215         return 0;
3216 }
3217
3218 int r100_init(struct radeon_device *rdev)
3219 {
3220         int r;
3221
3222         /* Register debugfs file specific to this group of asics */
3223         r100_debugfs(rdev);
3224         /* Disable VGA */
3225         r100_vga_render_disable(rdev);
3226         /* Initialize scratch registers */
3227         radeon_scratch_init(rdev);
3228         /* Initialize surface registers */
3229         radeon_surface_init(rdev);
3230         /* TODO: disable VGA need to use VGA request */
3231         /* BIOS*/
3232         if (!radeon_get_bios(rdev)) {
3233                 if (ASIC_IS_AVIVO(rdev))
3234                         return -EINVAL;
3235         }
3236         if (rdev->is_atom_bios) {
3237                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3238                 return -EINVAL;
3239         } else {
3240                 r = radeon_combios_init(rdev);
3241                 if (r)
3242                         return r;
3243         }
3244         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3245         if (radeon_gpu_reset(rdev)) {
3246                 dev_warn(rdev->dev,
3247                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3248                         RREG32(R_000E40_RBBM_STATUS),
3249                         RREG32(R_0007C0_CP_STAT));
3250         }
3251         /* check if cards are posted or not */
3252         if (!radeon_card_posted(rdev) && rdev->bios) {
3253                 DRM_INFO("GPU not posted. posting now...\n");
3254                 radeon_combios_asic_init(rdev->ddev);
3255         }
3256         /* Set asic errata */
3257         r100_errata(rdev);
3258         /* Initialize clocks */
3259         radeon_get_clock_info(rdev->ddev);
3260         /* Get vram informations */
3261         r100_vram_info(rdev);
3262         /* Initialize memory controller (also test AGP) */
3263         r = r100_mc_init(rdev);
3264         if (r)
3265                 return r;
3266         /* Fence driver */
3267         r = radeon_fence_driver_init(rdev);
3268         if (r)
3269                 return r;
3270         r = radeon_irq_kms_init(rdev);
3271         if (r)
3272                 return r;
3273         /* Memory manager */
3274         r = radeon_object_init(rdev);
3275         if (r)
3276                 return r;
3277         if (rdev->flags & RADEON_IS_PCI) {
3278                 r = r100_pci_gart_init(rdev);
3279                 if (r)
3280                         return r;
3281         }
3282         r100_set_safe_registers(rdev);
3283         rdev->accel_working = true;
3284         r = r100_startup(rdev);
3285         if (r) {
3286                 /* Somethings want wront with the accel init stop accel */
3287                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3288                 r100_suspend(rdev);
3289                 r100_cp_fini(rdev);
3290                 r100_wb_fini(rdev);
3291                 r100_ib_fini(rdev);
3292                 if (rdev->flags & RADEON_IS_PCI)
3293                         r100_pci_gart_fini(rdev);
3294                 radeon_irq_kms_fini(rdev);
3295                 rdev->accel_working = false;
3296         }
3297         return 0;
3298 }