2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
65 #include "r100_track.h"
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
71 void r100_get_power_state(struct radeon_device *rdev,
72 enum radeon_pm_action action)
75 rdev->pm.can_upclock = true;
76 rdev->pm.can_downclock = true;
79 case PM_ACTION_MINIMUM:
80 rdev->pm.requested_power_state_index = 0;
81 rdev->pm.can_downclock = false;
83 case PM_ACTION_DOWNCLOCK:
84 if (rdev->pm.current_power_state_index == 0) {
85 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
86 rdev->pm.can_downclock = false;
88 if (rdev->pm.active_crtc_count > 1) {
89 for (i = 0; i < rdev->pm.num_power_states; i++) {
90 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
92 else if (i >= rdev->pm.current_power_state_index) {
93 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
96 rdev->pm.requested_power_state_index = i;
101 rdev->pm.requested_power_state_index =
102 rdev->pm.current_power_state_index - 1;
105 case PM_ACTION_UPCLOCK:
106 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
107 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
108 rdev->pm.can_upclock = false;
110 if (rdev->pm.active_crtc_count > 1) {
111 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
112 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
114 else if (i <= rdev->pm.current_power_state_index) {
115 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.requested_power_state_index = i;
123 rdev->pm.requested_power_state_index =
124 rdev->pm.current_power_state_index + 1;
127 case PM_ACTION_DEFAULT:
128 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
129 rdev->pm.can_upclock = false;
133 DRM_ERROR("Requested mode for not defined action\n");
136 /* only one clock mode per power state */
137 rdev->pm.requested_clock_mode_index = 0;
139 DRM_INFO("Requested: e: %d m: %d p: %d\n",
140 rdev->pm.power_state[rdev->pm.requested_power_state_index].
141 clock_info[rdev->pm.requested_clock_mode_index].sclk,
142 rdev->pm.power_state[rdev->pm.requested_power_state_index].
143 clock_info[rdev->pm.requested_clock_mode_index].mclk,
144 rdev->pm.power_state[rdev->pm.requested_power_state_index].
148 void r100_set_power_state(struct radeon_device *rdev, bool static_switch)
152 if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
155 if (radeon_gui_idle(rdev)) {
157 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
158 clock_info[rdev->pm.requested_clock_mode_index].sclk;
159 if (sclk > rdev->clock.default_sclk)
160 sclk = rdev->clock.default_sclk;
162 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
163 clock_info[rdev->pm.requested_clock_mode_index].mclk;
164 if (mclk > rdev->clock.default_mclk)
165 mclk = rdev->clock.default_mclk;
166 /* don't change the mclk with multiple crtcs */
167 if (rdev->pm.active_crtc_count > 1)
168 mclk = rdev->clock.default_mclk;
170 /* voltage, pcie lanes, etc.*/
171 radeon_pm_misc(rdev);
174 radeon_pm_prepare(rdev);
175 /* set engine clock */
176 if (sclk != rdev->pm.current_sclk) {
177 radeon_set_engine_clock(rdev, sclk);
178 rdev->pm.current_sclk = sclk;
179 DRM_INFO("Setting: e: %d\n", sclk);
182 /* set memory clock */
183 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
184 radeon_set_memory_clock(rdev, mclk);
185 rdev->pm.current_mclk = mclk;
186 DRM_INFO("Setting: m: %d\n", mclk);
189 radeon_pm_finish(rdev);
191 radeon_sync_with_vblank(rdev);
193 if (!radeon_pm_in_vbl(rdev))
196 /* set engine clock */
197 if (sclk != rdev->pm.current_sclk) {
198 radeon_pm_debug_check_in_vbl(rdev, false);
199 radeon_set_engine_clock(rdev, sclk);
200 radeon_pm_debug_check_in_vbl(rdev, true);
201 rdev->pm.current_sclk = sclk;
202 DRM_INFO("Setting: e: %d\n", sclk);
205 /* set memory clock */
206 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_pm_prepare(rdev);
209 radeon_set_memory_clock(rdev, mclk);
210 radeon_pm_finish(rdev);
211 radeon_pm_debug_check_in_vbl(rdev, true);
212 rdev->pm.current_mclk = mclk;
213 DRM_INFO("Setting: m: %d\n", mclk);
217 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
218 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
220 DRM_INFO("GUI not idle!!!\n");
223 void r100_pm_misc(struct radeon_device *rdev)
226 int requested_index = rdev->pm.requested_power_state_index;
227 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
228 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
229 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
231 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
232 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
233 tmp = RREG32(voltage->gpio.reg);
234 if (voltage->active_high)
235 tmp |= voltage->gpio.mask;
237 tmp &= ~(voltage->gpio.mask);
238 WREG32(voltage->gpio.reg, tmp);
240 udelay(voltage->delay);
242 tmp = RREG32(voltage->gpio.reg);
243 if (voltage->active_high)
244 tmp &= ~voltage->gpio.mask;
246 tmp |= voltage->gpio.mask;
247 WREG32(voltage->gpio.reg, tmp);
249 udelay(voltage->delay);
253 sclk_cntl = RREG32_PLL(SCLK_CNTL);
254 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
255 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
256 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
257 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
258 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
259 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
260 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
261 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
263 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
264 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
265 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
266 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
267 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
269 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
271 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
272 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
273 if (voltage->delay) {
274 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
275 switch (voltage->delay) {
277 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
280 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
283 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
286 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
290 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
292 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
294 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
295 sclk_cntl &= ~FORCE_HDP;
297 sclk_cntl |= FORCE_HDP;
299 WREG32_PLL(SCLK_CNTL, sclk_cntl);
300 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
301 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
304 if ((rdev->flags & RADEON_IS_PCIE) &&
305 !(rdev->flags & RADEON_IS_IGP) &&
306 rdev->asic->set_pcie_lanes &&
308 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
309 radeon_set_pcie_lanes(rdev,
311 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
316 void r100_pm_prepare(struct radeon_device *rdev)
318 struct drm_device *ddev = rdev->ddev;
319 struct drm_crtc *crtc;
320 struct radeon_crtc *radeon_crtc;
323 /* disable any active CRTCs */
324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
325 radeon_crtc = to_radeon_crtc(crtc);
326 if (radeon_crtc->enabled) {
327 if (radeon_crtc->crtc_id) {
328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
332 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
333 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
334 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
340 void r100_pm_finish(struct radeon_device *rdev)
342 struct drm_device *ddev = rdev->ddev;
343 struct drm_crtc *crtc;
344 struct radeon_crtc *radeon_crtc;
347 /* enable any active CRTCs */
348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
349 radeon_crtc = to_radeon_crtc(crtc);
350 if (radeon_crtc->enabled) {
351 if (radeon_crtc->crtc_id) {
352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
356 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
358 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
364 bool r100_gui_idle(struct radeon_device *rdev)
366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
372 /* hpd for digital panel detect/disconnect */
373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
375 bool connected = false;
379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
392 void r100_hpd_set_polarity(struct radeon_device *rdev,
393 enum radeon_hpd_id hpd)
396 bool connected = r100_hpd_sense(rdev, hpd);
400 tmp = RREG32(RADEON_FP_GEN_CNTL);
402 tmp &= ~RADEON_FP_DETECT_INT_POL;
404 tmp |= RADEON_FP_DETECT_INT_POL;
405 WREG32(RADEON_FP_GEN_CNTL, tmp);
408 tmp = RREG32(RADEON_FP2_GEN_CNTL);
410 tmp &= ~RADEON_FP2_DETECT_INT_POL;
412 tmp |= RADEON_FP2_DETECT_INT_POL;
413 WREG32(RADEON_FP2_GEN_CNTL, tmp);
420 void r100_hpd_init(struct radeon_device *rdev)
422 struct drm_device *dev = rdev->ddev;
423 struct drm_connector *connector;
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427 switch (radeon_connector->hpd.hpd) {
429 rdev->irq.hpd[0] = true;
432 rdev->irq.hpd[1] = true;
438 if (rdev->irq.installed)
442 void r100_hpd_fini(struct radeon_device *rdev)
444 struct drm_device *dev = rdev->ddev;
445 struct drm_connector *connector;
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
449 switch (radeon_connector->hpd.hpd) {
451 rdev->irq.hpd[0] = false;
454 rdev->irq.hpd[1] = false;
465 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
467 /* TODO: can we do somethings here ? */
468 /* It seems hw only cache one entry so we should discard this
469 * entry otherwise if first GPU GART read hit this entry it
470 * could end up in wrong address. */
473 int r100_pci_gart_init(struct radeon_device *rdev)
477 if (rdev->gart.table.ram.ptr) {
478 WARN(1, "R100 PCI GART already initialized.\n");
481 /* Initialize common gart structure */
482 r = radeon_gart_init(rdev);
485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
487 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
488 return radeon_gart_table_ram_alloc(rdev);
491 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
492 void r100_enable_bm(struct radeon_device *rdev)
495 /* Enable bus mastering */
496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
497 WREG32(RADEON_BUS_CNTL, tmp);
500 int r100_pci_gart_enable(struct radeon_device *rdev)
504 radeon_gart_restore(rdev);
505 /* discard memory request outside of configured range */
506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
507 WREG32(RADEON_AIC_CNTL, tmp);
508 /* set address range for PCI address translate */
509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
511 /* set PCI GART page-table base address */
512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
514 WREG32(RADEON_AIC_CNTL, tmp);
515 r100_pci_gart_tlb_flush(rdev);
516 rdev->gart.ready = true;
520 void r100_pci_gart_disable(struct radeon_device *rdev)
524 /* discard memory request outside of configured range */
525 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
526 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
527 WREG32(RADEON_AIC_LO_ADDR, 0);
528 WREG32(RADEON_AIC_HI_ADDR, 0);
531 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
533 if (i < 0 || i > rdev->gart.num_gpu_pages) {
536 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
540 void r100_pci_gart_fini(struct radeon_device *rdev)
542 radeon_gart_fini(rdev);
543 r100_pci_gart_disable(rdev);
544 radeon_gart_table_ram_free(rdev);
547 int r100_irq_set(struct radeon_device *rdev)
551 if (!rdev->irq.installed) {
552 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
553 WREG32(R_000040_GEN_INT_CNTL, 0);
556 if (rdev->irq.sw_int) {
557 tmp |= RADEON_SW_INT_ENABLE;
559 if (rdev->irq.gui_idle) {
560 tmp |= RADEON_GUI_IDLE_MASK;
562 if (rdev->irq.crtc_vblank_int[0]) {
563 tmp |= RADEON_CRTC_VBLANK_MASK;
565 if (rdev->irq.crtc_vblank_int[1]) {
566 tmp |= RADEON_CRTC2_VBLANK_MASK;
568 if (rdev->irq.hpd[0]) {
569 tmp |= RADEON_FP_DETECT_MASK;
571 if (rdev->irq.hpd[1]) {
572 tmp |= RADEON_FP2_DETECT_MASK;
574 WREG32(RADEON_GEN_INT_CNTL, tmp);
578 void r100_irq_disable(struct radeon_device *rdev)
582 WREG32(R_000040_GEN_INT_CNTL, 0);
583 /* Wait and acknowledge irq */
585 tmp = RREG32(R_000044_GEN_INT_STATUS);
586 WREG32(R_000044_GEN_INT_STATUS, tmp);
589 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
591 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
592 uint32_t irq_mask = RADEON_SW_INT_TEST |
593 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
594 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
596 /* the interrupt works, but the status bit is permanently asserted */
597 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
598 if (!rdev->irq.gui_idle_acked)
599 irq_mask |= RADEON_GUI_IDLE_STAT;
603 WREG32(RADEON_GEN_INT_STATUS, irqs);
605 return irqs & irq_mask;
608 int r100_irq_process(struct radeon_device *rdev)
610 uint32_t status, msi_rearm;
611 bool queue_hotplug = false;
613 /* reset gui idle ack. the status bit is broken */
614 rdev->irq.gui_idle_acked = false;
616 status = r100_irq_ack(rdev);
620 if (rdev->shutdown) {
625 if (status & RADEON_SW_INT_TEST) {
626 radeon_fence_process(rdev);
628 /* gui idle interrupt */
629 if (status & RADEON_GUI_IDLE_STAT) {
630 rdev->irq.gui_idle_acked = true;
631 rdev->pm.gui_idle = true;
632 wake_up(&rdev->irq.idle_queue);
634 /* Vertical blank interrupts */
635 if (status & RADEON_CRTC_VBLANK_STAT) {
636 drm_handle_vblank(rdev->ddev, 0);
637 rdev->pm.vblank_sync = true;
638 wake_up(&rdev->irq.vblank_queue);
640 if (status & RADEON_CRTC2_VBLANK_STAT) {
641 drm_handle_vblank(rdev->ddev, 1);
642 rdev->pm.vblank_sync = true;
643 wake_up(&rdev->irq.vblank_queue);
645 if (status & RADEON_FP_DETECT_STAT) {
646 queue_hotplug = true;
649 if (status & RADEON_FP2_DETECT_STAT) {
650 queue_hotplug = true;
653 status = r100_irq_ack(rdev);
655 /* reset gui idle ack. the status bit is broken */
656 rdev->irq.gui_idle_acked = false;
658 queue_work(rdev->wq, &rdev->hotplug_work);
659 if (rdev->msi_enabled) {
660 switch (rdev->family) {
663 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
664 WREG32(RADEON_AIC_CNTL, msi_rearm);
665 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
668 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
669 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
670 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
677 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
680 return RREG32(RADEON_CRTC_CRNT_FRAME);
682 return RREG32(RADEON_CRTC2_CRNT_FRAME);
685 /* Who ever call radeon_fence_emit should call ring_lock and ask
686 * for enough space (today caller are ib schedule and buffer move) */
687 void r100_fence_ring_emit(struct radeon_device *rdev,
688 struct radeon_fence *fence)
690 /* We have to make sure that caches are flushed before
691 * CPU might read something from VRAM. */
692 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
693 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
694 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
695 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
696 /* Wait until IDLE & CLEAN */
697 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
698 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
699 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
700 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
701 RADEON_HDP_READ_BUFFER_INVALIDATE);
702 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
703 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
704 /* Emit fence sequence & fire IRQ */
705 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
706 radeon_ring_write(rdev, fence->seq);
707 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
708 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
711 int r100_wb_init(struct radeon_device *rdev)
715 if (rdev->wb.wb_obj == NULL) {
716 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
717 RADEON_GEM_DOMAIN_GTT,
720 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
723 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
724 if (unlikely(r != 0))
726 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
729 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
730 radeon_bo_unreserve(rdev->wb.wb_obj);
733 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
734 radeon_bo_unreserve(rdev->wb.wb_obj);
736 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
740 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
741 WREG32(R_00070C_CP_RB_RPTR_ADDR,
742 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
743 WREG32(R_000770_SCRATCH_UMSK, 0xff);
747 void r100_wb_disable(struct radeon_device *rdev)
749 WREG32(R_000770_SCRATCH_UMSK, 0);
752 void r100_wb_fini(struct radeon_device *rdev)
756 r100_wb_disable(rdev);
757 if (rdev->wb.wb_obj) {
758 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
759 if (unlikely(r != 0)) {
760 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
763 radeon_bo_kunmap(rdev->wb.wb_obj);
764 radeon_bo_unpin(rdev->wb.wb_obj);
765 radeon_bo_unreserve(rdev->wb.wb_obj);
766 radeon_bo_unref(&rdev->wb.wb_obj);
768 rdev->wb.wb_obj = NULL;
772 int r100_copy_blit(struct radeon_device *rdev,
776 struct radeon_fence *fence)
779 uint32_t stride_bytes = PAGE_SIZE;
781 uint32_t stride_pixels;
786 /* radeon limited to 16k stride */
787 stride_bytes &= 0x3fff;
788 /* radeon pitch is /64 */
789 pitch = stride_bytes / 64;
790 stride_pixels = stride_bytes / 4;
791 num_loops = DIV_ROUND_UP(num_pages, 8191);
793 /* Ask for enough room for blit + flush + fence */
794 ndw = 64 + (10 * num_loops);
795 r = radeon_ring_lock(rdev, ndw);
797 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
800 while (num_pages > 0) {
801 cur_pages = num_pages;
802 if (cur_pages > 8191) {
805 num_pages -= cur_pages;
807 /* pages are in Y direction - height
808 page width in X direction - width */
809 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
810 radeon_ring_write(rdev,
811 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
812 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
813 RADEON_GMC_SRC_CLIPPING |
814 RADEON_GMC_DST_CLIPPING |
815 RADEON_GMC_BRUSH_NONE |
816 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
817 RADEON_GMC_SRC_DATATYPE_COLOR |
819 RADEON_DP_SRC_SOURCE_MEMORY |
820 RADEON_GMC_CLR_CMP_CNTL_DIS |
821 RADEON_GMC_WR_MSK_DIS);
822 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
823 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
824 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
825 radeon_ring_write(rdev, 0);
826 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
827 radeon_ring_write(rdev, num_pages);
828 radeon_ring_write(rdev, num_pages);
829 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
831 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
832 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
833 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
834 radeon_ring_write(rdev,
835 RADEON_WAIT_2D_IDLECLEAN |
836 RADEON_WAIT_HOST_IDLECLEAN |
837 RADEON_WAIT_DMA_GUI_IDLE);
839 r = radeon_fence_emit(rdev, fence);
841 radeon_ring_unlock_commit(rdev);
845 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
850 for (i = 0; i < rdev->usec_timeout; i++) {
851 tmp = RREG32(R_000E40_RBBM_STATUS);
852 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
860 void r100_ring_start(struct radeon_device *rdev)
864 r = radeon_ring_lock(rdev, 2);
868 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
869 radeon_ring_write(rdev,
870 RADEON_ISYNC_ANY2D_IDLE3D |
871 RADEON_ISYNC_ANY3D_IDLE2D |
872 RADEON_ISYNC_WAIT_IDLEGUI |
873 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
874 radeon_ring_unlock_commit(rdev);
878 /* Load the microcode for the CP */
879 static int r100_cp_init_microcode(struct radeon_device *rdev)
881 struct platform_device *pdev;
882 const char *fw_name = NULL;
887 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
890 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
893 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
894 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
895 (rdev->family == CHIP_RS200)) {
896 DRM_INFO("Loading R100 Microcode\n");
897 fw_name = FIRMWARE_R100;
898 } else if ((rdev->family == CHIP_R200) ||
899 (rdev->family == CHIP_RV250) ||
900 (rdev->family == CHIP_RV280) ||
901 (rdev->family == CHIP_RS300)) {
902 DRM_INFO("Loading R200 Microcode\n");
903 fw_name = FIRMWARE_R200;
904 } else if ((rdev->family == CHIP_R300) ||
905 (rdev->family == CHIP_R350) ||
906 (rdev->family == CHIP_RV350) ||
907 (rdev->family == CHIP_RV380) ||
908 (rdev->family == CHIP_RS400) ||
909 (rdev->family == CHIP_RS480)) {
910 DRM_INFO("Loading R300 Microcode\n");
911 fw_name = FIRMWARE_R300;
912 } else if ((rdev->family == CHIP_R420) ||
913 (rdev->family == CHIP_R423) ||
914 (rdev->family == CHIP_RV410)) {
915 DRM_INFO("Loading R400 Microcode\n");
916 fw_name = FIRMWARE_R420;
917 } else if ((rdev->family == CHIP_RS690) ||
918 (rdev->family == CHIP_RS740)) {
919 DRM_INFO("Loading RS690/RS740 Microcode\n");
920 fw_name = FIRMWARE_RS690;
921 } else if (rdev->family == CHIP_RS600) {
922 DRM_INFO("Loading RS600 Microcode\n");
923 fw_name = FIRMWARE_RS600;
924 } else if ((rdev->family == CHIP_RV515) ||
925 (rdev->family == CHIP_R520) ||
926 (rdev->family == CHIP_RV530) ||
927 (rdev->family == CHIP_R580) ||
928 (rdev->family == CHIP_RV560) ||
929 (rdev->family == CHIP_RV570)) {
930 DRM_INFO("Loading R500 Microcode\n");
931 fw_name = FIRMWARE_R520;
934 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
935 platform_device_unregister(pdev);
937 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
939 } else if (rdev->me_fw->size % 8) {
941 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
942 rdev->me_fw->size, fw_name);
944 release_firmware(rdev->me_fw);
950 static void r100_cp_load_microcode(struct radeon_device *rdev)
952 const __be32 *fw_data;
955 if (r100_gui_wait_for_idle(rdev)) {
956 printk(KERN_WARNING "Failed to wait GUI idle while "
957 "programming pipes. Bad things might happen.\n");
961 size = rdev->me_fw->size / 4;
962 fw_data = (const __be32 *)&rdev->me_fw->data[0];
963 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
964 for (i = 0; i < size; i += 2) {
965 WREG32(RADEON_CP_ME_RAM_DATAH,
966 be32_to_cpup(&fw_data[i]));
967 WREG32(RADEON_CP_ME_RAM_DATAL,
968 be32_to_cpup(&fw_data[i + 1]));
973 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
978 unsigned pre_write_timer;
979 unsigned pre_write_limit;
980 unsigned indirect2_start;
981 unsigned indirect1_start;
985 if (r100_debugfs_cp_init(rdev)) {
986 DRM_ERROR("Failed to register debugfs file for CP !\n");
989 r = r100_cp_init_microcode(rdev);
991 DRM_ERROR("Failed to load firmware!\n");
996 /* Align ring size */
997 rb_bufsz = drm_order(ring_size / 8);
998 ring_size = (1 << (rb_bufsz + 1)) * 4;
999 r100_cp_load_microcode(rdev);
1000 r = radeon_ring_init(rdev, ring_size);
1004 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1005 * the rptr copy in system ram */
1007 /* cp will read 128bytes at a time (4 dwords) */
1009 rdev->cp.align_mask = 16 - 1;
1010 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1011 pre_write_timer = 64;
1012 /* Force CP_RB_WPTR write if written more than one time before the
1015 pre_write_limit = 0;
1016 /* Setup the cp cache like this (cache size is 96 dwords) :
1018 * INDIRECT1 16 to 79
1019 * INDIRECT2 80 to 95
1020 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1021 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1022 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1023 * Idea being that most of the gpu cmd will be through indirect1 buffer
1024 * so it gets the bigger cache.
1026 indirect2_start = 80;
1027 indirect1_start = 16;
1029 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1030 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1031 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1032 REG_SET(RADEON_MAX_FETCH, max_fetch) |
1033 RADEON_RB_NO_UPDATE);
1035 tmp |= RADEON_BUF_SWAP_32BIT;
1037 WREG32(RADEON_CP_RB_CNTL, tmp);
1039 /* Set ring address */
1040 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1041 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1042 /* Force read & write ptr to 0 */
1043 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1044 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1045 WREG32(RADEON_CP_RB_WPTR, 0);
1046 WREG32(RADEON_CP_RB_CNTL, tmp);
1048 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1049 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1050 /* protect against crazy HW on resume */
1051 rdev->cp.wptr &= rdev->cp.ptr_mask;
1052 /* Set cp mode to bus mastering & enable cp*/
1053 WREG32(RADEON_CP_CSQ_MODE,
1054 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1055 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1057 WREG32(0x744, 0x00004D4D);
1058 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1059 radeon_ring_start(rdev);
1060 r = radeon_ring_test(rdev);
1062 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1065 rdev->cp.ready = true;
1069 void r100_cp_fini(struct radeon_device *rdev)
1071 if (r100_cp_wait_for_idle(rdev)) {
1072 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1075 r100_cp_disable(rdev);
1076 radeon_ring_fini(rdev);
1077 DRM_INFO("radeon: cp finalized\n");
1080 void r100_cp_disable(struct radeon_device *rdev)
1083 rdev->cp.ready = false;
1084 WREG32(RADEON_CP_CSQ_MODE, 0);
1085 WREG32(RADEON_CP_CSQ_CNTL, 0);
1086 if (r100_gui_wait_for_idle(rdev)) {
1087 printk(KERN_WARNING "Failed to wait GUI idle while "
1088 "programming pipes. Bad things might happen.\n");
1092 void r100_cp_commit(struct radeon_device *rdev)
1094 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1095 (void)RREG32(RADEON_CP_RB_WPTR);
1102 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1103 struct radeon_cs_packet *pkt,
1104 const unsigned *auth, unsigned n,
1105 radeon_packet0_check_t check)
1114 /* Check that register fall into register range
1115 * determined by the number of entry (n) in the
1116 * safe register bitmap.
1118 if (pkt->one_reg_wr) {
1119 if ((reg >> 7) > n) {
1123 if (((reg + (pkt->count << 2)) >> 7) > n) {
1127 for (i = 0; i <= pkt->count; i++, idx++) {
1129 m = 1 << ((reg >> 2) & 31);
1131 r = check(p, pkt, idx, reg);
1136 if (pkt->one_reg_wr) {
1137 if (!(auth[j] & m)) {
1147 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1148 struct radeon_cs_packet *pkt)
1150 volatile uint32_t *ib;
1156 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1157 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1162 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1163 * @parser: parser structure holding parsing context.
1164 * @pkt: where to store packet informations
1166 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1167 * if packet is bigger than remaining ib size. or if packets is unknown.
1169 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1170 struct radeon_cs_packet *pkt,
1173 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1176 if (idx >= ib_chunk->length_dw) {
1177 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1178 idx, ib_chunk->length_dw);
1181 header = radeon_get_ib_value(p, idx);
1183 pkt->type = CP_PACKET_GET_TYPE(header);
1184 pkt->count = CP_PACKET_GET_COUNT(header);
1185 switch (pkt->type) {
1187 pkt->reg = CP_PACKET0_GET_REG(header);
1188 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1191 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1197 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1200 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1201 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1202 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1209 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1210 * @parser: parser structure holding parsing context.
1212 * Userspace sends a special sequence for VLINE waits.
1213 * PACKET0 - VLINE_START_END + value
1214 * PACKET0 - WAIT_UNTIL +_value
1215 * RELOC (P3) - crtc_id in reloc.
1217 * This function parses this and relocates the VLINE START END
1218 * and WAIT UNTIL packets to the correct crtc.
1219 * It also detects a switched off crtc and nulls out the
1220 * wait in that case.
1222 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1224 struct drm_mode_object *obj;
1225 struct drm_crtc *crtc;
1226 struct radeon_crtc *radeon_crtc;
1227 struct radeon_cs_packet p3reloc, waitreloc;
1230 uint32_t header, h_idx, reg;
1231 volatile uint32_t *ib;
1235 /* parse the wait until */
1236 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1240 /* check its a wait until and only 1 count */
1241 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1242 waitreloc.count != 0) {
1243 DRM_ERROR("vline wait had illegal wait until segment\n");
1248 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1249 DRM_ERROR("vline wait had illegal wait until\n");
1254 /* jump over the NOP */
1255 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1260 p->idx += waitreloc.count + 2;
1261 p->idx += p3reloc.count + 2;
1263 header = radeon_get_ib_value(p, h_idx);
1264 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1265 reg = CP_PACKET0_GET_REG(header);
1266 mutex_lock(&p->rdev->ddev->mode_config.mutex);
1267 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1269 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1273 crtc = obj_to_crtc(obj);
1274 radeon_crtc = to_radeon_crtc(crtc);
1275 crtc_id = radeon_crtc->crtc_id;
1277 if (!crtc->enabled) {
1278 /* if the CRTC isn't enabled - we need to nop out the wait until */
1279 ib[h_idx + 2] = PACKET2(0);
1280 ib[h_idx + 3] = PACKET2(0);
1281 } else if (crtc_id == 1) {
1283 case AVIVO_D1MODE_VLINE_START_END:
1284 header &= ~R300_CP_PACKET0_REG_MASK;
1285 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1287 case RADEON_CRTC_GUI_TRIG_VLINE:
1288 header &= ~R300_CP_PACKET0_REG_MASK;
1289 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1292 DRM_ERROR("unknown crtc reloc\n");
1297 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1300 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1305 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1306 * @parser: parser structure holding parsing context.
1307 * @data: pointer to relocation data
1308 * @offset_start: starting offset
1309 * @offset_mask: offset mask (to align start offset on)
1310 * @reloc: reloc informations
1312 * Check next packet is relocation packet3, do bo validation and compute
1313 * GPU offset using the provided start.
1315 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1316 struct radeon_cs_reloc **cs_reloc)
1318 struct radeon_cs_chunk *relocs_chunk;
1319 struct radeon_cs_packet p3reloc;
1323 if (p->chunk_relocs_idx == -1) {
1324 DRM_ERROR("No relocation chunk !\n");
1328 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1329 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1333 p->idx += p3reloc.count + 2;
1334 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1335 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1337 r100_cs_dump_packet(p, &p3reloc);
1340 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1341 if (idx >= relocs_chunk->length_dw) {
1342 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1343 idx, relocs_chunk->length_dw);
1344 r100_cs_dump_packet(p, &p3reloc);
1347 /* FIXME: we assume reloc size is 4 dwords */
1348 *cs_reloc = p->relocs_ptr[(idx / 4)];
1352 static int r100_get_vtx_size(uint32_t vtx_fmt)
1356 /* ordered according to bits in spec */
1357 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1359 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1361 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1363 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1365 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1367 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1369 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1371 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1373 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1375 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1377 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1379 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1381 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1383 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1385 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1388 if (vtx_fmt & (0x7 << 15))
1389 vtx_size += (vtx_fmt >> 15) & 0x7;
1390 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1392 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1394 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1396 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1398 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1400 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1405 static int r100_packet0_check(struct radeon_cs_parser *p,
1406 struct radeon_cs_packet *pkt,
1407 unsigned idx, unsigned reg)
1409 struct radeon_cs_reloc *reloc;
1410 struct r100_cs_track *track;
1411 volatile uint32_t *ib;
1419 track = (struct r100_cs_track *)p->track;
1421 idx_value = radeon_get_ib_value(p, idx);
1424 case RADEON_CRTC_GUI_TRIG_VLINE:
1425 r = r100_cs_packet_parse_vline(p);
1427 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1429 r100_cs_dump_packet(p, pkt);
1433 /* FIXME: only allow PACKET3 blit? easier to check for out of
1435 case RADEON_DST_PITCH_OFFSET:
1436 case RADEON_SRC_PITCH_OFFSET:
1437 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1441 case RADEON_RB3D_DEPTHOFFSET:
1442 r = r100_cs_packet_next_reloc(p, &reloc);
1444 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1446 r100_cs_dump_packet(p, pkt);
1449 track->zb.robj = reloc->robj;
1450 track->zb.offset = idx_value;
1451 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1453 case RADEON_RB3D_COLOROFFSET:
1454 r = r100_cs_packet_next_reloc(p, &reloc);
1456 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1458 r100_cs_dump_packet(p, pkt);
1461 track->cb[0].robj = reloc->robj;
1462 track->cb[0].offset = idx_value;
1463 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1465 case RADEON_PP_TXOFFSET_0:
1466 case RADEON_PP_TXOFFSET_1:
1467 case RADEON_PP_TXOFFSET_2:
1468 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1469 r = r100_cs_packet_next_reloc(p, &reloc);
1471 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1473 r100_cs_dump_packet(p, pkt);
1476 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1477 track->textures[i].robj = reloc->robj;
1479 case RADEON_PP_CUBIC_OFFSET_T0_0:
1480 case RADEON_PP_CUBIC_OFFSET_T0_1:
1481 case RADEON_PP_CUBIC_OFFSET_T0_2:
1482 case RADEON_PP_CUBIC_OFFSET_T0_3:
1483 case RADEON_PP_CUBIC_OFFSET_T0_4:
1484 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1485 r = r100_cs_packet_next_reloc(p, &reloc);
1487 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1489 r100_cs_dump_packet(p, pkt);
1492 track->textures[0].cube_info[i].offset = idx_value;
1493 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1494 track->textures[0].cube_info[i].robj = reloc->robj;
1496 case RADEON_PP_CUBIC_OFFSET_T1_0:
1497 case RADEON_PP_CUBIC_OFFSET_T1_1:
1498 case RADEON_PP_CUBIC_OFFSET_T1_2:
1499 case RADEON_PP_CUBIC_OFFSET_T1_3:
1500 case RADEON_PP_CUBIC_OFFSET_T1_4:
1501 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1502 r = r100_cs_packet_next_reloc(p, &reloc);
1504 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506 r100_cs_dump_packet(p, pkt);
1509 track->textures[1].cube_info[i].offset = idx_value;
1510 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1511 track->textures[1].cube_info[i].robj = reloc->robj;
1513 case RADEON_PP_CUBIC_OFFSET_T2_0:
1514 case RADEON_PP_CUBIC_OFFSET_T2_1:
1515 case RADEON_PP_CUBIC_OFFSET_T2_2:
1516 case RADEON_PP_CUBIC_OFFSET_T2_3:
1517 case RADEON_PP_CUBIC_OFFSET_T2_4:
1518 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1519 r = r100_cs_packet_next_reloc(p, &reloc);
1521 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1523 r100_cs_dump_packet(p, pkt);
1526 track->textures[2].cube_info[i].offset = idx_value;
1527 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1528 track->textures[2].cube_info[i].robj = reloc->robj;
1530 case RADEON_RE_WIDTH_HEIGHT:
1531 track->maxy = ((idx_value >> 16) & 0x7FF);
1533 case RADEON_RB3D_COLORPITCH:
1534 r = r100_cs_packet_next_reloc(p, &reloc);
1536 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1538 r100_cs_dump_packet(p, pkt);
1542 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1543 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1544 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1545 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1547 tmp = idx_value & ~(0x7 << 16);
1551 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1553 case RADEON_RB3D_DEPTHPITCH:
1554 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1556 case RADEON_RB3D_CNTL:
1557 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1563 track->cb[0].cpp = 1;
1568 track->cb[0].cpp = 2;
1571 track->cb[0].cpp = 4;
1574 DRM_ERROR("Invalid color buffer format (%d) !\n",
1575 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1578 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1580 case RADEON_RB3D_ZSTENCILCNTL:
1581 switch (idx_value & 0xf) {
1597 case RADEON_RB3D_ZPASS_ADDR:
1598 r = r100_cs_packet_next_reloc(p, &reloc);
1600 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1602 r100_cs_dump_packet(p, pkt);
1605 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1607 case RADEON_PP_CNTL:
1609 uint32_t temp = idx_value >> 4;
1610 for (i = 0; i < track->num_texture; i++)
1611 track->textures[i].enabled = !!(temp & (1 << i));
1614 case RADEON_SE_VF_CNTL:
1615 track->vap_vf_cntl = idx_value;
1617 case RADEON_SE_VTX_FMT:
1618 track->vtx_size = r100_get_vtx_size(idx_value);
1620 case RADEON_PP_TEX_SIZE_0:
1621 case RADEON_PP_TEX_SIZE_1:
1622 case RADEON_PP_TEX_SIZE_2:
1623 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1624 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1625 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1627 case RADEON_PP_TEX_PITCH_0:
1628 case RADEON_PP_TEX_PITCH_1:
1629 case RADEON_PP_TEX_PITCH_2:
1630 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1631 track->textures[i].pitch = idx_value + 32;
1633 case RADEON_PP_TXFILTER_0:
1634 case RADEON_PP_TXFILTER_1:
1635 case RADEON_PP_TXFILTER_2:
1636 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1637 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1638 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1639 tmp = (idx_value >> 23) & 0x7;
1640 if (tmp == 2 || tmp == 6)
1641 track->textures[i].roundup_w = false;
1642 tmp = (idx_value >> 27) & 0x7;
1643 if (tmp == 2 || tmp == 6)
1644 track->textures[i].roundup_h = false;
1646 case RADEON_PP_TXFORMAT_0:
1647 case RADEON_PP_TXFORMAT_1:
1648 case RADEON_PP_TXFORMAT_2:
1649 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1650 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1651 track->textures[i].use_pitch = 1;
1653 track->textures[i].use_pitch = 0;
1654 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1655 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1657 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1658 track->textures[i].tex_coord_type = 2;
1659 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1660 case RADEON_TXFORMAT_I8:
1661 case RADEON_TXFORMAT_RGB332:
1662 case RADEON_TXFORMAT_Y8:
1663 track->textures[i].cpp = 1;
1665 case RADEON_TXFORMAT_AI88:
1666 case RADEON_TXFORMAT_ARGB1555:
1667 case RADEON_TXFORMAT_RGB565:
1668 case RADEON_TXFORMAT_ARGB4444:
1669 case RADEON_TXFORMAT_VYUY422:
1670 case RADEON_TXFORMAT_YVYU422:
1671 case RADEON_TXFORMAT_SHADOW16:
1672 case RADEON_TXFORMAT_LDUDV655:
1673 case RADEON_TXFORMAT_DUDV88:
1674 track->textures[i].cpp = 2;
1676 case RADEON_TXFORMAT_ARGB8888:
1677 case RADEON_TXFORMAT_RGBA8888:
1678 case RADEON_TXFORMAT_SHADOW32:
1679 case RADEON_TXFORMAT_LDUDUV8888:
1680 track->textures[i].cpp = 4;
1682 case RADEON_TXFORMAT_DXT1:
1683 track->textures[i].cpp = 1;
1684 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1686 case RADEON_TXFORMAT_DXT23:
1687 case RADEON_TXFORMAT_DXT45:
1688 track->textures[i].cpp = 1;
1689 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1692 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1693 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1695 case RADEON_PP_CUBIC_FACES_0:
1696 case RADEON_PP_CUBIC_FACES_1:
1697 case RADEON_PP_CUBIC_FACES_2:
1699 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1700 for (face = 0; face < 4; face++) {
1701 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1702 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1706 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1713 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1714 struct radeon_cs_packet *pkt,
1715 struct radeon_bo *robj)
1720 value = radeon_get_ib_value(p, idx + 2);
1721 if ((value + 1) > radeon_bo_size(robj)) {
1722 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1723 "(need %u have %lu) !\n",
1725 radeon_bo_size(robj));
1731 static int r100_packet3_check(struct radeon_cs_parser *p,
1732 struct radeon_cs_packet *pkt)
1734 struct radeon_cs_reloc *reloc;
1735 struct r100_cs_track *track;
1737 volatile uint32_t *ib;
1742 track = (struct r100_cs_track *)p->track;
1743 switch (pkt->opcode) {
1744 case PACKET3_3D_LOAD_VBPNTR:
1745 r = r100_packet3_load_vbpntr(p, pkt, idx);
1749 case PACKET3_INDX_BUFFER:
1750 r = r100_cs_packet_next_reloc(p, &reloc);
1752 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1753 r100_cs_dump_packet(p, pkt);
1756 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1757 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1763 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1764 r = r100_cs_packet_next_reloc(p, &reloc);
1766 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1767 r100_cs_dump_packet(p, pkt);
1770 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1771 track->num_arrays = 1;
1772 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1774 track->arrays[0].robj = reloc->robj;
1775 track->arrays[0].esize = track->vtx_size;
1777 track->max_indx = radeon_get_ib_value(p, idx+1);
1779 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1780 track->immd_dwords = pkt->count - 1;
1781 r = r100_cs_track_check(p->rdev, track);
1785 case PACKET3_3D_DRAW_IMMD:
1786 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1787 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1790 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1791 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1792 track->immd_dwords = pkt->count - 1;
1793 r = r100_cs_track_check(p->rdev, track);
1797 /* triggers drawing using in-packet vertex data */
1798 case PACKET3_3D_DRAW_IMMD_2:
1799 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1800 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1803 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1804 track->immd_dwords = pkt->count;
1805 r = r100_cs_track_check(p->rdev, track);
1809 /* triggers drawing using in-packet vertex data */
1810 case PACKET3_3D_DRAW_VBUF_2:
1811 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1812 r = r100_cs_track_check(p->rdev, track);
1816 /* triggers drawing of vertex buffers setup elsewhere */
1817 case PACKET3_3D_DRAW_INDX_2:
1818 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1819 r = r100_cs_track_check(p->rdev, track);
1823 /* triggers drawing using indices to vertex buffer */
1824 case PACKET3_3D_DRAW_VBUF:
1825 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1826 r = r100_cs_track_check(p->rdev, track);
1830 /* triggers drawing of vertex buffers setup elsewhere */
1831 case PACKET3_3D_DRAW_INDX:
1832 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1833 r = r100_cs_track_check(p->rdev, track);
1837 /* triggers drawing using indices to vertex buffer */
1841 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1847 int r100_cs_parse(struct radeon_cs_parser *p)
1849 struct radeon_cs_packet pkt;
1850 struct r100_cs_track *track;
1853 track = kzalloc(sizeof(*track), GFP_KERNEL);
1854 r100_cs_track_clear(p->rdev, track);
1857 r = r100_cs_packet_parse(p, &pkt, p->idx);
1861 p->idx += pkt.count + 2;
1864 if (p->rdev->family >= CHIP_R200)
1865 r = r100_cs_parse_packet0(p, &pkt,
1866 p->rdev->config.r100.reg_safe_bm,
1867 p->rdev->config.r100.reg_safe_bm_size,
1868 &r200_packet0_check);
1870 r = r100_cs_parse_packet0(p, &pkt,
1871 p->rdev->config.r100.reg_safe_bm,
1872 p->rdev->config.r100.reg_safe_bm_size,
1873 &r100_packet0_check);
1878 r = r100_packet3_check(p, &pkt);
1881 DRM_ERROR("Unknown packet type %d !\n",
1888 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1894 * Global GPU functions
1896 void r100_errata(struct radeon_device *rdev)
1898 rdev->pll_errata = 0;
1900 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1901 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1904 if (rdev->family == CHIP_RV100 ||
1905 rdev->family == CHIP_RS100 ||
1906 rdev->family == CHIP_RS200) {
1907 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1911 /* Wait for vertical sync on primary CRTC */
1912 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1914 uint32_t crtc_gen_cntl, tmp;
1917 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1918 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1919 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1922 /* Clear the CRTC_VBLANK_SAVE bit */
1923 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1924 for (i = 0; i < rdev->usec_timeout; i++) {
1925 tmp = RREG32(RADEON_CRTC_STATUS);
1926 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1933 /* Wait for vertical sync on secondary CRTC */
1934 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1936 uint32_t crtc2_gen_cntl, tmp;
1939 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1940 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1941 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1944 /* Clear the CRTC_VBLANK_SAVE bit */
1945 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1946 for (i = 0; i < rdev->usec_timeout; i++) {
1947 tmp = RREG32(RADEON_CRTC2_STATUS);
1948 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1955 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1960 for (i = 0; i < rdev->usec_timeout; i++) {
1961 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1970 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1975 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1976 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1977 " Bad things might happen.\n");
1979 for (i = 0; i < rdev->usec_timeout; i++) {
1980 tmp = RREG32(RADEON_RBBM_STATUS);
1981 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1989 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1994 for (i = 0; i < rdev->usec_timeout; i++) {
1995 /* read MC_STATUS */
1996 tmp = RREG32(RADEON_MC_STATUS);
1997 if (tmp & RADEON_MC_IDLE) {
2005 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2007 lockup->last_cp_rptr = cp->rptr;
2008 lockup->last_jiffies = jiffies;
2012 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2013 * @rdev: radeon device structure
2014 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2015 * @cp: radeon_cp structure holding CP information
2017 * We don't need to initialize the lockup tracking information as we will either
2018 * have CP rptr to a different value of jiffies wrap around which will force
2019 * initialization of the lockup tracking informations.
2021 * A possible false positivie is if we get call after while and last_cp_rptr ==
2022 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2023 * if the elapsed time since last call is bigger than 2 second than we return
2024 * false and update the tracking information. Due to this the caller must call
2025 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2026 * the fencing code should be cautious about that.
2028 * Caller should write to the ring to force CP to do something so we don't get
2029 * false positive when CP is just gived nothing to do.
2032 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2034 unsigned long cjiffies, elapsed;
2037 if (!time_after(cjiffies, lockup->last_jiffies)) {
2038 /* likely a wrap around */
2039 lockup->last_cp_rptr = cp->rptr;
2040 lockup->last_jiffies = jiffies;
2043 if (cp->rptr != lockup->last_cp_rptr) {
2044 /* CP is still working no lockup */
2045 lockup->last_cp_rptr = cp->rptr;
2046 lockup->last_jiffies = jiffies;
2049 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2050 if (elapsed >= 3000) {
2051 /* very likely the improbable case where current
2052 * rptr is equal to last recorded, a while ago, rptr
2053 * this is more likely a false positive update tracking
2054 * information which should force us to be recall at
2057 lockup->last_cp_rptr = cp->rptr;
2058 lockup->last_jiffies = jiffies;
2061 if (elapsed >= 1000) {
2062 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2065 /* give a chance to the GPU ... */
2069 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2074 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2075 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2076 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2079 /* force CP activities */
2080 r = radeon_ring_lock(rdev, 2);
2083 radeon_ring_write(rdev, 0x80000000);
2084 radeon_ring_write(rdev, 0x80000000);
2085 radeon_ring_unlock_commit(rdev);
2087 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2088 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2091 void r100_bm_disable(struct radeon_device *rdev)
2095 /* disable bus mastering */
2096 tmp = RREG32(R_000030_BUS_CNTL);
2097 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2099 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2101 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2102 tmp = RREG32(RADEON_BUS_CNTL);
2104 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2105 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2109 int r100_asic_reset(struct radeon_device *rdev)
2111 struct r100_mc_save save;
2114 r100_mc_stop(rdev, &save);
2115 status = RREG32(R_000E40_RBBM_STATUS);
2116 if (!G_000E40_GUI_ACTIVE(status)) {
2119 status = RREG32(R_000E40_RBBM_STATUS);
2120 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2122 WREG32(RADEON_CP_CSQ_CNTL, 0);
2123 tmp = RREG32(RADEON_CP_RB_CNTL);
2124 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2125 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2126 WREG32(RADEON_CP_RB_WPTR, 0);
2127 WREG32(RADEON_CP_RB_CNTL, tmp);
2128 /* save PCI state */
2129 pci_save_state(rdev->pdev);
2130 /* disable bus mastering */
2131 r100_bm_disable(rdev);
2132 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2133 S_0000F0_SOFT_RESET_RE(1) |
2134 S_0000F0_SOFT_RESET_PP(1) |
2135 S_0000F0_SOFT_RESET_RB(1));
2136 RREG32(R_0000F0_RBBM_SOFT_RESET);
2138 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2140 status = RREG32(R_000E40_RBBM_STATUS);
2141 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2143 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2144 RREG32(R_0000F0_RBBM_SOFT_RESET);
2146 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2148 status = RREG32(R_000E40_RBBM_STATUS);
2149 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2150 /* restore PCI & busmastering */
2151 pci_restore_state(rdev->pdev);
2152 r100_enable_bm(rdev);
2153 /* Check if GPU is idle */
2154 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2155 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2156 dev_err(rdev->dev, "failed to reset GPU\n");
2157 rdev->gpu_lockup = true;
2160 r100_mc_resume(rdev, &save);
2161 dev_info(rdev->dev, "GPU reset succeed\n");
2165 void r100_set_common_regs(struct radeon_device *rdev)
2167 struct drm_device *dev = rdev->ddev;
2168 bool force_dac2 = false;
2171 /* set these so they don't interfere with anything */
2172 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2173 WREG32(RADEON_SUBPIC_CNTL, 0);
2174 WREG32(RADEON_VIPH_CONTROL, 0);
2175 WREG32(RADEON_I2C_CNTL_1, 0);
2176 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2177 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2178 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2180 /* always set up dac2 on rn50 and some rv100 as lots
2181 * of servers seem to wire it up to a VGA port but
2182 * don't report it in the bios connector
2185 switch (dev->pdev->device) {
2194 /* DELL triple head servers */
2195 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2196 ((dev->pdev->subsystem_device == 0x016c) ||
2197 (dev->pdev->subsystem_device == 0x016d) ||
2198 (dev->pdev->subsystem_device == 0x016e) ||
2199 (dev->pdev->subsystem_device == 0x016f) ||
2200 (dev->pdev->subsystem_device == 0x0170) ||
2201 (dev->pdev->subsystem_device == 0x017d) ||
2202 (dev->pdev->subsystem_device == 0x017e) ||
2203 (dev->pdev->subsystem_device == 0x0183) ||
2204 (dev->pdev->subsystem_device == 0x018a) ||
2205 (dev->pdev->subsystem_device == 0x019a)))
2211 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2212 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2213 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2215 /* For CRT on DAC2, don't turn it on if BIOS didn't
2216 enable it, even it's detected.
2219 /* force it to crtc0 */
2220 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2221 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2222 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2224 /* set up the TV DAC */
2225 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2226 RADEON_TV_DAC_STD_MASK |
2227 RADEON_TV_DAC_RDACPD |
2228 RADEON_TV_DAC_GDACPD |
2229 RADEON_TV_DAC_BDACPD |
2230 RADEON_TV_DAC_BGADJ_MASK |
2231 RADEON_TV_DAC_DACADJ_MASK);
2232 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2233 RADEON_TV_DAC_NHOLD |
2234 RADEON_TV_DAC_STD_PS2 |
2237 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2238 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2239 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2242 /* switch PM block to ACPI mode */
2243 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2244 tmp &= ~RADEON_PM_MODE_SEL;
2245 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2252 static void r100_vram_get_type(struct radeon_device *rdev)
2256 rdev->mc.vram_is_ddr = false;
2257 if (rdev->flags & RADEON_IS_IGP)
2258 rdev->mc.vram_is_ddr = true;
2259 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2260 rdev->mc.vram_is_ddr = true;
2261 if ((rdev->family == CHIP_RV100) ||
2262 (rdev->family == CHIP_RS100) ||
2263 (rdev->family == CHIP_RS200)) {
2264 tmp = RREG32(RADEON_MEM_CNTL);
2265 if (tmp & RV100_HALF_MODE) {
2266 rdev->mc.vram_width = 32;
2268 rdev->mc.vram_width = 64;
2270 if (rdev->flags & RADEON_SINGLE_CRTC) {
2271 rdev->mc.vram_width /= 4;
2272 rdev->mc.vram_is_ddr = true;
2274 } else if (rdev->family <= CHIP_RV280) {
2275 tmp = RREG32(RADEON_MEM_CNTL);
2276 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2277 rdev->mc.vram_width = 128;
2279 rdev->mc.vram_width = 64;
2283 rdev->mc.vram_width = 128;
2287 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2292 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2294 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2295 * that is has the 2nd generation multifunction PCI interface
2297 if (rdev->family == CHIP_RV280 ||
2298 rdev->family >= CHIP_RV350) {
2299 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2300 ~RADEON_HDP_APER_CNTL);
2301 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2302 return aper_size * 2;
2305 /* Older cards have all sorts of funny issues to deal with. First
2306 * check if it's a multifunction card by reading the PCI config
2307 * header type... Limit those to one aperture size
2309 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2311 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2312 DRM_INFO("Limiting VRAM to one aperture\n");
2316 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2317 * have set it up. We don't write this as it's broken on some ASICs but
2318 * we expect the BIOS to have done the right thing (might be too optimistic...)
2320 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2321 return aper_size * 2;
2325 void r100_vram_init_sizes(struct radeon_device *rdev)
2327 u64 config_aper_size;
2329 /* work out accessible VRAM */
2330 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2331 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2332 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2333 /* FIXME we don't use the second aperture yet when we could use it */
2334 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2335 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2336 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2337 if (rdev->flags & RADEON_IS_IGP) {
2339 /* read NB_TOM to get the amount of ram stolen for the GPU */
2340 tom = RREG32(RADEON_NB_TOM);
2341 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2342 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2343 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2345 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2346 /* Some production boards of m6 will report 0
2349 if (rdev->mc.real_vram_size == 0) {
2350 rdev->mc.real_vram_size = 8192 * 1024;
2351 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2353 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2354 * Novell bug 204882 + along with lots of ubuntu ones
2356 if (config_aper_size > rdev->mc.real_vram_size)
2357 rdev->mc.mc_vram_size = config_aper_size;
2359 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2363 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2367 temp = RREG32(RADEON_CONFIG_CNTL);
2368 if (state == false) {
2374 WREG32(RADEON_CONFIG_CNTL, temp);
2377 void r100_mc_init(struct radeon_device *rdev)
2381 r100_vram_get_type(rdev);
2382 r100_vram_init_sizes(rdev);
2383 base = rdev->mc.aper_base;
2384 if (rdev->flags & RADEON_IS_IGP)
2385 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2386 radeon_vram_location(rdev, &rdev->mc, base);
2387 if (!(rdev->flags & RADEON_IS_AGP))
2388 radeon_gtt_location(rdev, &rdev->mc);
2389 radeon_update_bandwidth_info(rdev);
2394 * Indirect registers accessor
2396 void r100_pll_errata_after_index(struct radeon_device *rdev)
2398 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2401 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2402 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2405 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2407 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2408 * or the chip could hang on a subsequent access
2410 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2414 /* This function is required to workaround a hardware bug in some (all?)
2415 * revisions of the R300. This workaround should be called after every
2416 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2417 * may not be correct.
2419 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2422 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2423 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2424 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2425 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2426 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2430 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2434 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2435 r100_pll_errata_after_index(rdev);
2436 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2437 r100_pll_errata_after_data(rdev);
2441 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2443 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2444 r100_pll_errata_after_index(rdev);
2445 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2446 r100_pll_errata_after_data(rdev);
2449 void r100_set_safe_registers(struct radeon_device *rdev)
2451 if (ASIC_IS_RN50(rdev)) {
2452 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2453 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2454 } else if (rdev->family < CHIP_R200) {
2455 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2456 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2458 r200_set_safe_registers(rdev);
2465 #if defined(CONFIG_DEBUG_FS)
2466 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2468 struct drm_info_node *node = (struct drm_info_node *) m->private;
2469 struct drm_device *dev = node->minor->dev;
2470 struct radeon_device *rdev = dev->dev_private;
2471 uint32_t reg, value;
2474 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2475 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2476 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2477 for (i = 0; i < 64; i++) {
2478 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2479 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2480 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2481 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2482 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2487 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2489 struct drm_info_node *node = (struct drm_info_node *) m->private;
2490 struct drm_device *dev = node->minor->dev;
2491 struct radeon_device *rdev = dev->dev_private;
2493 unsigned count, i, j;
2495 radeon_ring_free_size(rdev);
2496 rdp = RREG32(RADEON_CP_RB_RPTR);
2497 wdp = RREG32(RADEON_CP_RB_WPTR);
2498 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2499 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2500 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2501 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2502 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2503 seq_printf(m, "%u dwords in ring\n", count);
2504 for (j = 0; j <= count; j++) {
2505 i = (rdp + j) & rdev->cp.ptr_mask;
2506 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2512 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2514 struct drm_info_node *node = (struct drm_info_node *) m->private;
2515 struct drm_device *dev = node->minor->dev;
2516 struct radeon_device *rdev = dev->dev_private;
2517 uint32_t csq_stat, csq2_stat, tmp;
2518 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2521 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2522 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2523 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2524 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2525 r_rptr = (csq_stat >> 0) & 0x3ff;
2526 r_wptr = (csq_stat >> 10) & 0x3ff;
2527 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2528 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2529 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2530 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2531 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2532 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2533 seq_printf(m, "Ring rptr %u\n", r_rptr);
2534 seq_printf(m, "Ring wptr %u\n", r_wptr);
2535 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2536 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2537 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2538 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2539 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2540 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2541 seq_printf(m, "Ring fifo:\n");
2542 for (i = 0; i < 256; i++) {
2543 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2544 tmp = RREG32(RADEON_CP_CSQ_DATA);
2545 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2547 seq_printf(m, "Indirect1 fifo:\n");
2548 for (i = 256; i <= 512; i++) {
2549 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2550 tmp = RREG32(RADEON_CP_CSQ_DATA);
2551 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2553 seq_printf(m, "Indirect2 fifo:\n");
2554 for (i = 640; i < ib1_wptr; i++) {
2555 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2556 tmp = RREG32(RADEON_CP_CSQ_DATA);
2557 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2562 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2564 struct drm_info_node *node = (struct drm_info_node *) m->private;
2565 struct drm_device *dev = node->minor->dev;
2566 struct radeon_device *rdev = dev->dev_private;
2569 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2570 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2571 tmp = RREG32(RADEON_MC_FB_LOCATION);
2572 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2573 tmp = RREG32(RADEON_BUS_CNTL);
2574 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2575 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2576 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2577 tmp = RREG32(RADEON_AGP_BASE);
2578 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2579 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2580 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2581 tmp = RREG32(0x01D0);
2582 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2583 tmp = RREG32(RADEON_AIC_LO_ADDR);
2584 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2585 tmp = RREG32(RADEON_AIC_HI_ADDR);
2586 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2587 tmp = RREG32(0x01E4);
2588 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2592 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2593 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2596 static struct drm_info_list r100_debugfs_cp_list[] = {
2597 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2598 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2601 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2602 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2606 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2608 #if defined(CONFIG_DEBUG_FS)
2609 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2615 int r100_debugfs_cp_init(struct radeon_device *rdev)
2617 #if defined(CONFIG_DEBUG_FS)
2618 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2624 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2626 #if defined(CONFIG_DEBUG_FS)
2627 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2633 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2634 uint32_t tiling_flags, uint32_t pitch,
2635 uint32_t offset, uint32_t obj_size)
2637 int surf_index = reg * 16;
2640 /* r100/r200 divide by 16 */
2641 if (rdev->family < CHIP_R300)
2646 if (rdev->family <= CHIP_RS200) {
2647 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2648 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2649 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2650 if (tiling_flags & RADEON_TILING_MACRO)
2651 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2652 } else if (rdev->family <= CHIP_RV280) {
2653 if (tiling_flags & (RADEON_TILING_MACRO))
2654 flags |= R200_SURF_TILE_COLOR_MACRO;
2655 if (tiling_flags & RADEON_TILING_MICRO)
2656 flags |= R200_SURF_TILE_COLOR_MICRO;
2658 if (tiling_flags & RADEON_TILING_MACRO)
2659 flags |= R300_SURF_TILE_MACRO;
2660 if (tiling_flags & RADEON_TILING_MICRO)
2661 flags |= R300_SURF_TILE_MICRO;
2664 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2665 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2666 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2667 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2669 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2670 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2671 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2672 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2676 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2678 int surf_index = reg * 16;
2679 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2682 void r100_bandwidth_update(struct radeon_device *rdev)
2684 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2685 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2686 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2687 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2688 fixed20_12 memtcas_ff[8] = {
2697 fixed20_12 memtcas_rs480_ff[8] = {
2707 fixed20_12 memtcas2_ff[8] = {
2717 fixed20_12 memtrbs[8] = {
2727 fixed20_12 memtrbs_r4xx[8] = {
2737 fixed20_12 min_mem_eff;
2738 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2739 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2740 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2741 disp_drain_rate2, read_return_rate;
2742 fixed20_12 time_disp1_drop_priority;
2744 int cur_size = 16; /* in octawords */
2745 int critical_point = 0, critical_point2;
2746 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2747 int stop_req, max_stop_req;
2748 struct drm_display_mode *mode1 = NULL;
2749 struct drm_display_mode *mode2 = NULL;
2750 uint32_t pixel_bytes1 = 0;
2751 uint32_t pixel_bytes2 = 0;
2753 radeon_update_display_priority(rdev);
2755 if (rdev->mode_info.crtcs[0]->base.enabled) {
2756 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2757 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2759 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2760 if (rdev->mode_info.crtcs[1]->base.enabled) {
2761 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2762 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2766 min_mem_eff.full = rfixed_const_8(0);
2768 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2769 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2770 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2771 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2772 /* check crtc enables */
2774 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2776 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2777 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2781 * determine is there is enough bw for current mode
2783 sclk_ff = rdev->pm.sclk;
2784 mclk_ff = rdev->pm.mclk;
2786 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2787 temp_ff.full = rfixed_const(temp);
2788 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2792 peak_disp_bw.full = 0;
2794 temp_ff.full = rfixed_const(1000);
2795 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2796 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2797 temp_ff.full = rfixed_const(pixel_bytes1);
2798 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2801 temp_ff.full = rfixed_const(1000);
2802 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2803 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2804 temp_ff.full = rfixed_const(pixel_bytes2);
2805 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2808 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2809 if (peak_disp_bw.full >= mem_bw.full) {
2810 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2811 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2814 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2815 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2816 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2817 mem_trcd = ((temp >> 2) & 0x3) + 1;
2818 mem_trp = ((temp & 0x3)) + 1;
2819 mem_tras = ((temp & 0x70) >> 4) + 1;
2820 } else if (rdev->family == CHIP_R300 ||
2821 rdev->family == CHIP_R350) { /* r300, r350 */
2822 mem_trcd = (temp & 0x7) + 1;
2823 mem_trp = ((temp >> 8) & 0x7) + 1;
2824 mem_tras = ((temp >> 11) & 0xf) + 4;
2825 } else if (rdev->family == CHIP_RV350 ||
2826 rdev->family <= CHIP_RV380) {
2828 mem_trcd = (temp & 0x7) + 3;
2829 mem_trp = ((temp >> 8) & 0x7) + 3;
2830 mem_tras = ((temp >> 11) & 0xf) + 6;
2831 } else if (rdev->family == CHIP_R420 ||
2832 rdev->family == CHIP_R423 ||
2833 rdev->family == CHIP_RV410) {
2835 mem_trcd = (temp & 0xf) + 3;
2838 mem_trp = ((temp >> 8) & 0xf) + 3;
2841 mem_tras = ((temp >> 12) & 0x1f) + 6;
2844 } else { /* RV200, R200 */
2845 mem_trcd = (temp & 0x7) + 1;
2846 mem_trp = ((temp >> 8) & 0x7) + 1;
2847 mem_tras = ((temp >> 12) & 0xf) + 4;
2850 trcd_ff.full = rfixed_const(mem_trcd);
2851 trp_ff.full = rfixed_const(mem_trp);
2852 tras_ff.full = rfixed_const(mem_tras);
2854 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2855 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2856 data = (temp & (7 << 20)) >> 20;
2857 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2858 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2859 tcas_ff = memtcas_rs480_ff[data];
2861 tcas_ff = memtcas_ff[data];
2863 tcas_ff = memtcas2_ff[data];
2865 if (rdev->family == CHIP_RS400 ||
2866 rdev->family == CHIP_RS480) {
2867 /* extra cas latency stored in bits 23-25 0-4 clocks */
2868 data = (temp >> 23) & 0x7;
2870 tcas_ff.full += rfixed_const(data);
2873 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2874 /* on the R300, Tcas is included in Trbs.
2876 temp = RREG32(RADEON_MEM_CNTL);
2877 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2879 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2880 temp = RREG32(R300_MC_IND_INDEX);
2881 temp &= ~R300_MC_IND_ADDR_MASK;
2882 temp |= R300_MC_READ_CNTL_CD_mcind;
2883 WREG32(R300_MC_IND_INDEX, temp);
2884 temp = RREG32(R300_MC_IND_DATA);
2885 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2887 temp = RREG32(R300_MC_READ_CNTL_AB);
2888 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2891 temp = RREG32(R300_MC_READ_CNTL_AB);
2892 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2894 if (rdev->family == CHIP_RV410 ||
2895 rdev->family == CHIP_R420 ||
2896 rdev->family == CHIP_R423)
2897 trbs_ff = memtrbs_r4xx[data];
2899 trbs_ff = memtrbs[data];
2900 tcas_ff.full += trbs_ff.full;
2903 sclk_eff_ff.full = sclk_ff.full;
2905 if (rdev->flags & RADEON_IS_AGP) {
2906 fixed20_12 agpmode_ff;
2907 agpmode_ff.full = rfixed_const(radeon_agpmode);
2908 temp_ff.full = rfixed_const_666(16);
2909 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2911 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2913 if (ASIC_IS_R300(rdev)) {
2914 sclk_delay_ff.full = rfixed_const(250);
2916 if ((rdev->family == CHIP_RV100) ||
2917 rdev->flags & RADEON_IS_IGP) {
2918 if (rdev->mc.vram_is_ddr)
2919 sclk_delay_ff.full = rfixed_const(41);
2921 sclk_delay_ff.full = rfixed_const(33);
2923 if (rdev->mc.vram_width == 128)
2924 sclk_delay_ff.full = rfixed_const(57);
2926 sclk_delay_ff.full = rfixed_const(41);
2930 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2932 if (rdev->mc.vram_is_ddr) {
2933 if (rdev->mc.vram_width == 32) {
2934 k1.full = rfixed_const(40);
2937 k1.full = rfixed_const(20);
2941 k1.full = rfixed_const(40);
2945 temp_ff.full = rfixed_const(2);
2946 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2947 temp_ff.full = rfixed_const(c);
2948 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2949 temp_ff.full = rfixed_const(4);
2950 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2951 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2952 mc_latency_mclk.full += k1.full;
2954 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2955 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2958 HW cursor time assuming worst case of full size colour cursor.
2960 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2961 temp_ff.full += trcd_ff.full;
2962 if (temp_ff.full < tras_ff.full)
2963 temp_ff.full = tras_ff.full;
2964 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2966 temp_ff.full = rfixed_const(cur_size);
2967 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2969 Find the total latency for the display data.
2971 disp_latency_overhead.full = rfixed_const(8);
2972 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2973 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2974 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2976 if (mc_latency_mclk.full > mc_latency_sclk.full)
2977 disp_latency.full = mc_latency_mclk.full;
2979 disp_latency.full = mc_latency_sclk.full;
2981 /* setup Max GRPH_STOP_REQ default value */
2982 if (ASIC_IS_RV100(rdev))
2983 max_stop_req = 0x5c;
2985 max_stop_req = 0x7c;
2989 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2990 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2992 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2994 if (stop_req > max_stop_req)
2995 stop_req = max_stop_req;
2998 Find the drain rate of the display buffer.
3000 temp_ff.full = rfixed_const((16/pixel_bytes1));
3001 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
3004 Find the critical point of the display buffer.
3006 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
3007 crit_point_ff.full += rfixed_const_half(0);
3009 critical_point = rfixed_trunc(crit_point_ff);
3011 if (rdev->disp_priority == 2) {
3016 The critical point should never be above max_stop_req-4. Setting
3017 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3019 if (max_stop_req - critical_point < 4)
3022 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3023 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3024 critical_point = 0x10;
3027 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3028 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3029 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3030 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3031 if ((rdev->family == CHIP_R350) &&
3032 (stop_req > 0x15)) {
3035 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3036 temp |= RADEON_GRPH_BUFFER_SIZE;
3037 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3038 RADEON_GRPH_CRITICAL_AT_SOF |
3039 RADEON_GRPH_STOP_CNTL);
3041 Write the result into the register.
3043 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3044 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3047 if ((rdev->family == CHIP_RS400) ||
3048 (rdev->family == CHIP_RS480)) {
3049 /* attempt to program RS400 disp regs correctly ??? */
3050 temp = RREG32(RS400_DISP1_REG_CNTL);
3051 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3052 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3053 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3054 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3055 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3056 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3057 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3058 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3059 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3060 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3061 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3065 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3066 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3067 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3072 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3074 if (stop_req > max_stop_req)
3075 stop_req = max_stop_req;
3078 Find the drain rate of the display buffer.
3080 temp_ff.full = rfixed_const((16/pixel_bytes2));
3081 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
3083 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3084 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3085 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3086 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3087 if ((rdev->family == CHIP_R350) &&
3088 (stop_req > 0x15)) {
3091 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3092 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3093 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3094 RADEON_GRPH_CRITICAL_AT_SOF |
3095 RADEON_GRPH_STOP_CNTL);
3097 if ((rdev->family == CHIP_RS100) ||
3098 (rdev->family == CHIP_RS200))
3099 critical_point2 = 0;
3101 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3102 temp_ff.full = rfixed_const(temp);
3103 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
3104 if (sclk_ff.full < temp_ff.full)
3105 temp_ff.full = sclk_ff.full;
3107 read_return_rate.full = temp_ff.full;
3110 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3111 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
3113 time_disp1_drop_priority.full = 0;
3115 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3116 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
3117 crit_point_ff.full += rfixed_const_half(0);
3119 critical_point2 = rfixed_trunc(crit_point_ff);
3121 if (rdev->disp_priority == 2) {
3122 critical_point2 = 0;
3125 if (max_stop_req - critical_point2 < 4)
3126 critical_point2 = 0;
3130 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3131 /* some R300 cards have problem with this set to 0 */
3132 critical_point2 = 0x10;
3135 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3136 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3138 if ((rdev->family == CHIP_RS400) ||
3139 (rdev->family == CHIP_RS480)) {
3141 /* attempt to program RS400 disp2 regs correctly ??? */
3142 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3143 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3144 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3145 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3146 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3147 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3148 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3149 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3150 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3151 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3152 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3153 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3155 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3156 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3157 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3158 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3161 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3162 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3166 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3168 DRM_ERROR("pitch %d\n", t->pitch);
3169 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3170 DRM_ERROR("width %d\n", t->width);
3171 DRM_ERROR("width_11 %d\n", t->width_11);
3172 DRM_ERROR("height %d\n", t->height);
3173 DRM_ERROR("height_11 %d\n", t->height_11);
3174 DRM_ERROR("num levels %d\n", t->num_levels);
3175 DRM_ERROR("depth %d\n", t->txdepth);
3176 DRM_ERROR("bpp %d\n", t->cpp);
3177 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3178 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3179 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3180 DRM_ERROR("compress format %d\n", t->compress_format);
3183 static int r100_cs_track_cube(struct radeon_device *rdev,
3184 struct r100_cs_track *track, unsigned idx)
3186 unsigned face, w, h;
3187 struct radeon_bo *cube_robj;
3190 for (face = 0; face < 5; face++) {
3191 cube_robj = track->textures[idx].cube_info[face].robj;
3192 w = track->textures[idx].cube_info[face].width;
3193 h = track->textures[idx].cube_info[face].height;
3196 size *= track->textures[idx].cpp;
3198 size += track->textures[idx].cube_info[face].offset;
3200 if (size > radeon_bo_size(cube_robj)) {
3201 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3202 size, radeon_bo_size(cube_robj));
3203 r100_cs_track_texture_print(&track->textures[idx]);
3210 static int r100_track_compress_size(int compress_format, int w, int h)
3212 int block_width, block_height, block_bytes;
3213 int wblocks, hblocks;
3220 switch (compress_format) {
3221 case R100_TRACK_COMP_DXT1:
3226 case R100_TRACK_COMP_DXT35:
3232 hblocks = (h + block_height - 1) / block_height;
3233 wblocks = (w + block_width - 1) / block_width;
3234 if (wblocks < min_wblocks)
3235 wblocks = min_wblocks;
3236 sz = wblocks * hblocks * block_bytes;
3240 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3241 struct r100_cs_track *track)
3243 struct radeon_bo *robj;
3245 unsigned u, i, w, h, d;
3248 for (u = 0; u < track->num_texture; u++) {
3249 if (!track->textures[u].enabled)
3251 robj = track->textures[u].robj;
3253 DRM_ERROR("No texture bound to unit %u\n", u);
3257 for (i = 0; i <= track->textures[u].num_levels; i++) {
3258 if (track->textures[u].use_pitch) {
3259 if (rdev->family < CHIP_R300)
3260 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3262 w = track->textures[u].pitch / (1 << i);
3264 w = track->textures[u].width;
3265 if (rdev->family >= CHIP_RV515)
3266 w |= track->textures[u].width_11;
3268 if (track->textures[u].roundup_w)
3269 w = roundup_pow_of_two(w);
3271 h = track->textures[u].height;
3272 if (rdev->family >= CHIP_RV515)
3273 h |= track->textures[u].height_11;
3275 if (track->textures[u].roundup_h)
3276 h = roundup_pow_of_two(h);
3277 if (track->textures[u].tex_coord_type == 1) {
3278 d = (1 << track->textures[u].txdepth) / (1 << i);
3284 if (track->textures[u].compress_format) {
3286 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3287 /* compressed textures are block based */
3291 size *= track->textures[u].cpp;
3293 switch (track->textures[u].tex_coord_type) {
3298 if (track->separate_cube) {
3299 ret = r100_cs_track_cube(rdev, track, u);
3306 DRM_ERROR("Invalid texture coordinate type %u for unit "
3307 "%u\n", track->textures[u].tex_coord_type, u);
3310 if (size > radeon_bo_size(robj)) {
3311 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3312 "%lu\n", u, size, radeon_bo_size(robj));
3313 r100_cs_track_texture_print(&track->textures[u]);
3320 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3327 for (i = 0; i < track->num_cb; i++) {
3328 if (track->cb[i].robj == NULL) {
3329 if (!(track->fastfill || track->color_channel_mask ||
3330 track->blend_read_enable)) {
3333 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3336 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3337 size += track->cb[i].offset;
3338 if (size > radeon_bo_size(track->cb[i].robj)) {
3339 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3340 "(need %lu have %lu) !\n", i, size,
3341 radeon_bo_size(track->cb[i].robj));
3342 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3343 i, track->cb[i].pitch, track->cb[i].cpp,
3344 track->cb[i].offset, track->maxy);
3348 if (track->z_enabled) {
3349 if (track->zb.robj == NULL) {
3350 DRM_ERROR("[drm] No buffer for z buffer !\n");
3353 size = track->zb.pitch * track->zb.cpp * track->maxy;
3354 size += track->zb.offset;
3355 if (size > radeon_bo_size(track->zb.robj)) {
3356 DRM_ERROR("[drm] Buffer too small for z buffer "
3357 "(need %lu have %lu) !\n", size,
3358 radeon_bo_size(track->zb.robj));
3359 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3360 track->zb.pitch, track->zb.cpp,
3361 track->zb.offset, track->maxy);
3365 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3366 if (track->vap_vf_cntl & (1 << 14)) {
3367 nverts = track->vap_alt_nverts;
3369 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3371 switch (prim_walk) {
3373 for (i = 0; i < track->num_arrays; i++) {
3374 size = track->arrays[i].esize * track->max_indx * 4;
3375 if (track->arrays[i].robj == NULL) {
3376 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3377 "bound\n", prim_walk, i);
3380 if (size > radeon_bo_size(track->arrays[i].robj)) {
3381 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3382 "need %lu dwords have %lu dwords\n",
3383 prim_walk, i, size >> 2,
3384 radeon_bo_size(track->arrays[i].robj)
3386 DRM_ERROR("Max indices %u\n", track->max_indx);
3392 for (i = 0; i < track->num_arrays; i++) {
3393 size = track->arrays[i].esize * (nverts - 1) * 4;
3394 if (track->arrays[i].robj == NULL) {
3395 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3396 "bound\n", prim_walk, i);
3399 if (size > radeon_bo_size(track->arrays[i].robj)) {
3400 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3401 "need %lu dwords have %lu dwords\n",
3402 prim_walk, i, size >> 2,
3403 radeon_bo_size(track->arrays[i].robj)
3410 size = track->vtx_size * nverts;
3411 if (size != track->immd_dwords) {
3412 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3413 track->immd_dwords, size);
3414 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3415 nverts, track->vtx_size);
3420 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3424 return r100_cs_track_texture_check(rdev, track);
3427 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3431 if (rdev->family < CHIP_R300) {
3433 if (rdev->family <= CHIP_RS200)
3434 track->num_texture = 3;
3436 track->num_texture = 6;
3438 track->separate_cube = 1;
3441 track->num_texture = 16;
3443 track->separate_cube = 0;
3446 for (i = 0; i < track->num_cb; i++) {
3447 track->cb[i].robj = NULL;
3448 track->cb[i].pitch = 8192;
3449 track->cb[i].cpp = 16;
3450 track->cb[i].offset = 0;
3452 track->z_enabled = true;
3453 track->zb.robj = NULL;
3454 track->zb.pitch = 8192;
3456 track->zb.offset = 0;
3457 track->vtx_size = 0x7F;
3458 track->immd_dwords = 0xFFFFFFFFUL;
3459 track->num_arrays = 11;
3460 track->max_indx = 0x00FFFFFFUL;
3461 for (i = 0; i < track->num_arrays; i++) {
3462 track->arrays[i].robj = NULL;
3463 track->arrays[i].esize = 0x7F;
3465 for (i = 0; i < track->num_texture; i++) {
3466 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3467 track->textures[i].pitch = 16536;
3468 track->textures[i].width = 16536;
3469 track->textures[i].height = 16536;
3470 track->textures[i].width_11 = 1 << 11;
3471 track->textures[i].height_11 = 1 << 11;
3472 track->textures[i].num_levels = 12;
3473 if (rdev->family <= CHIP_RS200) {
3474 track->textures[i].tex_coord_type = 0;
3475 track->textures[i].txdepth = 0;
3477 track->textures[i].txdepth = 16;
3478 track->textures[i].tex_coord_type = 1;
3480 track->textures[i].cpp = 64;
3481 track->textures[i].robj = NULL;
3482 /* CS IB emission code makes sure texture unit are disabled */
3483 track->textures[i].enabled = false;
3484 track->textures[i].roundup_w = true;
3485 track->textures[i].roundup_h = true;
3486 if (track->separate_cube)
3487 for (face = 0; face < 5; face++) {
3488 track->textures[i].cube_info[face].robj = NULL;
3489 track->textures[i].cube_info[face].width = 16536;
3490 track->textures[i].cube_info[face].height = 16536;
3491 track->textures[i].cube_info[face].offset = 0;
3496 int r100_ring_test(struct radeon_device *rdev)
3503 r = radeon_scratch_get(rdev, &scratch);
3505 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3508 WREG32(scratch, 0xCAFEDEAD);
3509 r = radeon_ring_lock(rdev, 2);
3511 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3512 radeon_scratch_free(rdev, scratch);
3515 radeon_ring_write(rdev, PACKET0(scratch, 0));
3516 radeon_ring_write(rdev, 0xDEADBEEF);
3517 radeon_ring_unlock_commit(rdev);
3518 for (i = 0; i < rdev->usec_timeout; i++) {
3519 tmp = RREG32(scratch);
3520 if (tmp == 0xDEADBEEF) {
3525 if (i < rdev->usec_timeout) {
3526 DRM_INFO("ring test succeeded in %d usecs\n", i);
3528 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3532 radeon_scratch_free(rdev, scratch);
3536 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3538 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3539 radeon_ring_write(rdev, ib->gpu_addr);
3540 radeon_ring_write(rdev, ib->length_dw);
3543 int r100_ib_test(struct radeon_device *rdev)
3545 struct radeon_ib *ib;
3551 r = radeon_scratch_get(rdev, &scratch);
3553 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3556 WREG32(scratch, 0xCAFEDEAD);
3557 r = radeon_ib_get(rdev, &ib);
3561 ib->ptr[0] = PACKET0(scratch, 0);
3562 ib->ptr[1] = 0xDEADBEEF;
3563 ib->ptr[2] = PACKET2(0);
3564 ib->ptr[3] = PACKET2(0);
3565 ib->ptr[4] = PACKET2(0);
3566 ib->ptr[5] = PACKET2(0);
3567 ib->ptr[6] = PACKET2(0);
3568 ib->ptr[7] = PACKET2(0);
3570 r = radeon_ib_schedule(rdev, ib);
3572 radeon_scratch_free(rdev, scratch);
3573 radeon_ib_free(rdev, &ib);
3576 r = radeon_fence_wait(ib->fence, false);
3580 for (i = 0; i < rdev->usec_timeout; i++) {
3581 tmp = RREG32(scratch);
3582 if (tmp == 0xDEADBEEF) {
3587 if (i < rdev->usec_timeout) {
3588 DRM_INFO("ib test succeeded in %u usecs\n", i);
3590 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3594 radeon_scratch_free(rdev, scratch);
3595 radeon_ib_free(rdev, &ib);
3599 void r100_ib_fini(struct radeon_device *rdev)
3601 radeon_ib_pool_fini(rdev);
3604 int r100_ib_init(struct radeon_device *rdev)
3608 r = radeon_ib_pool_init(rdev);
3610 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3614 r = r100_ib_test(rdev);
3616 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3623 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3625 /* Shutdown CP we shouldn't need to do that but better be safe than
3628 rdev->cp.ready = false;
3629 WREG32(R_000740_CP_CSQ_CNTL, 0);
3631 /* Save few CRTC registers */
3632 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3633 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3634 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3635 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3636 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3637 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3638 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3641 /* Disable VGA aperture access */
3642 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3643 /* Disable cursor, overlay, crtc */
3644 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3645 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3646 S_000054_CRTC_DISPLAY_DIS(1));
3647 WREG32(R_000050_CRTC_GEN_CNTL,
3648 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3649 S_000050_CRTC_DISP_REQ_EN_B(1));
3650 WREG32(R_000420_OV0_SCALE_CNTL,
3651 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3652 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3653 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3654 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3655 S_000360_CUR2_LOCK(1));
3656 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3657 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3658 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3659 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3660 WREG32(R_000360_CUR2_OFFSET,
3661 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3665 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3667 /* Update base address for crtc */
3668 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3669 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3670 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3672 /* Restore CRTC registers */
3673 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3674 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3675 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3676 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3677 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3681 void r100_vga_render_disable(struct radeon_device *rdev)
3685 tmp = RREG8(R_0003C2_GENMO_WT);
3686 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3689 static void r100_debugfs(struct radeon_device *rdev)
3693 r = r100_debugfs_mc_info_init(rdev);
3695 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3698 static void r100_mc_program(struct radeon_device *rdev)
3700 struct r100_mc_save save;
3702 /* Stops all mc clients */
3703 r100_mc_stop(rdev, &save);
3704 if (rdev->flags & RADEON_IS_AGP) {
3705 WREG32(R_00014C_MC_AGP_LOCATION,
3706 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3707 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3708 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3709 if (rdev->family > CHIP_RV200)
3710 WREG32(R_00015C_AGP_BASE_2,
3711 upper_32_bits(rdev->mc.agp_base) & 0xff);
3713 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3714 WREG32(R_000170_AGP_BASE, 0);
3715 if (rdev->family > CHIP_RV200)
3716 WREG32(R_00015C_AGP_BASE_2, 0);
3718 /* Wait for mc idle */
3719 if (r100_mc_wait_for_idle(rdev))
3720 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3721 /* Program MC, should be a 32bits limited address space */
3722 WREG32(R_000148_MC_FB_LOCATION,
3723 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3724 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3725 r100_mc_resume(rdev, &save);
3728 void r100_clock_startup(struct radeon_device *rdev)
3732 if (radeon_dynclks != -1 && radeon_dynclks)
3733 radeon_legacy_set_clock_gating(rdev, 1);
3734 /* We need to force on some of the block */
3735 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3736 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3737 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3738 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3739 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3742 static int r100_startup(struct radeon_device *rdev)
3746 /* set common regs */
3747 r100_set_common_regs(rdev);
3749 r100_mc_program(rdev);
3751 r100_clock_startup(rdev);
3752 /* Initialize GPU configuration (# pipes, ...) */
3753 // r100_gpu_init(rdev);
3754 /* Initialize GART (initialize after TTM so we can allocate
3755 * memory through TTM but finalize after TTM) */
3756 r100_enable_bm(rdev);
3757 if (rdev->flags & RADEON_IS_PCI) {
3758 r = r100_pci_gart_enable(rdev);
3764 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3765 /* 1M ring buffer */
3766 r = r100_cp_init(rdev, 1024 * 1024);
3768 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3771 r = r100_wb_init(rdev);
3773 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3774 r = r100_ib_init(rdev);
3776 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3782 int r100_resume(struct radeon_device *rdev)
3784 /* Make sur GART are not working */
3785 if (rdev->flags & RADEON_IS_PCI)
3786 r100_pci_gart_disable(rdev);
3787 /* Resume clock before doing reset */
3788 r100_clock_startup(rdev);
3789 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3790 if (radeon_asic_reset(rdev)) {
3791 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3792 RREG32(R_000E40_RBBM_STATUS),
3793 RREG32(R_0007C0_CP_STAT));
3796 radeon_combios_asic_init(rdev->ddev);
3797 /* Resume clock after posting */
3798 r100_clock_startup(rdev);
3799 /* Initialize surface registers */
3800 radeon_surface_init(rdev);
3801 return r100_startup(rdev);
3804 int r100_suspend(struct radeon_device *rdev)
3806 r100_cp_disable(rdev);
3807 r100_wb_disable(rdev);
3808 r100_irq_disable(rdev);
3809 if (rdev->flags & RADEON_IS_PCI)
3810 r100_pci_gart_disable(rdev);
3814 void r100_fini(struct radeon_device *rdev)
3816 radeon_pm_fini(rdev);
3820 radeon_gem_fini(rdev);
3821 if (rdev->flags & RADEON_IS_PCI)
3822 r100_pci_gart_fini(rdev);
3823 radeon_agp_fini(rdev);
3824 radeon_irq_kms_fini(rdev);
3825 radeon_fence_driver_fini(rdev);
3826 radeon_bo_fini(rdev);
3827 radeon_atombios_fini(rdev);
3832 int r100_init(struct radeon_device *rdev)
3836 /* Register debugfs file specific to this group of asics */
3839 r100_vga_render_disable(rdev);
3840 /* Initialize scratch registers */
3841 radeon_scratch_init(rdev);
3842 /* Initialize surface registers */
3843 radeon_surface_init(rdev);
3844 /* TODO: disable VGA need to use VGA request */
3846 if (!radeon_get_bios(rdev)) {
3847 if (ASIC_IS_AVIVO(rdev))
3850 if (rdev->is_atom_bios) {
3851 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3854 r = radeon_combios_init(rdev);
3858 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3859 if (radeon_asic_reset(rdev)) {
3861 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3862 RREG32(R_000E40_RBBM_STATUS),
3863 RREG32(R_0007C0_CP_STAT));
3865 /* check if cards are posted or not */
3866 if (radeon_boot_test_post_card(rdev) == false)
3868 /* Set asic errata */
3870 /* Initialize clocks */
3871 radeon_get_clock_info(rdev->ddev);
3872 /* Initialize power management */
3873 radeon_pm_init(rdev);
3874 /* initialize AGP */
3875 if (rdev->flags & RADEON_IS_AGP) {
3876 r = radeon_agp_init(rdev);
3878 radeon_agp_disable(rdev);
3881 /* initialize VRAM */
3884 r = radeon_fence_driver_init(rdev);
3887 r = radeon_irq_kms_init(rdev);
3890 /* Memory manager */
3891 r = radeon_bo_init(rdev);
3894 if (rdev->flags & RADEON_IS_PCI) {
3895 r = r100_pci_gart_init(rdev);
3899 r100_set_safe_registers(rdev);
3900 rdev->accel_working = true;
3901 r = r100_startup(rdev);
3903 /* Somethings want wront with the accel init stop accel */
3904 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3908 radeon_irq_kms_fini(rdev);
3909 if (rdev->flags & RADEON_IS_PCI)
3910 r100_pci_gart_fini(rdev);
3911 rdev->accel_working = false;