SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "r100d.h"
  35 #include "rs100d.h"
  36 #include "rv200d.h"
  37 #include "rv250d.h"
  38
  39 #include <linux/firmware.h>
  40 #include <linux/platform_device.h>
  41
  42 #include "r100_reg_safe.h"
  43 #include "rn50_reg_safe.h"
  44
  45 /* Firmware Names */
  46 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  47 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  48 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  49 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  50 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  51 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  52 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  53
  54 MODULE_FIRMWARE(FIRMWARE_R100);
  55 MODULE_FIRMWARE(FIRMWARE_R200);
  56 MODULE_FIRMWARE(FIRMWARE_R300);
  57 MODULE_FIRMWARE(FIRMWARE_R420);
  58 MODULE_FIRMWARE(FIRMWARE_RS690);
  59 MODULE_FIRMWARE(FIRMWARE_RS600);
  60 MODULE_FIRMWARE(FIRMWARE_R520);
  61
  62 #include "r100_track.h"
  63
  64 /* This files gather functions specifics to:
  65  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  66  */
  67
  68 /* hpd for digital panel detect/disconnect */
  69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  70 {
  71         bool connected = false;
  72
  73         switch (hpd) {
  74         case RADEON_HPD_1:
  75                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  76                         connected = true;
  77                 break;
  78         case RADEON_HPD_2:
  79                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  80                         connected = true;
  81                 break;
  82         default:
  83                 break;
  84         }
  85         return connected;
  86 }
  87
  88 void r100_hpd_set_polarity(struct radeon_device *rdev,
  89                            enum radeon_hpd_id hpd)
  90 {
  91         u32 tmp;
  92         bool connected = r100_hpd_sense(rdev, hpd);
  93
  94         switch (hpd) {
  95         case RADEON_HPD_1:
  96                 tmp = RREG32(RADEON_FP_GEN_CNTL);
  97                 if (connected)
  98                         tmp &= ~RADEON_FP_DETECT_INT_POL;
  99                 else
 100                         tmp |= RADEON_FP_DETECT_INT_POL;
 101                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 102                 break;
 103         case RADEON_HPD_2:
 104                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 105                 if (connected)
 106                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 107                 else
 108                         tmp |= RADEON_FP2_DETECT_INT_POL;
 109                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 110                 break;
 111         default:
 112                 break;
 113         }
 114 }
 115
 116 void r100_hpd_init(struct radeon_device *rdev)
 117 {
 118         struct drm_device *dev = rdev->ddev;
 119         struct drm_connector *connector;
 120
 121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 122                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 123                 switch (radeon_connector->hpd.hpd) {
 124                 case RADEON_HPD_1:
 125                         rdev->irq.hpd[0] = true;
 126                         break;
 127                 case RADEON_HPD_2:
 128                         rdev->irq.hpd[1] = true;
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134         r100_irq_set(rdev);
 135 }
 136
 137 void r100_hpd_fini(struct radeon_device *rdev)
 138 {
 139         struct drm_device *dev = rdev->ddev;
 140         struct drm_connector *connector;
 141
 142         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 143                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 144                 switch (radeon_connector->hpd.hpd) {
 145                 case RADEON_HPD_1:
 146                         rdev->irq.hpd[0] = false;
 147                         break;
 148                 case RADEON_HPD_2:
 149                         rdev->irq.hpd[1] = false;
 150                         break;
 151                 default:
 152                         break;
 153                 }
 154         }
 155 }
 156
 157 /*
 158  * PCI GART
 159  */
 160 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 161 {
 162         /* TODO: can we do somethings here ? */
 163         /* It seems hw only cache one entry so we should discard this
 164          * entry otherwise if first GPU GART read hit this entry it
 165          * could end up in wrong address. */
 166 }
 167
 168 int r100_pci_gart_init(struct radeon_device *rdev)
 169 {
 170         int r;
 171
 172         if (rdev->gart.table.ram.ptr) {
 173                 WARN(1, "R100 PCI GART already initialized.\n");
 174                 return 0;
 175         }
 176         /* Initialize common gart structure */
 177         r = radeon_gart_init(rdev);
 178         if (r)
 179                 return r;
 180         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 181         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 182         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 183         return radeon_gart_table_ram_alloc(rdev);
 184 }
 185
 186 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 187 void r100_enable_bm(struct radeon_device *rdev)
 188 {
 189         uint32_t tmp;
 190         /* Enable bus mastering */
 191         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 192         WREG32(RADEON_BUS_CNTL, tmp);
 193 }
 194
 195 int r100_pci_gart_enable(struct radeon_device *rdev)
 196 {
 197         uint32_t tmp;
 198
 199         /* discard memory request outside of configured range */
 200         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 201         WREG32(RADEON_AIC_CNTL, tmp);
 202         /* set address range for PCI address translate */
 203         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
 204         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 205         WREG32(RADEON_AIC_HI_ADDR, tmp);
 206         /* set PCI GART page-table base address */
 207         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 208         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 209         WREG32(RADEON_AIC_CNTL, tmp);
 210         r100_pci_gart_tlb_flush(rdev);
 211         rdev->gart.ready = true;
 212         return 0;
 213 }
 214
 215 void r100_pci_gart_disable(struct radeon_device *rdev)
 216 {
 217         uint32_t tmp;
 218
 219         /* discard memory request outside of configured range */
 220         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 221         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 222         WREG32(RADEON_AIC_LO_ADDR, 0);
 223         WREG32(RADEON_AIC_HI_ADDR, 0);
 224 }
 225
 226 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 227 {
 228         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 229                 return -EINVAL;
 230         }
 231         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 232         return 0;
 233 }
 234
 235 void r100_pci_gart_fini(struct radeon_device *rdev)
 236 {
 237         r100_pci_gart_disable(rdev);
 238         radeon_gart_table_ram_free(rdev);
 239         radeon_gart_fini(rdev);
 240 }
 241
 242 int r100_irq_set(struct radeon_device *rdev)
 243 {
 244         uint32_t tmp = 0;
 245
 246         if (rdev->irq.sw_int) {
 247                 tmp |= RADEON_SW_INT_ENABLE;
 248         }
 249         if (rdev->irq.crtc_vblank_int[0]) {
 250                 tmp |= RADEON_CRTC_VBLANK_MASK;
 251         }
 252         if (rdev->irq.crtc_vblank_int[1]) {
 253                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 254         }
 255         if (rdev->irq.hpd[0]) {
 256                 tmp |= RADEON_FP_DETECT_MASK;
 257         }
 258         if (rdev->irq.hpd[1]) {
 259                 tmp |= RADEON_FP2_DETECT_MASK;
 260         }
 261         WREG32(RADEON_GEN_INT_CNTL, tmp);
 262         return 0;
 263 }
 264
 265 void r100_irq_disable(struct radeon_device *rdev)
 266 {
 267         u32 tmp;
 268
 269         WREG32(R_000040_GEN_INT_CNTL, 0);
 270         /* Wait and acknowledge irq */
 271         mdelay(1);
 272         tmp = RREG32(R_000044_GEN_INT_STATUS);
 273         WREG32(R_000044_GEN_INT_STATUS, tmp);
 274 }
 275
 276 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 277 {
 278         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 279         uint32_t irq_mask = RADEON_SW_INT_TEST |
 280                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 281                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 282
 283         if (irqs) {
 284                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 285         }
 286         return irqs & irq_mask;
 287 }
 288
 289 int r100_irq_process(struct radeon_device *rdev)
 290 {
 291         uint32_t status, msi_rearm;
 292
 293         status = r100_irq_ack(rdev);
 294         if (!status) {
 295                 return IRQ_NONE;
 296         }
 297         if (rdev->shutdown) {
 298                 return IRQ_NONE;
 299         }
 300         while (status) {
 301                 /* SW interrupt */
 302                 if (status & RADEON_SW_INT_TEST) {
 303                         radeon_fence_process(rdev);
 304                 }
 305                 /* Vertical blank interrupts */
 306                 if (status & RADEON_CRTC_VBLANK_STAT) {
 307                         drm_handle_vblank(rdev->ddev, 0);
 308                 }
 309                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 310                         drm_handle_vblank(rdev->ddev, 1);
 311                 }
 312                 if (status & RADEON_FP_DETECT_STAT) {
 313                         DRM_INFO("HPD1\n");
 314                 }
 315                 if (status & RADEON_FP2_DETECT_STAT) {
 316                         DRM_INFO("HPD2\n");
 317                 }
 318                 status = r100_irq_ack(rdev);
 319         }
 320         if (rdev->msi_enabled) {
 321                 switch (rdev->family) {
 322                 case CHIP_RS400:
 323                 case CHIP_RS480:
 324                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 325                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 326                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 327                         break;
 328                 default:
 329                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 330                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 331                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 332                         break;
 333                 }
 334         }
 335         return IRQ_HANDLED;
 336 }
 337
 338 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 339 {
 340         if (crtc == 0)
 341                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 342         else
 343                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 344 }
 345
 346 void r100_fence_ring_emit(struct radeon_device *rdev,
 347                           struct radeon_fence *fence)
 348 {
 349         /* Who ever call radeon_fence_emit should call ring_lock and ask
 350          * for enough space (today caller are ib schedule and buffer move) */
 351         /* Wait until IDLE & CLEAN */
 352         radeon_ring_write(rdev, PACKET0(0x1720, 0));
 353         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
 354         /* Emit fence sequence & fire IRQ */
 355         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 356         radeon_ring_write(rdev, fence->seq);
 357         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 358         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 359 }
 360
 361 int r100_wb_init(struct radeon_device *rdev)
 362 {
 363         int r;
 364
 365         if (rdev->wb.wb_obj == NULL) {
 366                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 367                                         RADEON_GEM_DOMAIN_GTT,
 368                                         &rdev->wb.wb_obj);
 369                 if (r) {
 370                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 371                         return r;
 372                 }
 373                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 374                 if (unlikely(r != 0))
 375                         return r;
 376                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 377                                         &rdev->wb.gpu_addr);
 378                 if (r) {
 379                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 380                         radeon_bo_unreserve(rdev->wb.wb_obj);
 381                         return r;
 382                 }
 383                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 384                 radeon_bo_unreserve(rdev->wb.wb_obj);
 385                 if (r) {
 386                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 387                         return r;
 388                 }
 389         }
 390         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 391         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 392                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 393         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 394         return 0;
 395 }
 396
 397 void r100_wb_disable(struct radeon_device *rdev)
 398 {
 399         WREG32(R_000770_SCRATCH_UMSK, 0);
 400 }
 401
 402 void r100_wb_fini(struct radeon_device *rdev)
 403 {
 404         int r;
 405
 406         r100_wb_disable(rdev);
 407         if (rdev->wb.wb_obj) {
 408                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 409                 if (unlikely(r != 0)) {
 410                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 411                         return;
 412                 }
 413                 radeon_bo_kunmap(rdev->wb.wb_obj);
 414                 radeon_bo_unpin(rdev->wb.wb_obj);
 415                 radeon_bo_unreserve(rdev->wb.wb_obj);
 416                 radeon_bo_unref(&rdev->wb.wb_obj);
 417                 rdev->wb.wb = NULL;
 418                 rdev->wb.wb_obj = NULL;
 419         }
 420 }
 421
 422 int r100_copy_blit(struct radeon_device *rdev,
 423                    uint64_t src_offset,
 424                    uint64_t dst_offset,
 425                    unsigned num_pages,
 426                    struct radeon_fence *fence)
 427 {
 428         uint32_t cur_pages;
 429         uint32_t stride_bytes = PAGE_SIZE;
 430         uint32_t pitch;
 431         uint32_t stride_pixels;
 432         unsigned ndw;
 433         int num_loops;
 434         int r = 0;
 435
 436         /* radeon limited to 16k stride */
 437         stride_bytes &= 0x3fff;
 438         /* radeon pitch is /64 */
 439         pitch = stride_bytes / 64;
 440         stride_pixels = stride_bytes / 4;
 441         num_loops = DIV_ROUND_UP(num_pages, 8191);
 442
 443         /* Ask for enough room for blit + flush + fence */
 444         ndw = 64 + (10 * num_loops);
 445         r = radeon_ring_lock(rdev, ndw);
 446         if (r) {
 447                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 448                 return -EINVAL;
 449         }
 450         while (num_pages > 0) {
 451                 cur_pages = num_pages;
 452                 if (cur_pages > 8191) {
 453                         cur_pages = 8191;
 454                 }
 455                 num_pages -= cur_pages;
 456
 457                 /* pages are in Y direction - height
 458                    page width in X direction - width */
 459                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 460                 radeon_ring_write(rdev,
 461                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 462                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 463                                   RADEON_GMC_SRC_CLIPPING |
 464                                   RADEON_GMC_DST_CLIPPING |
 465                                   RADEON_GMC_BRUSH_NONE |
 466                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 467                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 468                                   RADEON_ROP3_S |
 469                                   RADEON_DP_SRC_SOURCE_MEMORY |
 470                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 471                                   RADEON_GMC_WR_MSK_DIS);
 472                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 473                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 474                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 475                 radeon_ring_write(rdev, 0);
 476                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 477                 radeon_ring_write(rdev, num_pages);
 478                 radeon_ring_write(rdev, num_pages);
 479                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 480         }
 481         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 482         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 483         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 484         radeon_ring_write(rdev,
 485                           RADEON_WAIT_2D_IDLECLEAN |
 486                           RADEON_WAIT_HOST_IDLECLEAN |
 487                           RADEON_WAIT_DMA_GUI_IDLE);
 488         if (fence) {
 489                 r = radeon_fence_emit(rdev, fence);
 490         }
 491         radeon_ring_unlock_commit(rdev);
 492         return r;
 493 }
 494
 495 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 496 {
 497         unsigned i;
 498         u32 tmp;
 499
 500         for (i = 0; i < rdev->usec_timeout; i++) {
 501                 tmp = RREG32(R_000E40_RBBM_STATUS);
 502                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 503                         return 0;
 504                 }
 505                 udelay(1);
 506         }
 507         return -1;
 508 }
 509
 510 void r100_ring_start(struct radeon_device *rdev)
 511 {
 512         int r;
 513
 514         r = radeon_ring_lock(rdev, 2);
 515         if (r) {
 516                 return;
 517         }
 518         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 519         radeon_ring_write(rdev,
 520                           RADEON_ISYNC_ANY2D_IDLE3D |
 521                           RADEON_ISYNC_ANY3D_IDLE2D |
 522                           RADEON_ISYNC_WAIT_IDLEGUI |
 523                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 524         radeon_ring_unlock_commit(rdev);
 525 }
 526
 527
 528 /* Load the microcode for the CP */
 529 static int r100_cp_init_microcode(struct radeon_device *rdev)
 530 {
 531         struct platform_device *pdev;
 532         const char *fw_name = NULL;
 533         int err;
 534
 535         DRM_DEBUG("\n");
 536
 537         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 538         err = IS_ERR(pdev);
 539         if (err) {
 540                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 541                 return -EINVAL;
 542         }
 543         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 544             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 545             (rdev->family == CHIP_RS200)) {
 546                 DRM_INFO("Loading R100 Microcode\n");
 547                 fw_name = FIRMWARE_R100;
 548         } else if ((rdev->family == CHIP_R200) ||
 549                    (rdev->family == CHIP_RV250) ||
 550                    (rdev->family == CHIP_RV280) ||
 551                    (rdev->family == CHIP_RS300)) {
 552                 DRM_INFO("Loading R200 Microcode\n");
 553                 fw_name = FIRMWARE_R200;
 554         } else if ((rdev->family == CHIP_R300) ||
 555                    (rdev->family == CHIP_R350) ||
 556                    (rdev->family == CHIP_RV350) ||
 557                    (rdev->family == CHIP_RV380) ||
 558                    (rdev->family == CHIP_RS400) ||
 559                    (rdev->family == CHIP_RS480)) {
 560                 DRM_INFO("Loading R300 Microcode\n");
 561                 fw_name = FIRMWARE_R300;
 562         } else if ((rdev->family == CHIP_R420) ||
 563                    (rdev->family == CHIP_R423) ||
 564                    (rdev->family == CHIP_RV410)) {
 565                 DRM_INFO("Loading R400 Microcode\n");
 566                 fw_name = FIRMWARE_R420;
 567         } else if ((rdev->family == CHIP_RS690) ||
 568                    (rdev->family == CHIP_RS740)) {
 569                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 570                 fw_name = FIRMWARE_RS690;
 571         } else if (rdev->family == CHIP_RS600) {
 572                 DRM_INFO("Loading RS600 Microcode\n");
 573                 fw_name = FIRMWARE_RS600;
 574         } else if ((rdev->family == CHIP_RV515) ||
 575                    (rdev->family == CHIP_R520) ||
 576                    (rdev->family == CHIP_RV530) ||
 577                    (rdev->family == CHIP_R580) ||
 578                    (rdev->family == CHIP_RV560) ||
 579                    (rdev->family == CHIP_RV570)) {
 580                 DRM_INFO("Loading R500 Microcode\n");
 581                 fw_name = FIRMWARE_R520;
 582         }
 583
 584         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 585         platform_device_unregister(pdev);
 586         if (err) {
 587                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 588                        fw_name);
 589         } else if (rdev->me_fw->size % 8) {
 590                 printk(KERN_ERR
 591                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 592                        rdev->me_fw->size, fw_name);
 593                 err = -EINVAL;
 594                 release_firmware(rdev->me_fw);
 595                 rdev->me_fw = NULL;
 596         }
 597         return err;
 598 }
 599
 600 static void r100_cp_load_microcode(struct radeon_device *rdev)
 601 {
 602         const __be32 *fw_data;
 603         int i, size;
 604
 605         if (r100_gui_wait_for_idle(rdev)) {
 606                 printk(KERN_WARNING "Failed to wait GUI idle while "
 607                        "programming pipes. Bad things might happen.\n");
 608         }
 609
 610         if (rdev->me_fw) {
 611                 size = rdev->me_fw->size / 4;
 612                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 613                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 614                 for (i = 0; i < size; i += 2) {
 615                         WREG32(RADEON_CP_ME_RAM_DATAH,
 616                                be32_to_cpup(&fw_data[i]));
 617                         WREG32(RADEON_CP_ME_RAM_DATAL,
 618                                be32_to_cpup(&fw_data[i + 1]));
 619                 }
 620         }
 621 }
 622
 623 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 624 {
 625         unsigned rb_bufsz;
 626         unsigned rb_blksz;
 627         unsigned max_fetch;
 628         unsigned pre_write_timer;
 629         unsigned pre_write_limit;
 630         unsigned indirect2_start;
 631         unsigned indirect1_start;
 632         uint32_t tmp;
 633         int r;
 634
 635         if (r100_debugfs_cp_init(rdev)) {
 636                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 637         }
 638         /* Reset CP */
 639         tmp = RREG32(RADEON_CP_CSQ_STAT);
 640         if ((tmp & (1 << 31))) {
 641                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 642                 WREG32(RADEON_CP_CSQ_MODE, 0);
 643                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 644                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 645                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 646                 mdelay(2);
 647                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 648                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 649                 mdelay(2);
 650                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 651                 if ((tmp & (1 << 31))) {
 652                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 653                 }
 654         } else {
 655                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 656         }
 657
 658         if (!rdev->me_fw) {
 659                 r = r100_cp_init_microcode(rdev);
 660                 if (r) {
 661                         DRM_ERROR("Failed to load firmware!\n");
 662                         return r;
 663                 }
 664         }
 665
 666         /* Align ring size */
 667         rb_bufsz = drm_order(ring_size / 8);
 668         ring_size = (1 << (rb_bufsz + 1)) * 4;
 669         r100_cp_load_microcode(rdev);
 670         r = radeon_ring_init(rdev, ring_size);
 671         if (r) {
 672                 return r;
 673         }
 674         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 675          * the rptr copy in system ram */
 676         rb_blksz = 9;
 677         /* cp will read 128bytes at a time (4 dwords) */
 678         max_fetch = 1;
 679         rdev->cp.align_mask = 16 - 1;
 680         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 681         pre_write_timer = 64;
 682         /* Force CP_RB_WPTR write if written more than one time before the
 683          * delay expire
 684          */
 685         pre_write_limit = 0;
 686         /* Setup the cp cache like this (cache size is 96 dwords) :
 687          *      RING            0  to 15
 688          *      INDIRECT1       16 to 79
 689          *      INDIRECT2       80 to 95
 690          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 691          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 692          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 693          * Idea being that most of the gpu cmd will be through indirect1 buffer
 694          * so it gets the bigger cache.
 695          */
 696         indirect2_start = 80;
 697         indirect1_start = 16;
 698         /* cp setup */
 699         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 700         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 701                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 702                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 703                RADEON_RB_NO_UPDATE);
 704 #ifdef __BIG_ENDIAN
 705         tmp |= RADEON_BUF_SWAP_32BIT;
 706 #endif
 707         WREG32(RADEON_CP_RB_CNTL, tmp);
 708
 709         /* Set ring address */
 710         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 711         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 712         /* Force read & write ptr to 0 */
 713         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 714         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 715         WREG32(RADEON_CP_RB_WPTR, 0);
 716         WREG32(RADEON_CP_RB_CNTL, tmp);
 717         udelay(10);
 718         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 719         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 720         /* Set cp mode to bus mastering & enable cp*/
 721         WREG32(RADEON_CP_CSQ_MODE,
 722                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 723                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 724         WREG32(0x718, 0);
 725         WREG32(0x744, 0x00004D4D);
 726         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 727         radeon_ring_start(rdev);
 728         r = radeon_ring_test(rdev);
 729         if (r) {
 730                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 731                 return r;
 732         }
 733         rdev->cp.ready = true;
 734         return 0;
 735 }
 736
 737 void r100_cp_fini(struct radeon_device *rdev)
 738 {
 739         if (r100_cp_wait_for_idle(rdev)) {
 740                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 741         }
 742         /* Disable ring */
 743         r100_cp_disable(rdev);
 744         radeon_ring_fini(rdev);
 745         DRM_INFO("radeon: cp finalized\n");
 746 }
 747
 748 void r100_cp_disable(struct radeon_device *rdev)
 749 {
 750         /* Disable ring */
 751         rdev->cp.ready = false;
 752         WREG32(RADEON_CP_CSQ_MODE, 0);
 753         WREG32(RADEON_CP_CSQ_CNTL, 0);
 754         if (r100_gui_wait_for_idle(rdev)) {
 755                 printk(KERN_WARNING "Failed to wait GUI idle while "
 756                        "programming pipes. Bad things might happen.\n");
 757         }
 758 }
 759
 760 int r100_cp_reset(struct radeon_device *rdev)
 761 {
 762         uint32_t tmp;
 763         bool reinit_cp;
 764         int i;
 765
 766         reinit_cp = rdev->cp.ready;
 767         rdev->cp.ready = false;
 768         WREG32(RADEON_CP_CSQ_MODE, 0);
 769         WREG32(RADEON_CP_CSQ_CNTL, 0);
 770         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 771         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 772         udelay(200);
 773         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 774         /* Wait to prevent race in RBBM_STATUS */
 775         mdelay(1);
 776         for (i = 0; i < rdev->usec_timeout; i++) {
 777                 tmp = RREG32(RADEON_RBBM_STATUS);
 778                 if (!(tmp & (1 << 16))) {
 779                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 780                                  tmp);
 781                         if (reinit_cp) {
 782                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 783                         }
 784                         return 0;
 785                 }
 786                 DRM_UDELAY(1);
 787         }
 788         tmp = RREG32(RADEON_RBBM_STATUS);
 789         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 790         return -1;
 791 }
 792
 793 void r100_cp_commit(struct radeon_device *rdev)
 794 {
 795         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 796         (void)RREG32(RADEON_CP_RB_WPTR);
 797 }
 798
 799
 800 /*
 801  * CS functions
 802  */
 803 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 804                           struct radeon_cs_packet *pkt,
 805                           const unsigned *auth, unsigned n,
 806                           radeon_packet0_check_t check)
 807 {
 808         unsigned reg;
 809         unsigned i, j, m;
 810         unsigned idx;
 811         int r;
 812
 813         idx = pkt->idx + 1;
 814         reg = pkt->reg;
 815         /* Check that register fall into register range
 816          * determined by the number of entry (n) in the
 817          * safe register bitmap.
 818          */
 819         if (pkt->one_reg_wr) {
 820                 if ((reg >> 7) > n) {
 821                         return -EINVAL;
 822                 }
 823         } else {
 824                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 825                         return -EINVAL;
 826                 }
 827         }
 828         for (i = 0; i <= pkt->count; i++, idx++) {
 829                 j = (reg >> 7);
 830                 m = 1 << ((reg >> 2) & 31);
 831                 if (auth[j] & m) {
 832                         r = check(p, pkt, idx, reg);
 833                         if (r) {
 834                                 return r;
 835                         }
 836                 }
 837                 if (pkt->one_reg_wr) {
 838                         if (!(auth[j] & m)) {
 839                                 break;
 840                         }
 841                 } else {
 842                         reg += 4;
 843                 }
 844         }
 845         return 0;
 846 }
 847
 848 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 849                          struct radeon_cs_packet *pkt)
 850 {
 851         volatile uint32_t *ib;
 852         unsigned i;
 853         unsigned idx;
 854
 855         ib = p->ib->ptr;
 856         idx = pkt->idx;
 857         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 858                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 859         }
 860 }
 861
 862 /**
 863  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 864  * @parser:     parser structure holding parsing context.
 865  * @pkt:        where to store packet informations
 866  *
 867  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 868  * if packet is bigger than remaining ib size. or if packets is unknown.
 869  **/
 870 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 871                          struct radeon_cs_packet *pkt,
 872                          unsigned idx)
 873 {
 874         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 875         uint32_t header;
 876
 877         if (idx >= ib_chunk->length_dw) {
 878                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 879                           idx, ib_chunk->length_dw);
 880                 return -EINVAL;
 881         }
 882         header = radeon_get_ib_value(p, idx);
 883         pkt->idx = idx;
 884         pkt->type = CP_PACKET_GET_TYPE(header);
 885         pkt->count = CP_PACKET_GET_COUNT(header);
 886         switch (pkt->type) {
 887         case PACKET_TYPE0:
 888                 pkt->reg = CP_PACKET0_GET_REG(header);
 889                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 890                 break;
 891         case PACKET_TYPE3:
 892                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 893                 break;
 894         case PACKET_TYPE2:
 895                 pkt->count = -1;
 896                 break;
 897         default:
 898                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 899                 return -EINVAL;
 900         }
 901         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 902                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 903                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 904                 return -EINVAL;
 905         }
 906         return 0;
 907 }
 908
 909 /**
 910  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 911  * @parser:             parser structure holding parsing context.
 912  *
 913  * Userspace sends a special sequence for VLINE waits.
 914  * PACKET0 - VLINE_START_END + value
 915  * PACKET0 - WAIT_UNTIL +_value
 916  * RELOC (P3) - crtc_id in reloc.
 917  *
 918  * This function parses this and relocates the VLINE START END
 919  * and WAIT UNTIL packets to the correct crtc.
 920  * It also detects a switched off crtc and nulls out the
 921  * wait in that case.
 922  */
 923 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 924 {
 925         struct drm_mode_object *obj;
 926         struct drm_crtc *crtc;
 927         struct radeon_crtc *radeon_crtc;
 928         struct radeon_cs_packet p3reloc, waitreloc;
 929         int crtc_id;
 930         int r;
 931         uint32_t header, h_idx, reg;
 932         volatile uint32_t *ib;
 933
 934         ib = p->ib->ptr;
 935
 936         /* parse the wait until */
 937         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 938         if (r)
 939                 return r;
 940
 941         /* check its a wait until and only 1 count */
 942         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 943             waitreloc.count != 0) {
 944                 DRM_ERROR("vline wait had illegal wait until segment\n");
 945                 r = -EINVAL;
 946                 return r;
 947         }
 948
 949         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 950                 DRM_ERROR("vline wait had illegal wait until\n");
 951                 r = -EINVAL;
 952                 return r;
 953         }
 954
 955         /* jump over the NOP */
 956         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 957         if (r)
 958                 return r;
 959
 960         h_idx = p->idx - 2;
 961         p->idx += waitreloc.count + 2;
 962         p->idx += p3reloc.count + 2;
 963
 964         header = radeon_get_ib_value(p, h_idx);
 965         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 966         reg = CP_PACKET0_GET_REG(header);
 967         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 968         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 969         if (!obj) {
 970                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 971                 r = -EINVAL;
 972                 goto out;
 973         }
 974         crtc = obj_to_crtc(obj);
 975         radeon_crtc = to_radeon_crtc(crtc);
 976         crtc_id = radeon_crtc->crtc_id;
 977
 978         if (!crtc->enabled) {
 979                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 980                 ib[h_idx + 2] = PACKET2(0);
 981                 ib[h_idx + 3] = PACKET2(0);
 982         } else if (crtc_id == 1) {
 983                 switch (reg) {
 984                 case AVIVO_D1MODE_VLINE_START_END:
 985                         header &= ~R300_CP_PACKET0_REG_MASK;
 986                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 987                         break;
 988                 case RADEON_CRTC_GUI_TRIG_VLINE:
 989                         header &= ~R300_CP_PACKET0_REG_MASK;
 990                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 991                         break;
 992                 default:
 993                         DRM_ERROR("unknown crtc reloc\n");
 994                         r = -EINVAL;
 995                         goto out;
 996                 }
 997                 ib[h_idx] = header;
 998                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 999         }
1000 out:
1001         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1002         return r;
1003 }
1004
1005 /**
1006  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1007  * @parser:             parser structure holding parsing context.
1008  * @data:               pointer to relocation data
1009  * @offset_start:       starting offset
1010  * @offset_mask:        offset mask (to align start offset on)
1011  * @reloc:              reloc informations
1012  *
1013  * Check next packet is relocation packet3, do bo validation and compute
1014  * GPU offset using the provided start.
1015  **/
1016 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1017                               struct radeon_cs_reloc **cs_reloc)
1018 {
1019         struct radeon_cs_chunk *relocs_chunk;
1020         struct radeon_cs_packet p3reloc;
1021         unsigned idx;
1022         int r;
1023
1024         if (p->chunk_relocs_idx == -1) {
1025                 DRM_ERROR("No relocation chunk !\n");
1026                 return -EINVAL;
1027         }
1028         *cs_reloc = NULL;
1029         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1030         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1031         if (r) {
1032                 return r;
1033         }
1034         p->idx += p3reloc.count + 2;
1035         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1036                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1037                           p3reloc.idx);
1038                 r100_cs_dump_packet(p, &p3reloc);
1039                 return -EINVAL;
1040         }
1041         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1042         if (idx >= relocs_chunk->length_dw) {
1043                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1044                           idx, relocs_chunk->length_dw);
1045                 r100_cs_dump_packet(p, &p3reloc);
1046                 return -EINVAL;
1047         }
1048         /* FIXME: we assume reloc size is 4 dwords */
1049         *cs_reloc = p->relocs_ptr[(idx / 4)];
1050         return 0;
1051 }
1052
1053 static int r100_get_vtx_size(uint32_t vtx_fmt)
1054 {
1055         int vtx_size;
1056         vtx_size = 2;
1057         /* ordered according to bits in spec */
1058         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1059                 vtx_size++;
1060         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1061                 vtx_size += 3;
1062         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1063                 vtx_size++;
1064         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1065                 vtx_size++;
1066         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1067                 vtx_size += 3;
1068         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1069                 vtx_size++;
1070         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1071                 vtx_size++;
1072         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1073                 vtx_size += 2;
1074         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1075                 vtx_size += 2;
1076         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1077                 vtx_size++;
1078         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1079                 vtx_size += 2;
1080         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1081                 vtx_size++;
1082         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1083                 vtx_size += 2;
1084         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1085                 vtx_size++;
1086         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1087                 vtx_size++;
1088         /* blend weight */
1089         if (vtx_fmt & (0x7 << 15))
1090                 vtx_size += (vtx_fmt >> 15) & 0x7;
1091         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1092                 vtx_size += 3;
1093         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1094                 vtx_size += 2;
1095         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1096                 vtx_size++;
1097         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1098                 vtx_size++;
1099         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1100                 vtx_size++;
1101         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1102                 vtx_size++;
1103         return vtx_size;
1104 }
1105
1106 static int r100_packet0_check(struct radeon_cs_parser *p,
1107                               struct radeon_cs_packet *pkt,
1108                               unsigned idx, unsigned reg)
1109 {
1110         struct radeon_cs_reloc *reloc;
1111         struct r100_cs_track *track;
1112         volatile uint32_t *ib;
1113         uint32_t tmp;
1114         int r;
1115         int i, face;
1116         u32 tile_flags = 0;
1117         u32 idx_value;
1118
1119         ib = p->ib->ptr;
1120         track = (struct r100_cs_track *)p->track;
1121
1122         idx_value = radeon_get_ib_value(p, idx);
1123
1124         switch (reg) {
1125         case RADEON_CRTC_GUI_TRIG_VLINE:
1126                 r = r100_cs_packet_parse_vline(p);
1127                 if (r) {
1128                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1129                                   idx, reg);
1130                         r100_cs_dump_packet(p, pkt);
1131                         return r;
1132                 }
1133                 break;
1134                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1135                  * range access */
1136         case RADEON_DST_PITCH_OFFSET:
1137         case RADEON_SRC_PITCH_OFFSET:
1138                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1139                 if (r)
1140                         return r;
1141                 break;
1142         case RADEON_RB3D_DEPTHOFFSET:
1143                 r = r100_cs_packet_next_reloc(p, &reloc);
1144                 if (r) {
1145                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1146                                   idx, reg);
1147                         r100_cs_dump_packet(p, pkt);
1148                         return r;
1149                 }
1150                 track->zb.robj = reloc->robj;
1151                 track->zb.offset = idx_value;
1152                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1153                 break;
1154         case RADEON_RB3D_COLOROFFSET:
1155                 r = r100_cs_packet_next_reloc(p, &reloc);
1156                 if (r) {
1157                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1158                                   idx, reg);
1159                         r100_cs_dump_packet(p, pkt);
1160                         return r;
1161                 }
1162                 track->cb[0].robj = reloc->robj;
1163                 track->cb[0].offset = idx_value;
1164                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1165                 break;
1166         case RADEON_PP_TXOFFSET_0:
1167         case RADEON_PP_TXOFFSET_1:
1168         case RADEON_PP_TXOFFSET_2:
1169                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1170                 r = r100_cs_packet_next_reloc(p, &reloc);
1171                 if (r) {
1172                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1173                                   idx, reg);
1174                         r100_cs_dump_packet(p, pkt);
1175                         return r;
1176                 }
1177                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1178                 track->textures[i].robj = reloc->robj;
1179                 break;
1180         case RADEON_PP_CUBIC_OFFSET_T0_0:
1181         case RADEON_PP_CUBIC_OFFSET_T0_1:
1182         case RADEON_PP_CUBIC_OFFSET_T0_2:
1183         case RADEON_PP_CUBIC_OFFSET_T0_3:
1184         case RADEON_PP_CUBIC_OFFSET_T0_4:
1185                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1186                 r = r100_cs_packet_next_reloc(p, &reloc);
1187                 if (r) {
1188                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1189                                   idx, reg);
1190                         r100_cs_dump_packet(p, pkt);
1191                         return r;
1192                 }
1193                 track->textures[0].cube_info[i].offset = idx_value;
1194                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1195                 track->textures[0].cube_info[i].robj = reloc->robj;
1196                 break;
1197         case RADEON_PP_CUBIC_OFFSET_T1_0:
1198         case RADEON_PP_CUBIC_OFFSET_T1_1:
1199         case RADEON_PP_CUBIC_OFFSET_T1_2:
1200         case RADEON_PP_CUBIC_OFFSET_T1_3:
1201         case RADEON_PP_CUBIC_OFFSET_T1_4:
1202                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1203                 r = r100_cs_packet_next_reloc(p, &reloc);
1204                 if (r) {
1205                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1206                                   idx, reg);
1207                         r100_cs_dump_packet(p, pkt);
1208                         return r;
1209                 }
1210                 track->textures[1].cube_info[i].offset = idx_value;
1211                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1212                 track->textures[1].cube_info[i].robj = reloc->robj;
1213                 break;
1214         case RADEON_PP_CUBIC_OFFSET_T2_0:
1215         case RADEON_PP_CUBIC_OFFSET_T2_1:
1216         case RADEON_PP_CUBIC_OFFSET_T2_2:
1217         case RADEON_PP_CUBIC_OFFSET_T2_3:
1218         case RADEON_PP_CUBIC_OFFSET_T2_4:
1219                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1220                 r = r100_cs_packet_next_reloc(p, &reloc);
1221                 if (r) {
1222                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1223                                   idx, reg);
1224                         r100_cs_dump_packet(p, pkt);
1225                         return r;
1226                 }
1227                 track->textures[2].cube_info[i].offset = idx_value;
1228                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1229                 track->textures[2].cube_info[i].robj = reloc->robj;
1230                 break;
1231         case RADEON_RE_WIDTH_HEIGHT:
1232                 track->maxy = ((idx_value >> 16) & 0x7FF);
1233                 break;
1234         case RADEON_RB3D_COLORPITCH:
1235                 r = r100_cs_packet_next_reloc(p, &reloc);
1236                 if (r) {
1237                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1238                                   idx, reg);
1239                         r100_cs_dump_packet(p, pkt);
1240                         return r;
1241                 }
1242
1243                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1244                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1245                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1246                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1247
1248                 tmp = idx_value & ~(0x7 << 16);
1249                 tmp |= tile_flags;
1250                 ib[idx] = tmp;
1251
1252                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1253                 break;
1254         case RADEON_RB3D_DEPTHPITCH:
1255                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1256                 break;
1257         case RADEON_RB3D_CNTL:
1258                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1259                 case 7:
1260                 case 8:
1261                 case 9:
1262                 case 11:
1263                 case 12:
1264                         track->cb[0].cpp = 1;
1265                         break;
1266                 case 3:
1267                 case 4:
1268                 case 15:
1269                         track->cb[0].cpp = 2;
1270                         break;
1271                 case 6:
1272                         track->cb[0].cpp = 4;
1273                         break;
1274                 default:
1275                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1276                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1277                         return -EINVAL;
1278                 }
1279                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1280                 break;
1281         case RADEON_RB3D_ZSTENCILCNTL:
1282                 switch (idx_value & 0xf) {
1283                 case 0:
1284                         track->zb.cpp = 2;
1285                         break;
1286                 case 2:
1287                 case 3:
1288                 case 4:
1289                 case 5:
1290                 case 9:
1291                 case 11:
1292                         track->zb.cpp = 4;
1293                         break;
1294                 default:
1295                         break;
1296                 }
1297                 break;
1298         case RADEON_RB3D_ZPASS_ADDR:
1299                 r = r100_cs_packet_next_reloc(p, &reloc);
1300                 if (r) {
1301                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1302                                   idx, reg);
1303                         r100_cs_dump_packet(p, pkt);
1304                         return r;
1305                 }
1306                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1307                 break;
1308         case RADEON_PP_CNTL:
1309                 {
1310                         uint32_t temp = idx_value >> 4;
1311                         for (i = 0; i < track->num_texture; i++)
1312                                 track->textures[i].enabled = !!(temp & (1 << i));
1313                 }
1314                 break;
1315         case RADEON_SE_VF_CNTL:
1316                 track->vap_vf_cntl = idx_value;
1317                 break;
1318         case RADEON_SE_VTX_FMT:
1319                 track->vtx_size = r100_get_vtx_size(idx_value);
1320                 break;
1321         case RADEON_PP_TEX_SIZE_0:
1322         case RADEON_PP_TEX_SIZE_1:
1323         case RADEON_PP_TEX_SIZE_2:
1324                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1325                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1326                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1327                 break;
1328         case RADEON_PP_TEX_PITCH_0:
1329         case RADEON_PP_TEX_PITCH_1:
1330         case RADEON_PP_TEX_PITCH_2:
1331                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1332                 track->textures[i].pitch = idx_value + 32;
1333                 break;
1334         case RADEON_PP_TXFILTER_0:
1335         case RADEON_PP_TXFILTER_1:
1336         case RADEON_PP_TXFILTER_2:
1337                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1338                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1339                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1340                 tmp = (idx_value >> 23) & 0x7;
1341                 if (tmp == 2 || tmp == 6)
1342                         track->textures[i].roundup_w = false;
1343                 tmp = (idx_value >> 27) & 0x7;
1344                 if (tmp == 2 || tmp == 6)
1345                         track->textures[i].roundup_h = false;
1346                 break;
1347         case RADEON_PP_TXFORMAT_0:
1348         case RADEON_PP_TXFORMAT_1:
1349         case RADEON_PP_TXFORMAT_2:
1350                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1351                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1352                         track->textures[i].use_pitch = 1;
1353                 } else {
1354                         track->textures[i].use_pitch = 0;
1355                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1356                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1357                 }
1358                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1359                         track->textures[i].tex_coord_type = 2;
1360                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1361                 case RADEON_TXFORMAT_I8:
1362                 case RADEON_TXFORMAT_RGB332:
1363                 case RADEON_TXFORMAT_Y8:
1364                         track->textures[i].cpp = 1;
1365                         break;
1366                 case RADEON_TXFORMAT_AI88:
1367                 case RADEON_TXFORMAT_ARGB1555:
1368                 case RADEON_TXFORMAT_RGB565:
1369                 case RADEON_TXFORMAT_ARGB4444:
1370                 case RADEON_TXFORMAT_VYUY422:
1371                 case RADEON_TXFORMAT_YVYU422:
1372                 case RADEON_TXFORMAT_DXT1:
1373                 case RADEON_TXFORMAT_SHADOW16:
1374                 case RADEON_TXFORMAT_LDUDV655:
1375                 case RADEON_TXFORMAT_DUDV88:
1376                         track->textures[i].cpp = 2;
1377                         break;
1378                 case RADEON_TXFORMAT_ARGB8888:
1379                 case RADEON_TXFORMAT_RGBA8888:
1380                 case RADEON_TXFORMAT_DXT23:
1381                 case RADEON_TXFORMAT_DXT45:
1382                 case RADEON_TXFORMAT_SHADOW32:
1383                 case RADEON_TXFORMAT_LDUDUV8888:
1384                         track->textures[i].cpp = 4;
1385                         break;
1386                 }
1387                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1388                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1389                 break;
1390         case RADEON_PP_CUBIC_FACES_0:
1391         case RADEON_PP_CUBIC_FACES_1:
1392         case RADEON_PP_CUBIC_FACES_2:
1393                 tmp = idx_value;
1394                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1395                 for (face = 0; face < 4; face++) {
1396                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1397                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1398                 }
1399                 break;
1400         default:
1401                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1402                        reg, idx);
1403                 return -EINVAL;
1404         }
1405         return 0;
1406 }
1407
1408 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1409                                          struct radeon_cs_packet *pkt,
1410                                          struct radeon_bo *robj)
1411 {
1412         unsigned idx;
1413         u32 value;
1414         idx = pkt->idx + 1;
1415         value = radeon_get_ib_value(p, idx + 2);
1416         if ((value + 1) > radeon_bo_size(robj)) {
1417                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1418                           "(need %u have %lu) !\n",
1419                           value + 1,
1420                           radeon_bo_size(robj));
1421                 return -EINVAL;
1422         }
1423         return 0;
1424 }
1425
1426 static int r100_packet3_check(struct radeon_cs_parser *p,
1427                               struct radeon_cs_packet *pkt)
1428 {
1429         struct radeon_cs_reloc *reloc;
1430         struct r100_cs_track *track;
1431         unsigned idx;
1432         volatile uint32_t *ib;
1433         int r;
1434
1435         ib = p->ib->ptr;
1436         idx = pkt->idx + 1;
1437         track = (struct r100_cs_track *)p->track;
1438         switch (pkt->opcode) {
1439         case PACKET3_3D_LOAD_VBPNTR:
1440                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1441                 if (r)
1442                         return r;
1443                 break;
1444         case PACKET3_INDX_BUFFER:
1445                 r = r100_cs_packet_next_reloc(p, &reloc);
1446                 if (r) {
1447                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1448                         r100_cs_dump_packet(p, pkt);
1449                         return r;
1450                 }
1451                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1452                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1453                 if (r) {
1454                         return r;
1455                 }
1456                 break;
1457         case 0x23:
1458                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1459                 r = r100_cs_packet_next_reloc(p, &reloc);
1460                 if (r) {
1461                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1462                         r100_cs_dump_packet(p, pkt);
1463                         return r;
1464                 }
1465                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1466                 track->num_arrays = 1;
1467                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1468
1469                 track->arrays[0].robj = reloc->robj;
1470                 track->arrays[0].esize = track->vtx_size;
1471
1472                 track->max_indx = radeon_get_ib_value(p, idx+1);
1473
1474                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1475                 track->immd_dwords = pkt->count - 1;
1476                 r = r100_cs_track_check(p->rdev, track);
1477                 if (r)
1478                         return r;
1479                 break;
1480         case PACKET3_3D_DRAW_IMMD:
1481                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1482                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1483                         return -EINVAL;
1484                 }
1485                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1486                 track->immd_dwords = pkt->count - 1;
1487                 r = r100_cs_track_check(p->rdev, track);
1488                 if (r)
1489                         return r;
1490                 break;
1491                 /* triggers drawing using in-packet vertex data */
1492         case PACKET3_3D_DRAW_IMMD_2:
1493                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1494                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1495                         return -EINVAL;
1496                 }
1497                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1498                 track->immd_dwords = pkt->count;
1499                 r = r100_cs_track_check(p->rdev, track);
1500                 if (r)
1501                         return r;
1502                 break;
1503                 /* triggers drawing using in-packet vertex data */
1504         case PACKET3_3D_DRAW_VBUF_2:
1505                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1506                 r = r100_cs_track_check(p->rdev, track);
1507                 if (r)
1508                         return r;
1509                 break;
1510                 /* triggers drawing of vertex buffers setup elsewhere */
1511         case PACKET3_3D_DRAW_INDX_2:
1512                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1513                 r = r100_cs_track_check(p->rdev, track);
1514                 if (r)
1515                         return r;
1516                 break;
1517                 /* triggers drawing using indices to vertex buffer */
1518         case PACKET3_3D_DRAW_VBUF:
1519                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1520                 r = r100_cs_track_check(p->rdev, track);
1521                 if (r)
1522                         return r;
1523                 break;
1524                 /* triggers drawing of vertex buffers setup elsewhere */
1525         case PACKET3_3D_DRAW_INDX:
1526                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1527                 r = r100_cs_track_check(p->rdev, track);
1528                 if (r)
1529                         return r;
1530                 break;
1531                 /* triggers drawing using indices to vertex buffer */
1532         case PACKET3_NOP:
1533                 break;
1534         default:
1535                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1536                 return -EINVAL;
1537         }
1538         return 0;
1539 }
1540
1541 int r100_cs_parse(struct radeon_cs_parser *p)
1542 {
1543         struct radeon_cs_packet pkt;
1544         struct r100_cs_track *track;
1545         int r;
1546
1547         track = kzalloc(sizeof(*track), GFP_KERNEL);
1548         r100_cs_track_clear(p->rdev, track);
1549         p->track = track;
1550         do {
1551                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1552                 if (r) {
1553                         return r;
1554                 }
1555                 p->idx += pkt.count + 2;
1556                 switch (pkt.type) {
1557                         case PACKET_TYPE0:
1558                                 if (p->rdev->family >= CHIP_R200)
1559                                         r = r100_cs_parse_packet0(p, &pkt,
1560                                                                   p->rdev->config.r100.reg_safe_bm,
1561                                                                   p->rdev->config.r100.reg_safe_bm_size,
1562                                                                   &r200_packet0_check);
1563                                 else
1564                                         r = r100_cs_parse_packet0(p, &pkt,
1565                                                                   p->rdev->config.r100.reg_safe_bm,
1566                                                                   p->rdev->config.r100.reg_safe_bm_size,
1567                                                                   &r100_packet0_check);
1568                                 break;
1569                         case PACKET_TYPE2:
1570                                 break;
1571                         case PACKET_TYPE3:
1572                                 r = r100_packet3_check(p, &pkt);
1573                                 break;
1574                         default:
1575                                 DRM_ERROR("Unknown packet type %d !\n",
1576                                           pkt.type);
1577                                 return -EINVAL;
1578                 }
1579                 if (r) {
1580                         return r;
1581                 }
1582         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1583         return 0;
1584 }
1585
1586
1587 /*
1588  * Global GPU functions
1589  */
1590 void r100_errata(struct radeon_device *rdev)
1591 {
1592         rdev->pll_errata = 0;
1593
1594         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1595                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1596         }
1597
1598         if (rdev->family == CHIP_RV100 ||
1599             rdev->family == CHIP_RS100 ||
1600             rdev->family == CHIP_RS200) {
1601                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1602         }
1603 }
1604
1605 /* Wait for vertical sync on primary CRTC */
1606 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1607 {
1608         uint32_t crtc_gen_cntl, tmp;
1609         int i;
1610
1611         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1612         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1613             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1614                 return;
1615         }
1616         /* Clear the CRTC_VBLANK_SAVE bit */
1617         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1618         for (i = 0; i < rdev->usec_timeout; i++) {
1619                 tmp = RREG32(RADEON_CRTC_STATUS);
1620                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1621                         return;
1622                 }
1623                 DRM_UDELAY(1);
1624         }
1625 }
1626
1627 /* Wait for vertical sync on secondary CRTC */
1628 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1629 {
1630         uint32_t crtc2_gen_cntl, tmp;
1631         int i;
1632
1633         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1634         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1635             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1636                 return;
1637
1638         /* Clear the CRTC_VBLANK_SAVE bit */
1639         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1640         for (i = 0; i < rdev->usec_timeout; i++) {
1641                 tmp = RREG32(RADEON_CRTC2_STATUS);
1642                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1643                         return;
1644                 }
1645                 DRM_UDELAY(1);
1646         }
1647 }
1648
1649 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1650 {
1651         unsigned i;
1652         uint32_t tmp;
1653
1654         for (i = 0; i < rdev->usec_timeout; i++) {
1655                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1656                 if (tmp >= n) {
1657                         return 0;
1658                 }
1659                 DRM_UDELAY(1);
1660         }
1661         return -1;
1662 }
1663
1664 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1665 {
1666         unsigned i;
1667         uint32_t tmp;
1668
1669         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1670                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1671                        " Bad things might happen.\n");
1672         }
1673         for (i = 0; i < rdev->usec_timeout; i++) {
1674                 tmp = RREG32(RADEON_RBBM_STATUS);
1675                 if (!(tmp & (1 << 31))) {
1676                         return 0;
1677                 }
1678                 DRM_UDELAY(1);
1679         }
1680         return -1;
1681 }
1682
1683 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1684 {
1685         unsigned i;
1686         uint32_t tmp;
1687
1688         for (i = 0; i < rdev->usec_timeout; i++) {
1689                 /* read MC_STATUS */
1690                 tmp = RREG32(0x0150);
1691                 if (tmp & (1 << 2)) {
1692                         return 0;
1693                 }
1694                 DRM_UDELAY(1);
1695         }
1696         return -1;
1697 }
1698
1699 void r100_gpu_init(struct radeon_device *rdev)
1700 {
1701         /* TODO: anythings to do here ? pipes ? */
1702         r100_hdp_reset(rdev);
1703 }
1704
1705 void r100_hdp_flush(struct radeon_device *rdev)
1706 {
1707         u32 tmp;
1708         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1709         tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
1710         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1711 }
1712
1713 void r100_hdp_reset(struct radeon_device *rdev)
1714 {
1715         uint32_t tmp;
1716
1717         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1718         tmp |= (7 << 28);
1719         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1720         (void)RREG32(RADEON_HOST_PATH_CNTL);
1721         udelay(200);
1722         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1723         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1724         (void)RREG32(RADEON_HOST_PATH_CNTL);
1725 }
1726
1727 int r100_rb2d_reset(struct radeon_device *rdev)
1728 {
1729         uint32_t tmp;
1730         int i;
1731
1732         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1733         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1734         udelay(200);
1735         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1736         /* Wait to prevent race in RBBM_STATUS */
1737         mdelay(1);
1738         for (i = 0; i < rdev->usec_timeout; i++) {
1739                 tmp = RREG32(RADEON_RBBM_STATUS);
1740                 if (!(tmp & (1 << 26))) {
1741                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1742                                  tmp);
1743                         return 0;
1744                 }
1745                 DRM_UDELAY(1);
1746         }
1747         tmp = RREG32(RADEON_RBBM_STATUS);
1748         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1749         return -1;
1750 }
1751
1752 int r100_gpu_reset(struct radeon_device *rdev)
1753 {
1754         uint32_t status;
1755
1756         /* reset order likely matter */
1757         status = RREG32(RADEON_RBBM_STATUS);
1758         /* reset HDP */
1759         r100_hdp_reset(rdev);
1760         /* reset rb2d */
1761         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1762                 r100_rb2d_reset(rdev);
1763         }
1764         /* TODO: reset 3D engine */
1765         /* reset CP */
1766         status = RREG32(RADEON_RBBM_STATUS);
1767         if (status & (1 << 16)) {
1768                 r100_cp_reset(rdev);
1769         }
1770         /* Check if GPU is idle */
1771         status = RREG32(RADEON_RBBM_STATUS);
1772         if (status & (1 << 31)) {
1773                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1774                 return -1;
1775         }
1776         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1777         return 0;
1778 }
1779
1780 void r100_set_common_regs(struct radeon_device *rdev)
1781 {
1782         /* set these so they don't interfere with anything */
1783         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1784         WREG32(RADEON_SUBPIC_CNTL, 0);
1785         WREG32(RADEON_VIPH_CONTROL, 0);
1786         WREG32(RADEON_I2C_CNTL_1, 0);
1787         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1788         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1789         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1790 }
1791
1792 /*
1793  * VRAM info
1794  */
1795 static void r100_vram_get_type(struct radeon_device *rdev)
1796 {
1797         uint32_t tmp;
1798
1799         rdev->mc.vram_is_ddr = false;
1800         if (rdev->flags & RADEON_IS_IGP)
1801                 rdev->mc.vram_is_ddr = true;
1802         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1803                 rdev->mc.vram_is_ddr = true;
1804         if ((rdev->family == CHIP_RV100) ||
1805             (rdev->family == CHIP_RS100) ||
1806             (rdev->family == CHIP_RS200)) {
1807                 tmp = RREG32(RADEON_MEM_CNTL);
1808                 if (tmp & RV100_HALF_MODE) {
1809                         rdev->mc.vram_width = 32;
1810                 } else {
1811                         rdev->mc.vram_width = 64;
1812                 }
1813                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1814                         rdev->mc.vram_width /= 4;
1815                         rdev->mc.vram_is_ddr = true;
1816                 }
1817         } else if (rdev->family <= CHIP_RV280) {
1818                 tmp = RREG32(RADEON_MEM_CNTL);
1819                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1820                         rdev->mc.vram_width = 128;
1821                 } else {
1822                         rdev->mc.vram_width = 64;
1823                 }
1824         } else {
1825                 /* newer IGPs */
1826                 rdev->mc.vram_width = 128;
1827         }
1828 }
1829
1830 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1831 {
1832         u32 aper_size;
1833         u8 byte;
1834
1835         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1836
1837         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1838          * that is has the 2nd generation multifunction PCI interface
1839          */
1840         if (rdev->family == CHIP_RV280 ||
1841             rdev->family >= CHIP_RV350) {
1842                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1843                        ~RADEON_HDP_APER_CNTL);
1844                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1845                 return aper_size * 2;
1846         }
1847
1848         /* Older cards have all sorts of funny issues to deal with. First
1849          * check if it's a multifunction card by reading the PCI config
1850          * header type... Limit those to one aperture size
1851          */
1852         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1853         if (byte & 0x80) {
1854                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1855                 DRM_INFO("Limiting VRAM to one aperture\n");
1856                 return aper_size;
1857         }
1858
1859         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1860          * have set it up. We don't write this as it's broken on some ASICs but
1861          * we expect the BIOS to have done the right thing (might be too optimistic...)
1862          */
1863         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1864                 return aper_size * 2;
1865         return aper_size;
1866 }
1867
1868 void r100_vram_init_sizes(struct radeon_device *rdev)
1869 {
1870         u64 config_aper_size;
1871         u32 accessible;
1872
1873         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1874
1875         if (rdev->flags & RADEON_IS_IGP) {
1876                 uint32_t tom;
1877                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1878                 tom = RREG32(RADEON_NB_TOM);
1879                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1880                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1881                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1882                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1883                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1884         } else {
1885                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1886                 /* Some production boards of m6 will report 0
1887                  * if it's 8 MB
1888                  */
1889                 if (rdev->mc.real_vram_size == 0) {
1890                         rdev->mc.real_vram_size = 8192 * 1024;
1891                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1892                 }
1893                 /* let driver place VRAM */
1894                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1895                  /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1896                   * Novell bug 204882 + along with lots of ubuntu ones */
1897                 if (config_aper_size > rdev->mc.real_vram_size)
1898                         rdev->mc.mc_vram_size = config_aper_size;
1899                 else
1900                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1901         }
1902
1903         /* work out accessible VRAM */
1904         accessible = r100_get_accessible_vram(rdev);
1905
1906         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1907         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1908
1909         if (accessible > rdev->mc.aper_size)
1910                 accessible = rdev->mc.aper_size;
1911
1912         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1913                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1914
1915         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1916                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1917 }
1918
1919 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1920 {
1921         uint32_t temp;
1922
1923         temp = RREG32(RADEON_CONFIG_CNTL);
1924         if (state == false) {
1925                 temp &= ~(1<<8);
1926                 temp |= (1<<9);
1927         } else {
1928                 temp &= ~(1<<9);
1929         }
1930         WREG32(RADEON_CONFIG_CNTL, temp);
1931 }
1932
1933 void r100_vram_info(struct radeon_device *rdev)
1934 {
1935         r100_vram_get_type(rdev);
1936
1937         r100_vram_init_sizes(rdev);
1938 }
1939
1940
1941 /*
1942  * Indirect registers accessor
1943  */
1944 void r100_pll_errata_after_index(struct radeon_device *rdev)
1945 {
1946         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1947                 return;
1948         }
1949         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1950         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1951 }
1952
1953 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1954 {
1955         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1956          * or the chip could hang on a subsequent access
1957          */
1958         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1959                 udelay(5000);
1960         }
1961
1962         /* This function is required to workaround a hardware bug in some (all?)
1963          * revisions of the R300.  This workaround should be called after every
1964          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1965          * may not be correct.
1966          */
1967         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1968                 uint32_t save, tmp;
1969
1970                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1971                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1972                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1973                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1974                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1975         }
1976 }
1977
1978 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1979 {
1980         uint32_t data;
1981
1982         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1983         r100_pll_errata_after_index(rdev);
1984         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1985         r100_pll_errata_after_data(rdev);
1986         return data;
1987 }
1988
1989 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1990 {
1991         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1992         r100_pll_errata_after_index(rdev);
1993         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1994         r100_pll_errata_after_data(rdev);
1995 }
1996
1997 void r100_set_safe_registers(struct radeon_device *rdev)
1998 {
1999         if (ASIC_IS_RN50(rdev)) {
2000                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2001                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2002         } else if (rdev->family < CHIP_R200) {
2003                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2004                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2005         } else {
2006                 r200_set_safe_registers(rdev);
2007         }
2008 }
2009
2010 /*
2011  * Debugfs info
2012  */
2013 #if defined(CONFIG_DEBUG_FS)
2014 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2015 {
2016         struct drm_info_node *node = (struct drm_info_node *) m->private;
2017         struct drm_device *dev = node->minor->dev;
2018         struct radeon_device *rdev = dev->dev_private;
2019         uint32_t reg, value;
2020         unsigned i;
2021
2022         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2023         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2024         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2025         for (i = 0; i < 64; i++) {
2026                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2027                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2028                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2029                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2030                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2031         }
2032         return 0;
2033 }
2034
2035 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2036 {
2037         struct drm_info_node *node = (struct drm_info_node *) m->private;
2038         struct drm_device *dev = node->minor->dev;
2039         struct radeon_device *rdev = dev->dev_private;
2040         uint32_t rdp, wdp;
2041         unsigned count, i, j;
2042
2043         radeon_ring_free_size(rdev);
2044         rdp = RREG32(RADEON_CP_RB_RPTR);
2045         wdp = RREG32(RADEON_CP_RB_WPTR);
2046         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2047         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2048         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2049         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2050         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2051         seq_printf(m, "%u dwords in ring\n", count);
2052         for (j = 0; j <= count; j++) {
2053                 i = (rdp + j) & rdev->cp.ptr_mask;
2054                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2055         }
2056         return 0;
2057 }
2058
2059
2060 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2061 {
2062         struct drm_info_node *node = (struct drm_info_node *) m->private;
2063         struct drm_device *dev = node->minor->dev;
2064         struct radeon_device *rdev = dev->dev_private;
2065         uint32_t csq_stat, csq2_stat, tmp;
2066         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2067         unsigned i;
2068
2069         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2070         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2071         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2072         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2073         r_rptr = (csq_stat >> 0) & 0x3ff;
2074         r_wptr = (csq_stat >> 10) & 0x3ff;
2075         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2076         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2077         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2078         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2079         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2080         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2081         seq_printf(m, "Ring rptr %u\n", r_rptr);
2082         seq_printf(m, "Ring wptr %u\n", r_wptr);
2083         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2084         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2085         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2086         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2087         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2088          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2089         seq_printf(m, "Ring fifo:\n");
2090         for (i = 0; i < 256; i++) {
2091                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2092                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2093                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2094         }
2095         seq_printf(m, "Indirect1 fifo:\n");
2096         for (i = 256; i <= 512; i++) {
2097                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2098                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2099                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2100         }
2101         seq_printf(m, "Indirect2 fifo:\n");
2102         for (i = 640; i < ib1_wptr; i++) {
2103                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2104                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2105                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2106         }
2107         return 0;
2108 }
2109
2110 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2111 {
2112         struct drm_info_node *node = (struct drm_info_node *) m->private;
2113         struct drm_device *dev = node->minor->dev;
2114         struct radeon_device *rdev = dev->dev_private;
2115         uint32_t tmp;
2116
2117         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2118         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2119         tmp = RREG32(RADEON_MC_FB_LOCATION);
2120         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2121         tmp = RREG32(RADEON_BUS_CNTL);
2122         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2123         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2124         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2125         tmp = RREG32(RADEON_AGP_BASE);
2126         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2127         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2128         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2129         tmp = RREG32(0x01D0);
2130         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2131         tmp = RREG32(RADEON_AIC_LO_ADDR);
2132         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2133         tmp = RREG32(RADEON_AIC_HI_ADDR);
2134         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2135         tmp = RREG32(0x01E4);
2136         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2137         return 0;
2138 }
2139
2140 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2141         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2142 };
2143
2144 static struct drm_info_list r100_debugfs_cp_list[] = {
2145         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2146         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2147 };
2148
2149 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2150         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2151 };
2152 #endif
2153
2154 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2155 {
2156 #if defined(CONFIG_DEBUG_FS)
2157         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2158 #else
2159         return 0;
2160 #endif
2161 }
2162
2163 int r100_debugfs_cp_init(struct radeon_device *rdev)
2164 {
2165 #if defined(CONFIG_DEBUG_FS)
2166         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2167 #else
2168         return 0;
2169 #endif
2170 }
2171
2172 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2173 {
2174 #if defined(CONFIG_DEBUG_FS)
2175         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2176 #else
2177         return 0;
2178 #endif
2179 }
2180
2181 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2182                          uint32_t tiling_flags, uint32_t pitch,
2183                          uint32_t offset, uint32_t obj_size)
2184 {
2185         int surf_index = reg * 16;
2186         int flags = 0;
2187
2188         /* r100/r200 divide by 16 */
2189         if (rdev->family < CHIP_R300)
2190                 flags = pitch / 16;
2191         else
2192                 flags = pitch / 8;
2193
2194         if (rdev->family <= CHIP_RS200) {
2195                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2196                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2197                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2198                 if (tiling_flags & RADEON_TILING_MACRO)
2199                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2200         } else if (rdev->family <= CHIP_RV280) {
2201                 if (tiling_flags & (RADEON_TILING_MACRO))
2202                         flags |= R200_SURF_TILE_COLOR_MACRO;
2203                 if (tiling_flags & RADEON_TILING_MICRO)
2204                         flags |= R200_SURF_TILE_COLOR_MICRO;
2205         } else {
2206                 if (tiling_flags & RADEON_TILING_MACRO)
2207                         flags |= R300_SURF_TILE_MACRO;
2208                 if (tiling_flags & RADEON_TILING_MICRO)
2209                         flags |= R300_SURF_TILE_MICRO;
2210         }
2211
2212         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2213                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2214         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2215                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2216
2217         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2218         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2219         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2220         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2221         return 0;
2222 }
2223
2224 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2225 {
2226         int surf_index = reg * 16;
2227         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2228 }
2229
2230 void r100_bandwidth_update(struct radeon_device *rdev)
2231 {
2232         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2233         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2234         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2235         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2236         fixed20_12 memtcas_ff[8] = {
2237                 fixed_init(1),
2238                 fixed_init(2),
2239                 fixed_init(3),
2240                 fixed_init(0),
2241                 fixed_init_half(1),
2242                 fixed_init_half(2),
2243                 fixed_init(0),
2244         };
2245         fixed20_12 memtcas_rs480_ff[8] = {
2246                 fixed_init(0),
2247                 fixed_init(1),
2248                 fixed_init(2),
2249                 fixed_init(3),
2250                 fixed_init(0),
2251                 fixed_init_half(1),
2252                 fixed_init_half(2),
2253                 fixed_init_half(3),
2254         };
2255         fixed20_12 memtcas2_ff[8] = {
2256                 fixed_init(0),
2257                 fixed_init(1),
2258                 fixed_init(2),
2259                 fixed_init(3),
2260                 fixed_init(4),
2261                 fixed_init(5),
2262                 fixed_init(6),
2263                 fixed_init(7),
2264         };
2265         fixed20_12 memtrbs[8] = {
2266                 fixed_init(1),
2267                 fixed_init_half(1),
2268                 fixed_init(2),
2269                 fixed_init_half(2),
2270                 fixed_init(3),
2271                 fixed_init_half(3),
2272                 fixed_init(4),
2273                 fixed_init_half(4)
2274         };
2275         fixed20_12 memtrbs_r4xx[8] = {
2276                 fixed_init(4),
2277                 fixed_init(5),
2278                 fixed_init(6),
2279                 fixed_init(7),
2280                 fixed_init(8),
2281                 fixed_init(9),
2282                 fixed_init(10),
2283                 fixed_init(11)
2284         };
2285         fixed20_12 min_mem_eff;
2286         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2287         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2288         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2289                 disp_drain_rate2, read_return_rate;
2290         fixed20_12 time_disp1_drop_priority;
2291         int c;
2292         int cur_size = 16;       /* in octawords */
2293         int critical_point = 0, critical_point2;
2294 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2295         int stop_req, max_stop_req;
2296         struct drm_display_mode *mode1 = NULL;
2297         struct drm_display_mode *mode2 = NULL;
2298         uint32_t pixel_bytes1 = 0;
2299         uint32_t pixel_bytes2 = 0;
2300
2301         if (rdev->mode_info.crtcs[0]->base.enabled) {
2302                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2303                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2304         }
2305         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2306                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2307                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2308                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2309                 }
2310         }
2311
2312         min_mem_eff.full = rfixed_const_8(0);
2313         /* get modes */
2314         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2315                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2316                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2317                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2318                 /* check crtc enables */
2319                 if (mode2)
2320                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2321                 if (mode1)
2322                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2323                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2324         }
2325
2326         /*
2327          * determine is there is enough bw for current mode
2328          */
2329         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2330         temp_ff.full = rfixed_const(100);
2331         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2332         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2333         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2334
2335         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2336         temp_ff.full = rfixed_const(temp);
2337         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2338
2339         pix_clk.full = 0;
2340         pix_clk2.full = 0;
2341         peak_disp_bw.full = 0;
2342         if (mode1) {
2343                 temp_ff.full = rfixed_const(1000);
2344                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2345                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2346                 temp_ff.full = rfixed_const(pixel_bytes1);
2347                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2348         }
2349         if (mode2) {
2350                 temp_ff.full = rfixed_const(1000);
2351                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2352                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2353                 temp_ff.full = rfixed_const(pixel_bytes2);
2354                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2355         }
2356
2357         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2358         if (peak_disp_bw.full >= mem_bw.full) {
2359                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2360                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2361         }
2362
2363         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2364         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2365         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2366                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2367                 mem_trp  = ((temp & 0x3)) + 1;
2368                 mem_tras = ((temp & 0x70) >> 4) + 1;
2369         } else if (rdev->family == CHIP_R300 ||
2370                    rdev->family == CHIP_R350) { /* r300, r350 */
2371                 mem_trcd = (temp & 0x7) + 1;
2372                 mem_trp = ((temp >> 8) & 0x7) + 1;
2373                 mem_tras = ((temp >> 11) & 0xf) + 4;
2374         } else if (rdev->family == CHIP_RV350 ||
2375                    rdev->family <= CHIP_RV380) {
2376                 /* rv3x0 */
2377                 mem_trcd = (temp & 0x7) + 3;
2378                 mem_trp = ((temp >> 8) & 0x7) + 3;
2379                 mem_tras = ((temp >> 11) & 0xf) + 6;
2380         } else if (rdev->family == CHIP_R420 ||
2381                    rdev->family == CHIP_R423 ||
2382                    rdev->family == CHIP_RV410) {
2383                 /* r4xx */
2384                 mem_trcd = (temp & 0xf) + 3;
2385                 if (mem_trcd > 15)
2386                         mem_trcd = 15;
2387                 mem_trp = ((temp >> 8) & 0xf) + 3;
2388                 if (mem_trp > 15)
2389                         mem_trp = 15;
2390                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2391                 if (mem_tras > 31)
2392                         mem_tras = 31;
2393         } else { /* RV200, R200 */
2394                 mem_trcd = (temp & 0x7) + 1;
2395                 mem_trp = ((temp >> 8) & 0x7) + 1;
2396                 mem_tras = ((temp >> 12) & 0xf) + 4;
2397         }
2398         /* convert to FF */
2399         trcd_ff.full = rfixed_const(mem_trcd);
2400         trp_ff.full = rfixed_const(mem_trp);
2401         tras_ff.full = rfixed_const(mem_tras);
2402
2403         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2404         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2405         data = (temp & (7 << 20)) >> 20;
2406         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2407                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2408                         tcas_ff = memtcas_rs480_ff[data];
2409                 else
2410                         tcas_ff = memtcas_ff[data];
2411         } else
2412                 tcas_ff = memtcas2_ff[data];
2413
2414         if (rdev->family == CHIP_RS400 ||
2415             rdev->family == CHIP_RS480) {
2416                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2417                 data = (temp >> 23) & 0x7;
2418                 if (data < 5)
2419                         tcas_ff.full += rfixed_const(data);
2420         }
2421
2422         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2423                 /* on the R300, Tcas is included in Trbs.
2424                  */
2425                 temp = RREG32(RADEON_MEM_CNTL);
2426                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2427                 if (data == 1) {
2428                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2429                                 temp = RREG32(R300_MC_IND_INDEX);
2430                                 temp &= ~R300_MC_IND_ADDR_MASK;
2431                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2432                                 WREG32(R300_MC_IND_INDEX, temp);
2433                                 temp = RREG32(R300_MC_IND_DATA);
2434                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2435                         } else {
2436                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2437                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2438                         }
2439                 } else {
2440                         temp = RREG32(R300_MC_READ_CNTL_AB);
2441                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2442                 }
2443                 if (rdev->family == CHIP_RV410 ||
2444                     rdev->family == CHIP_R420 ||
2445                     rdev->family == CHIP_R423)
2446                         trbs_ff = memtrbs_r4xx[data];
2447                 else
2448                         trbs_ff = memtrbs[data];
2449                 tcas_ff.full += trbs_ff.full;
2450         }
2451
2452         sclk_eff_ff.full = sclk_ff.full;
2453
2454         if (rdev->flags & RADEON_IS_AGP) {
2455                 fixed20_12 agpmode_ff;
2456                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2457                 temp_ff.full = rfixed_const_666(16);
2458                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2459         }
2460         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2461
2462         if (ASIC_IS_R300(rdev)) {
2463                 sclk_delay_ff.full = rfixed_const(250);
2464         } else {
2465                 if ((rdev->family == CHIP_RV100) ||
2466                     rdev->flags & RADEON_IS_IGP) {
2467                         if (rdev->mc.vram_is_ddr)
2468                                 sclk_delay_ff.full = rfixed_const(41);
2469                         else
2470                                 sclk_delay_ff.full = rfixed_const(33);
2471                 } else {
2472                         if (rdev->mc.vram_width == 128)
2473                                 sclk_delay_ff.full = rfixed_const(57);
2474                         else
2475                                 sclk_delay_ff.full = rfixed_const(41);
2476                 }
2477         }
2478
2479         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2480
2481         if (rdev->mc.vram_is_ddr) {
2482                 if (rdev->mc.vram_width == 32) {
2483                         k1.full = rfixed_const(40);
2484                         c  = 3;
2485                 } else {
2486                         k1.full = rfixed_const(20);
2487                         c  = 1;
2488                 }
2489         } else {
2490                 k1.full = rfixed_const(40);
2491                 c  = 3;
2492         }
2493
2494         temp_ff.full = rfixed_const(2);
2495         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2496         temp_ff.full = rfixed_const(c);
2497         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2498         temp_ff.full = rfixed_const(4);
2499         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2500         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2501         mc_latency_mclk.full += k1.full;
2502
2503         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2504         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2505
2506         /*
2507           HW cursor time assuming worst case of full size colour cursor.
2508         */
2509         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2510         temp_ff.full += trcd_ff.full;
2511         if (temp_ff.full < tras_ff.full)
2512                 temp_ff.full = tras_ff.full;
2513         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2514
2515         temp_ff.full = rfixed_const(cur_size);
2516         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2517         /*
2518           Find the total latency for the display data.
2519         */
2520         disp_latency_overhead.full = rfixed_const(8);
2521         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2522         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2523         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2524
2525         if (mc_latency_mclk.full > mc_latency_sclk.full)
2526                 disp_latency.full = mc_latency_mclk.full;
2527         else
2528                 disp_latency.full = mc_latency_sclk.full;
2529
2530         /* setup Max GRPH_STOP_REQ default value */
2531         if (ASIC_IS_RV100(rdev))
2532                 max_stop_req = 0x5c;
2533         else
2534                 max_stop_req = 0x7c;
2535
2536         if (mode1) {
2537                 /*  CRTC1
2538                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2539                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2540                 */
2541                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2542
2543                 if (stop_req > max_stop_req)
2544                         stop_req = max_stop_req;
2545
2546                 /*
2547                   Find the drain rate of the display buffer.
2548                 */
2549                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2550                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2551
2552                 /*
2553                   Find the critical point of the display buffer.
2554                 */
2555                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2556                 crit_point_ff.full += rfixed_const_half(0);
2557
2558                 critical_point = rfixed_trunc(crit_point_ff);
2559
2560                 if (rdev->disp_priority == 2) {
2561                         critical_point = 0;
2562                 }
2563
2564                 /*
2565                   The critical point should never be above max_stop_req-4.  Setting
2566                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2567                 */
2568                 if (max_stop_req - critical_point < 4)
2569                         critical_point = 0;
2570
2571                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2572                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2573                         critical_point = 0x10;
2574                 }
2575
2576                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2577                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2578                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2579                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2580                 if ((rdev->family == CHIP_R350) &&
2581                     (stop_req > 0x15)) {
2582                         stop_req -= 0x10;
2583                 }
2584                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2585                 temp |= RADEON_GRPH_BUFFER_SIZE;
2586                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2587                           RADEON_GRPH_CRITICAL_AT_SOF |
2588                           RADEON_GRPH_STOP_CNTL);
2589                 /*
2590                   Write the result into the register.
2591                 */
2592                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2593                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2594
2595 #if 0
2596                 if ((rdev->family == CHIP_RS400) ||
2597                     (rdev->family == CHIP_RS480)) {
2598                         /* attempt to program RS400 disp regs correctly ??? */
2599                         temp = RREG32(RS400_DISP1_REG_CNTL);
2600                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2601                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2602                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2603                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2604                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2605                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2606                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2607                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2608                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2609                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2610                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2611                 }
2612 #endif
2613
2614                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2615                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2616                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2617         }
2618
2619         if (mode2) {
2620                 u32 grph2_cntl;
2621                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2622
2623                 if (stop_req > max_stop_req)
2624                         stop_req = max_stop_req;
2625
2626                 /*
2627                   Find the drain rate of the display buffer.
2628                 */
2629                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2630                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2631
2632                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2633                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2634                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2635                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2636                 if ((rdev->family == CHIP_R350) &&
2637                     (stop_req > 0x15)) {
2638                         stop_req -= 0x10;
2639                 }
2640                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2641                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2642                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2643                           RADEON_GRPH_CRITICAL_AT_SOF |
2644                           RADEON_GRPH_STOP_CNTL);
2645
2646                 if ((rdev->family == CHIP_RS100) ||
2647                     (rdev->family == CHIP_RS200))
2648                         critical_point2 = 0;
2649                 else {
2650                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2651                         temp_ff.full = rfixed_const(temp);
2652                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2653                         if (sclk_ff.full < temp_ff.full)
2654                                 temp_ff.full = sclk_ff.full;
2655
2656                         read_return_rate.full = temp_ff.full;
2657
2658                         if (mode1) {
2659                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2660                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2661                         } else {
2662                                 time_disp1_drop_priority.full = 0;
2663                         }
2664                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2665                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2666                         crit_point_ff.full += rfixed_const_half(0);
2667
2668                         critical_point2 = rfixed_trunc(crit_point_ff);
2669
2670                         if (rdev->disp_priority == 2) {
2671                                 critical_point2 = 0;
2672                         }
2673
2674                         if (max_stop_req - critical_point2 < 4)
2675                                 critical_point2 = 0;
2676
2677                 }
2678
2679                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2680                         /* some R300 cards have problem with this set to 0 */
2681                         critical_point2 = 0x10;
2682                 }
2683
2684                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2685                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2686
2687                 if ((rdev->family == CHIP_RS400) ||
2688                     (rdev->family == CHIP_RS480)) {
2689 #if 0
2690                         /* attempt to program RS400 disp2 regs correctly ??? */
2691                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2692                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2693                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2694                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2695                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2696                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2697                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2698                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2699                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2700                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2701                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2702                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2703 #endif
2704                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2705                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2706                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2707                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2708                 }
2709
2710                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2711                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2712         }
2713 }
2714
2715 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2716 {
2717         DRM_ERROR("pitch                      %d\n", t->pitch);
2718         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2719         DRM_ERROR("width                      %d\n", t->width);
2720         DRM_ERROR("width_11                   %d\n", t->width_11);
2721         DRM_ERROR("height                     %d\n", t->height);
2722         DRM_ERROR("height_11                  %d\n", t->height_11);
2723         DRM_ERROR("num levels                 %d\n", t->num_levels);
2724         DRM_ERROR("depth                      %d\n", t->txdepth);
2725         DRM_ERROR("bpp                        %d\n", t->cpp);
2726         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2727         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2728         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2729 }
2730
2731 static int r100_cs_track_cube(struct radeon_device *rdev,
2732                               struct r100_cs_track *track, unsigned idx)
2733 {
2734         unsigned face, w, h;
2735         struct radeon_bo *cube_robj;
2736         unsigned long size;
2737
2738         for (face = 0; face < 5; face++) {
2739                 cube_robj = track->textures[idx].cube_info[face].robj;
2740                 w = track->textures[idx].cube_info[face].width;
2741                 h = track->textures[idx].cube_info[face].height;
2742
2743                 size = w * h;
2744                 size *= track->textures[idx].cpp;
2745
2746                 size += track->textures[idx].cube_info[face].offset;
2747
2748                 if (size > radeon_bo_size(cube_robj)) {
2749                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2750                                   size, radeon_bo_size(cube_robj));
2751                         r100_cs_track_texture_print(&track->textures[idx]);
2752                         return -1;
2753                 }
2754         }
2755         return 0;
2756 }
2757
2758 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2759                                        struct r100_cs_track *track)
2760 {
2761         struct radeon_bo *robj;
2762         unsigned long size;
2763         unsigned u, i, w, h;
2764         int ret;
2765
2766         for (u = 0; u < track->num_texture; u++) {
2767                 if (!track->textures[u].enabled)
2768                         continue;
2769                 robj = track->textures[u].robj;
2770                 if (robj == NULL) {
2771                         DRM_ERROR("No texture bound to unit %u\n", u);
2772                         return -EINVAL;
2773                 }
2774                 size = 0;
2775                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2776                         if (track->textures[u].use_pitch) {
2777                                 if (rdev->family < CHIP_R300)
2778                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2779                                 else
2780                                         w = track->textures[u].pitch / (1 << i);
2781                         } else {
2782                                 w = track->textures[u].width;
2783                                 if (rdev->family >= CHIP_RV515)
2784                                         w |= track->textures[u].width_11;
2785                                 w = w / (1 << i);
2786                                 if (track->textures[u].roundup_w)
2787                                         w = roundup_pow_of_two(w);
2788                         }
2789                         h = track->textures[u].height;
2790                         if (rdev->family >= CHIP_RV515)
2791                                 h |= track->textures[u].height_11;
2792                         h = h / (1 << i);
2793                         if (track->textures[u].roundup_h)
2794                                 h = roundup_pow_of_two(h);
2795                         size += w * h;
2796                 }
2797                 size *= track->textures[u].cpp;
2798                 switch (track->textures[u].tex_coord_type) {
2799                 case 0:
2800                         break;
2801                 case 1:
2802                         size *= (1 << track->textures[u].txdepth);
2803                         break;
2804                 case 2:
2805                         if (track->separate_cube) {
2806                                 ret = r100_cs_track_cube(rdev, track, u);
2807                                 if (ret)
2808                                         return ret;
2809                         } else
2810                                 size *= 6;
2811                         break;
2812                 default:
2813                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2814                                   "%u\n", track->textures[u].tex_coord_type, u);
2815                         return -EINVAL;
2816                 }
2817                 if (size > radeon_bo_size(robj)) {
2818                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2819                                   "%lu\n", u, size, radeon_bo_size(robj));
2820                         r100_cs_track_texture_print(&track->textures[u]);
2821                         return -EINVAL;
2822                 }
2823         }
2824         return 0;
2825 }
2826
2827 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2828 {
2829         unsigned i;
2830         unsigned long size;
2831         unsigned prim_walk;
2832         unsigned nverts;
2833
2834         for (i = 0; i < track->num_cb; i++) {
2835                 if (track->cb[i].robj == NULL) {
2836                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2837                         return -EINVAL;
2838                 }
2839                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2840                 size += track->cb[i].offset;
2841                 if (size > radeon_bo_size(track->cb[i].robj)) {
2842                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2843                                   "(need %lu have %lu) !\n", i, size,
2844                                   radeon_bo_size(track->cb[i].robj));
2845                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2846                                   i, track->cb[i].pitch, track->cb[i].cpp,
2847                                   track->cb[i].offset, track->maxy);
2848                         return -EINVAL;
2849                 }
2850         }
2851         if (track->z_enabled) {
2852                 if (track->zb.robj == NULL) {
2853                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2854                         return -EINVAL;
2855                 }
2856                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2857                 size += track->zb.offset;
2858                 if (size > radeon_bo_size(track->zb.robj)) {
2859                         DRM_ERROR("[drm] Buffer too small for z buffer "
2860                                   "(need %lu have %lu) !\n", size,
2861                                   radeon_bo_size(track->zb.robj));
2862                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2863                                   track->zb.pitch, track->zb.cpp,
2864                                   track->zb.offset, track->maxy);
2865                         return -EINVAL;
2866                 }
2867         }
2868         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2869         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2870         switch (prim_walk) {
2871         case 1:
2872                 for (i = 0; i < track->num_arrays; i++) {
2873                         size = track->arrays[i].esize * track->max_indx * 4;
2874                         if (track->arrays[i].robj == NULL) {
2875                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2876                                           "bound\n", prim_walk, i);
2877                                 return -EINVAL;
2878                         }
2879                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2880                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2881                                         "need %lu dwords have %lu dwords\n",
2882                                         prim_walk, i, size >> 2,
2883                                         radeon_bo_size(track->arrays[i].robj)
2884                                         >> 2);
2885                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2886                                 return -EINVAL;
2887                         }
2888                 }
2889                 break;
2890         case 2:
2891                 for (i = 0; i < track->num_arrays; i++) {
2892                         size = track->arrays[i].esize * (nverts - 1) * 4;
2893                         if (track->arrays[i].robj == NULL) {
2894                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2895                                           "bound\n", prim_walk, i);
2896                                 return -EINVAL;
2897                         }
2898                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2899                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2900                                         "need %lu dwords have %lu dwords\n",
2901                                         prim_walk, i, size >> 2,
2902                                         radeon_bo_size(track->arrays[i].robj)
2903                                         >> 2);
2904                                 return -EINVAL;
2905                         }
2906                 }
2907                 break;
2908         case 3:
2909                 size = track->vtx_size * nverts;
2910                 if (size != track->immd_dwords) {
2911                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2912                                   track->immd_dwords, size);
2913                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2914                                   nverts, track->vtx_size);
2915                         return -EINVAL;
2916                 }
2917                 break;
2918         default:
2919                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2920                           prim_walk);
2921                 return -EINVAL;
2922         }
2923         return r100_cs_track_texture_check(rdev, track);
2924 }
2925
2926 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2927 {
2928         unsigned i, face;
2929
2930         if (rdev->family < CHIP_R300) {
2931                 track->num_cb = 1;
2932                 if (rdev->family <= CHIP_RS200)
2933                         track->num_texture = 3;
2934                 else
2935                         track->num_texture = 6;
2936                 track->maxy = 2048;
2937                 track->separate_cube = 1;
2938         } else {
2939                 track->num_cb = 4;
2940                 track->num_texture = 16;
2941                 track->maxy = 4096;
2942                 track->separate_cube = 0;
2943         }
2944
2945         for (i = 0; i < track->num_cb; i++) {
2946                 track->cb[i].robj = NULL;
2947                 track->cb[i].pitch = 8192;
2948                 track->cb[i].cpp = 16;
2949                 track->cb[i].offset = 0;
2950         }
2951         track->z_enabled = true;
2952         track->zb.robj = NULL;
2953         track->zb.pitch = 8192;
2954         track->zb.cpp = 4;
2955         track->zb.offset = 0;
2956         track->vtx_size = 0x7F;
2957         track->immd_dwords = 0xFFFFFFFFUL;
2958         track->num_arrays = 11;
2959         track->max_indx = 0x00FFFFFFUL;
2960         for (i = 0; i < track->num_arrays; i++) {
2961                 track->arrays[i].robj = NULL;
2962                 track->arrays[i].esize = 0x7F;
2963         }
2964         for (i = 0; i < track->num_texture; i++) {
2965                 track->textures[i].pitch = 16536;
2966                 track->textures[i].width = 16536;
2967                 track->textures[i].height = 16536;
2968                 track->textures[i].width_11 = 1 << 11;
2969                 track->textures[i].height_11 = 1 << 11;
2970                 track->textures[i].num_levels = 12;
2971                 if (rdev->family <= CHIP_RS200) {
2972                         track->textures[i].tex_coord_type = 0;
2973                         track->textures[i].txdepth = 0;
2974                 } else {
2975                         track->textures[i].txdepth = 16;
2976                         track->textures[i].tex_coord_type = 1;
2977                 }
2978                 track->textures[i].cpp = 64;
2979                 track->textures[i].robj = NULL;
2980                 /* CS IB emission code makes sure texture unit are disabled */
2981                 track->textures[i].enabled = false;
2982                 track->textures[i].roundup_w = true;
2983                 track->textures[i].roundup_h = true;
2984                 if (track->separate_cube)
2985                         for (face = 0; face < 5; face++) {
2986                                 track->textures[i].cube_info[face].robj = NULL;
2987                                 track->textures[i].cube_info[face].width = 16536;
2988                                 track->textures[i].cube_info[face].height = 16536;
2989                                 track->textures[i].cube_info[face].offset = 0;
2990                         }
2991         }
2992 }
2993
2994 int r100_ring_test(struct radeon_device *rdev)
2995 {
2996         uint32_t scratch;
2997         uint32_t tmp = 0;
2998         unsigned i;
2999         int r;
3000
3001         r = radeon_scratch_get(rdev, &scratch);
3002         if (r) {
3003                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3004                 return r;
3005         }
3006         WREG32(scratch, 0xCAFEDEAD);
3007         r = radeon_ring_lock(rdev, 2);
3008         if (r) {
3009                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3010                 radeon_scratch_free(rdev, scratch);
3011                 return r;
3012         }
3013         radeon_ring_write(rdev, PACKET0(scratch, 0));
3014         radeon_ring_write(rdev, 0xDEADBEEF);
3015         radeon_ring_unlock_commit(rdev);
3016         for (i = 0; i < rdev->usec_timeout; i++) {
3017                 tmp = RREG32(scratch);
3018                 if (tmp == 0xDEADBEEF) {
3019                         break;
3020                 }
3021                 DRM_UDELAY(1);
3022         }
3023         if (i < rdev->usec_timeout) {
3024                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3025         } else {
3026                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3027                           scratch, tmp);
3028                 r = -EINVAL;
3029         }
3030         radeon_scratch_free(rdev, scratch);
3031         return r;
3032 }
3033
3034 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3035 {
3036         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3037         radeon_ring_write(rdev, ib->gpu_addr);
3038         radeon_ring_write(rdev, ib->length_dw);
3039 }
3040
3041 int r100_ib_test(struct radeon_device *rdev)
3042 {
3043         struct radeon_ib *ib;
3044         uint32_t scratch;
3045         uint32_t tmp = 0;
3046         unsigned i;
3047         int r;
3048
3049         r = radeon_scratch_get(rdev, &scratch);
3050         if (r) {
3051                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3052                 return r;
3053         }
3054         WREG32(scratch, 0xCAFEDEAD);
3055         r = radeon_ib_get(rdev, &ib);
3056         if (r) {
3057                 return r;
3058         }
3059         ib->ptr[0] = PACKET0(scratch, 0);
3060         ib->ptr[1] = 0xDEADBEEF;
3061         ib->ptr[2] = PACKET2(0);
3062         ib->ptr[3] = PACKET2(0);
3063         ib->ptr[4] = PACKET2(0);
3064         ib->ptr[5] = PACKET2(0);
3065         ib->ptr[6] = PACKET2(0);
3066         ib->ptr[7] = PACKET2(0);
3067         ib->length_dw = 8;
3068         r = radeon_ib_schedule(rdev, ib);
3069         if (r) {
3070                 radeon_scratch_free(rdev, scratch);
3071                 radeon_ib_free(rdev, &ib);
3072                 return r;
3073         }
3074         r = radeon_fence_wait(ib->fence, false);
3075         if (r) {
3076                 return r;
3077         }
3078         for (i = 0; i < rdev->usec_timeout; i++) {
3079                 tmp = RREG32(scratch);
3080                 if (tmp == 0xDEADBEEF) {
3081                         break;
3082                 }
3083                 DRM_UDELAY(1);
3084         }
3085         if (i < rdev->usec_timeout) {
3086                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3087         } else {
3088                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3089                           scratch, tmp);
3090                 r = -EINVAL;
3091         }
3092         radeon_scratch_free(rdev, scratch);
3093         radeon_ib_free(rdev, &ib);
3094         return r;
3095 }
3096
3097 void r100_ib_fini(struct radeon_device *rdev)
3098 {
3099         radeon_ib_pool_fini(rdev);
3100 }
3101
3102 int r100_ib_init(struct radeon_device *rdev)
3103 {
3104         int r;
3105
3106         r = radeon_ib_pool_init(rdev);
3107         if (r) {
3108                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3109                 r100_ib_fini(rdev);
3110                 return r;
3111         }
3112         r = r100_ib_test(rdev);
3113         if (r) {
3114                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3115                 r100_ib_fini(rdev);
3116                 return r;
3117         }
3118         return 0;
3119 }
3120
3121 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3122 {
3123         /* Shutdown CP we shouldn't need to do that but better be safe than
3124          * sorry
3125          */
3126         rdev->cp.ready = false;
3127         WREG32(R_000740_CP_CSQ_CNTL, 0);
3128
3129         /* Save few CRTC registers */
3130         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3131         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3132         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3133         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3134         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3135                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3136                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3137         }
3138
3139         /* Disable VGA aperture access */
3140         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3141         /* Disable cursor, overlay, crtc */
3142         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3143         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3144                                         S_000054_CRTC_DISPLAY_DIS(1));
3145         WREG32(R_000050_CRTC_GEN_CNTL,
3146                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3147                         S_000050_CRTC_DISP_REQ_EN_B(1));
3148         WREG32(R_000420_OV0_SCALE_CNTL,
3149                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3150         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3151         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3152                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3153                                                 S_000360_CUR2_LOCK(1));
3154                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3155                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3156                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3157                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3158                 WREG32(R_000360_CUR2_OFFSET,
3159                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3160         }
3161 }
3162
3163 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3164 {
3165         /* Update base address for crtc */
3166         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3167         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3168                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3169                                 rdev->mc.vram_location);
3170         }
3171         /* Restore CRTC registers */
3172         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3173         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3174         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3175         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3176                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3177         }
3178 }
3179
3180 void r100_vga_render_disable(struct radeon_device *rdev)
3181 {
3182         u32 tmp;
3183
3184         tmp = RREG8(R_0003C2_GENMO_WT);
3185         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3186 }
3187
3188 static void r100_debugfs(struct radeon_device *rdev)
3189 {
3190         int r;
3191
3192         r = r100_debugfs_mc_info_init(rdev);
3193         if (r)
3194                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3195 }
3196
3197 static void r100_mc_program(struct radeon_device *rdev)
3198 {
3199         struct r100_mc_save save;
3200
3201         /* Stops all mc clients */
3202         r100_mc_stop(rdev, &save);
3203         if (rdev->flags & RADEON_IS_AGP) {
3204                 WREG32(R_00014C_MC_AGP_LOCATION,
3205                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3206                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3207                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3208                 if (rdev->family > CHIP_RV200)
3209                         WREG32(R_00015C_AGP_BASE_2,
3210                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3211         } else {
3212                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3213                 WREG32(R_000170_AGP_BASE, 0);
3214                 if (rdev->family > CHIP_RV200)
3215                         WREG32(R_00015C_AGP_BASE_2, 0);
3216         }
3217         /* Wait for mc idle */
3218         if (r100_mc_wait_for_idle(rdev))
3219                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3220         /* Program MC, should be a 32bits limited address space */
3221         WREG32(R_000148_MC_FB_LOCATION,
3222                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3223                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3224         r100_mc_resume(rdev, &save);
3225 }
3226
3227 void r100_clock_startup(struct radeon_device *rdev)
3228 {
3229         u32 tmp;
3230
3231         if (radeon_dynclks != -1 && radeon_dynclks)
3232                 radeon_legacy_set_clock_gating(rdev, 1);
3233         /* We need to force on some of the block */
3234         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3235         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3236         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3237                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3238         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3239 }
3240
3241 static int r100_startup(struct radeon_device *rdev)
3242 {
3243         int r;
3244
3245         /* set common regs */
3246         r100_set_common_regs(rdev);
3247         /* program mc */
3248         r100_mc_program(rdev);
3249         /* Resume clock */
3250         r100_clock_startup(rdev);
3251         /* Initialize GPU configuration (# pipes, ...) */
3252         r100_gpu_init(rdev);
3253         /* Initialize GART (initialize after TTM so we can allocate
3254          * memory through TTM but finalize after TTM) */
3255         r100_enable_bm(rdev);
3256         if (rdev->flags & RADEON_IS_PCI) {
3257                 r = r100_pci_gart_enable(rdev);
3258                 if (r)
3259                         return r;
3260         }
3261         /* Enable IRQ */
3262         r100_irq_set(rdev);
3263         /* 1M ring buffer */
3264         r = r100_cp_init(rdev, 1024 * 1024);
3265         if (r) {
3266                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3267                 return r;
3268         }
3269         r = r100_wb_init(rdev);
3270         if (r)
3271                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3272         r = r100_ib_init(rdev);
3273         if (r) {
3274                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3275                 return r;
3276         }
3277         return 0;
3278 }
3279
3280 int r100_resume(struct radeon_device *rdev)
3281 {
3282         /* Make sur GART are not working */
3283         if (rdev->flags & RADEON_IS_PCI)
3284                 r100_pci_gart_disable(rdev);
3285         /* Resume clock before doing reset */
3286         r100_clock_startup(rdev);
3287         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3288         if (radeon_gpu_reset(rdev)) {
3289                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3290                         RREG32(R_000E40_RBBM_STATUS),
3291                         RREG32(R_0007C0_CP_STAT));
3292         }
3293         /* post */
3294         radeon_combios_asic_init(rdev->ddev);
3295         /* Resume clock after posting */
3296         r100_clock_startup(rdev);
3297         return r100_startup(rdev);
3298 }
3299
3300 int r100_suspend(struct radeon_device *rdev)
3301 {
3302         r100_cp_disable(rdev);
3303         r100_wb_disable(rdev);
3304         r100_irq_disable(rdev);
3305         if (rdev->flags & RADEON_IS_PCI)
3306                 r100_pci_gart_disable(rdev);
3307         return 0;
3308 }
3309
3310 void r100_fini(struct radeon_device *rdev)
3311 {
3312         r100_suspend(rdev);
3313         r100_cp_fini(rdev);
3314         r100_wb_fini(rdev);
3315         r100_ib_fini(rdev);
3316         radeon_gem_fini(rdev);
3317         if (rdev->flags & RADEON_IS_PCI)
3318                 r100_pci_gart_fini(rdev);
3319         radeon_irq_kms_fini(rdev);
3320         radeon_fence_driver_fini(rdev);
3321         radeon_bo_fini(rdev);
3322         radeon_atombios_fini(rdev);
3323         kfree(rdev->bios);
3324         rdev->bios = NULL;
3325 }
3326
3327 int r100_mc_init(struct radeon_device *rdev)
3328 {
3329         int r;
3330         u32 tmp;
3331
3332         /* Setup GPU memory space */
3333         rdev->mc.vram_location = 0xFFFFFFFFUL;
3334         rdev->mc.gtt_location = 0xFFFFFFFFUL;
3335         if (rdev->flags & RADEON_IS_IGP) {
3336                 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3337                 rdev->mc.vram_location = tmp << 16;
3338         }
3339         if (rdev->flags & RADEON_IS_AGP) {
3340                 r = radeon_agp_init(rdev);
3341                 if (r) {
3342                         printk(KERN_WARNING "[drm] Disabling AGP\n");
3343                         rdev->flags &= ~RADEON_IS_AGP;
3344                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3345                 } else {
3346                         rdev->mc.gtt_location = rdev->mc.agp_base;
3347                 }
3348         }
3349         r = radeon_mc_setup(rdev);
3350         if (r)
3351                 return r;
3352         return 0;
3353 }
3354
3355 int r100_init(struct radeon_device *rdev)
3356 {
3357         int r;
3358
3359         /* Register debugfs file specific to this group of asics */
3360         r100_debugfs(rdev);
3361         /* Disable VGA */
3362         r100_vga_render_disable(rdev);
3363         /* Initialize scratch registers */
3364         radeon_scratch_init(rdev);
3365         /* Initialize surface registers */
3366         radeon_surface_init(rdev);
3367         /* TODO: disable VGA need to use VGA request */
3368         /* BIOS*/
3369         if (!radeon_get_bios(rdev)) {
3370                 if (ASIC_IS_AVIVO(rdev))
3371                         return -EINVAL;
3372         }
3373         if (rdev->is_atom_bios) {
3374                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3375                 return -EINVAL;
3376         } else {
3377                 r = radeon_combios_init(rdev);
3378                 if (r)
3379                         return r;
3380         }
3381         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3382         if (radeon_gpu_reset(rdev)) {
3383                 dev_warn(rdev->dev,
3384                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3385                         RREG32(R_000E40_RBBM_STATUS),
3386                         RREG32(R_0007C0_CP_STAT));
3387         }
3388         /* check if cards are posted or not */
3389         if (radeon_boot_test_post_card(rdev) == false)
3390                 return -EINVAL;
3391         /* Set asic errata */
3392         r100_errata(rdev);
3393         /* Initialize clocks */
3394         radeon_get_clock_info(rdev->ddev);
3395         /* Get vram informations */
3396         r100_vram_info(rdev);
3397         /* Initialize memory controller (also test AGP) */
3398         r = r100_mc_init(rdev);
3399         if (r)
3400                 return r;
3401         /* Fence driver */
3402         r = radeon_fence_driver_init(rdev);
3403         if (r)
3404                 return r;
3405         r = radeon_irq_kms_init(rdev);
3406         if (r)
3407                 return r;
3408         /* Memory manager */
3409         r = radeon_bo_init(rdev);
3410         if (r)
3411                 return r;
3412         if (rdev->flags & RADEON_IS_PCI) {
3413                 r = r100_pci_gart_init(rdev);
3414                 if (r)
3415                         return r;
3416         }
3417         r100_set_safe_registers(rdev);
3418         rdev->accel_working = true;
3419         r = r100_startup(rdev);
3420         if (r) {
3421                 /* Somethings want wront with the accel init stop accel */
3422                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3423                 r100_suspend(rdev);
3424                 r100_cp_fini(rdev);
3425                 r100_wb_fini(rdev);
3426                 r100_ib_fini(rdev);
3427                 if (rdev->flags & RADEON_IS_PCI)
3428                         r100_pci_gart_fini(rdev);
3429                 radeon_irq_kms_fini(rdev);
3430                 rdev->accel_working = false;
3431         }
3432         return 0;
3433 }