SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_get_power_state(struct radeon_device *rdev,
  72                           enum radeon_pm_action action)
  73 {
  74         int i;
  75         rdev->pm.can_upclock = true;
  76         rdev->pm.can_downclock = true;
  77
  78         switch (action) {
  79         case PM_ACTION_MINIMUM:
  80                 rdev->pm.requested_power_state_index = 0;
  81                 rdev->pm.can_downclock = false;
  82                 break;
  83         case PM_ACTION_DOWNCLOCK:
  84                 if (rdev->pm.current_power_state_index == 0) {
  85                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  86                         rdev->pm.can_downclock = false;
  87                 } else {
  88                         if (rdev->pm.active_crtc_count > 1) {
  89                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  90                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
  91                                                 continue;
  92                                         else if (i >= rdev->pm.current_power_state_index) {
  93                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  94                                                 break;
  95                                         } else {
  96                                                 rdev->pm.requested_power_state_index = i;
  97                                                 break;
  98                                         }
  99                                 }
 100                         } else
 101                                 rdev->pm.requested_power_state_index =
 102                                         rdev->pm.current_power_state_index - 1;
 103                 }
 104                 break;
 105         case PM_ACTION_UPCLOCK:
 106                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 107                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 108                         rdev->pm.can_upclock = false;
 109                 } else {
 110                         if (rdev->pm.active_crtc_count > 1) {
 111                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 112                                         if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 113                                                 continue;
 114                                         else if (i <= rdev->pm.current_power_state_index) {
 115                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 116                                                 break;
 117                                         } else {
 118                                                 rdev->pm.requested_power_state_index = i;
 119                                                 break;
 120                                         }
 121                                 }
 122                         } else
 123                                 rdev->pm.requested_power_state_index =
 124                                         rdev->pm.current_power_state_index + 1;
 125                 }
 126                 break;
 127         case PM_ACTION_DEFAULT:
 128                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 129                 rdev->pm.can_upclock = false;
 130                 break;
 131         case PM_ACTION_NONE:
 132         default:
 133                 DRM_ERROR("Requested mode for not defined action\n");
 134                 return;
 135         }
 136         /* only one clock mode per power state */
 137         rdev->pm.requested_clock_mode_index = 0;
 138
 139         DRM_INFO("Requested: e: %d m: %d p: %d\n",
 140                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 141                  clock_info[rdev->pm.requested_clock_mode_index].sclk,
 142                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 143                  clock_info[rdev->pm.requested_clock_mode_index].mclk,
 144                  rdev->pm.power_state[rdev->pm.requested_power_state_index].
 145                  pcie_lanes);
 146 }
 147
 148 void r100_set_power_state(struct radeon_device *rdev)
 149 {
 150         u32 sclk, mclk;
 151
 152         if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
 153                 return;
 154
 155         if (radeon_gui_idle(rdev)) {
 156
 157                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 159                 if (sclk > rdev->clock.default_sclk)
 160                         sclk = rdev->clock.default_sclk;
 161
 162                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 163                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 164                 if (mclk > rdev->clock.default_mclk)
 165                         mclk = rdev->clock.default_mclk;
 166                 /* don't change the mclk with multiple crtcs */
 167                 if (rdev->pm.active_crtc_count > 1)
 168                         mclk = rdev->clock.default_mclk;
 169
 170                 /* set pcie lanes */
 171                 /* TODO */
 172
 173                 /* set voltage */
 174                 /* TODO */
 175
 176                 /* set engine clock */
 177                 if (sclk != rdev->pm.current_sclk) {
 178                         radeon_sync_with_vblank(rdev);
 179                         radeon_pm_debug_check_in_vbl(rdev, false);
 180                         radeon_set_engine_clock(rdev, sclk);
 181                         radeon_pm_debug_check_in_vbl(rdev, true);
 182                         rdev->pm.current_sclk = sclk;
 183                         DRM_INFO("Setting: e: %d\n", sclk);
 184                 }
 185
 186 #if 0
 187                 /* set memory clock */
 188                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 189                         radeon_sync_with_vblank(rdev);
 190                         radeon_pm_debug_check_in_vbl(rdev, false);
 191                         radeon_set_memory_clock(rdev, mclk);
 192                         radeon_pm_debug_check_in_vbl(rdev, true);
 193                         rdev->pm.current_mclk = mclk;
 194                         DRM_INFO("Setting: m: %d\n", mclk);
 195                 }
 196 #endif
 197
 198                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 199                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 200         } else
 201                 DRM_INFO("GUI not idle!!!\n");
 202 }
 203
 204 void r100_pm_misc(struct radeon_device *rdev)
 205 {
 206 #if 0
 207         int requested_index = rdev->pm.requested_power_state_index;
 208         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 209         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 210         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 211
 212         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 213                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 214                         tmp = RREG32(voltage->gpio.reg);
 215                         if (voltage->active_high)
 216                                 tmp |= voltage->gpio.mask;
 217                         else
 218                                 tmp &= ~(voltage->gpio.mask);
 219                         WREG32(voltage->gpio.reg, tmp);
 220                         if (voltage->delay)
 221                                 udelay(voltage->delay);
 222                 } else {
 223                         tmp = RREG32(voltage->gpio.reg);
 224                         if (voltage->active_high)
 225                                 tmp &= ~voltage->gpio.mask;
 226                         else
 227                                 tmp |= voltage->gpio.mask;
 228                         WREG32(voltage->gpio.reg, tmp);
 229                         if (voltage->delay)
 230                                 udelay(voltage->delay);
 231                 }
 232         }
 233
 234         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 235         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 236         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 237         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 238         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 239         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 240                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 241                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 242                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 243                 else
 244                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 245                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 246                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 247                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 248                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 249         } else
 250                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 251
 252         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 253                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 254                 if (voltage->delay) {
 255                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 256                         switch (voltage->delay) {
 257                         case 33:
 258                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 259                                 break;
 260                         case 66:
 261                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 262                                 break;
 263                         case 99:
 264                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 265                                 break;
 266                         case 132:
 267                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 268                                 break;
 269                         }
 270                 } else
 271                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 272         } else
 273                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 274
 275         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 276                 sclk_cntl &= ~FORCE_HDP;
 277         else
 278                 sclk_cntl |= FORCE_HDP;
 279
 280         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 281         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 282         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 283
 284         /* set pcie lanes */
 285         if ((rdev->flags & RADEON_IS_PCIE) &&
 286             !(rdev->flags & RADEON_IS_IGP) &&
 287             rdev->asic->set_pcie_lanes &&
 288             (ps->pcie_lanes !=
 289              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 290                 radeon_set_pcie_lanes(rdev,
 291                                       ps->pcie_lanes);
 292                 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
 293         }
 294 #endif
 295 }
 296
 297 void r100_pm_prepare(struct radeon_device *rdev)
 298 {
 299         struct drm_device *ddev = rdev->ddev;
 300         struct drm_crtc *crtc;
 301         struct radeon_crtc *radeon_crtc;
 302         u32 tmp;
 303
 304         /* disable any active CRTCs */
 305         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 306                 radeon_crtc = to_radeon_crtc(crtc);
 307                 if (radeon_crtc->enabled) {
 308                         if (radeon_crtc->crtc_id) {
 309                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 310                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 311                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 312                         } else {
 313                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 314                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 315                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 316                         }
 317                 }
 318         }
 319 }
 320
 321 void r100_pm_finish(struct radeon_device *rdev)
 322 {
 323         struct drm_device *ddev = rdev->ddev;
 324         struct drm_crtc *crtc;
 325         struct radeon_crtc *radeon_crtc;
 326         u32 tmp;
 327
 328         /* enable any active CRTCs */
 329         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 330                 radeon_crtc = to_radeon_crtc(crtc);
 331                 if (radeon_crtc->enabled) {
 332                         if (radeon_crtc->crtc_id) {
 333                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 334                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 335                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 336                         } else {
 337                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 338                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 339                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 340                         }
 341                 }
 342         }
 343 }
 344
 345 bool r100_gui_idle(struct radeon_device *rdev)
 346 {
 347         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 348                 return false;
 349         else
 350                 return true;
 351 }
 352
 353 /* hpd for digital panel detect/disconnect */
 354 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 355 {
 356         bool connected = false;
 357
 358         switch (hpd) {
 359         case RADEON_HPD_1:
 360                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 361                         connected = true;
 362                 break;
 363         case RADEON_HPD_2:
 364                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 365                         connected = true;
 366                 break;
 367         default:
 368                 break;
 369         }
 370         return connected;
 371 }
 372
 373 void r100_hpd_set_polarity(struct radeon_device *rdev,
 374                            enum radeon_hpd_id hpd)
 375 {
 376         u32 tmp;
 377         bool connected = r100_hpd_sense(rdev, hpd);
 378
 379         switch (hpd) {
 380         case RADEON_HPD_1:
 381                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 382                 if (connected)
 383                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 384                 else
 385                         tmp |= RADEON_FP_DETECT_INT_POL;
 386                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 387                 break;
 388         case RADEON_HPD_2:
 389                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 390                 if (connected)
 391                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 392                 else
 393                         tmp |= RADEON_FP2_DETECT_INT_POL;
 394                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 395                 break;
 396         default:
 397                 break;
 398         }
 399 }
 400
 401 void r100_hpd_init(struct radeon_device *rdev)
 402 {
 403         struct drm_device *dev = rdev->ddev;
 404         struct drm_connector *connector;
 405
 406         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 407                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 408                 switch (radeon_connector->hpd.hpd) {
 409                 case RADEON_HPD_1:
 410                         rdev->irq.hpd[0] = true;
 411                         break;
 412                 case RADEON_HPD_2:
 413                         rdev->irq.hpd[1] = true;
 414                         break;
 415                 default:
 416                         break;
 417                 }
 418         }
 419         if (rdev->irq.installed)
 420                 r100_irq_set(rdev);
 421 }
 422
 423 void r100_hpd_fini(struct radeon_device *rdev)
 424 {
 425         struct drm_device *dev = rdev->ddev;
 426         struct drm_connector *connector;
 427
 428         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 429                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 430                 switch (radeon_connector->hpd.hpd) {
 431                 case RADEON_HPD_1:
 432                         rdev->irq.hpd[0] = false;
 433                         break;
 434                 case RADEON_HPD_2:
 435                         rdev->irq.hpd[1] = false;
 436                         break;
 437                 default:
 438                         break;
 439                 }
 440         }
 441 }
 442
 443 /*
 444  * PCI GART
 445  */
 446 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 447 {
 448         /* TODO: can we do somethings here ? */
 449         /* It seems hw only cache one entry so we should discard this
 450          * entry otherwise if first GPU GART read hit this entry it
 451          * could end up in wrong address. */
 452 }
 453
 454 int r100_pci_gart_init(struct radeon_device *rdev)
 455 {
 456         int r;
 457
 458         if (rdev->gart.table.ram.ptr) {
 459                 WARN(1, "R100 PCI GART already initialized.\n");
 460                 return 0;
 461         }
 462         /* Initialize common gart structure */
 463         r = radeon_gart_init(rdev);
 464         if (r)
 465                 return r;
 466         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 467         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 468         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 469         return radeon_gart_table_ram_alloc(rdev);
 470 }
 471
 472 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 473 void r100_enable_bm(struct radeon_device *rdev)
 474 {
 475         uint32_t tmp;
 476         /* Enable bus mastering */
 477         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 478         WREG32(RADEON_BUS_CNTL, tmp);
 479 }
 480
 481 int r100_pci_gart_enable(struct radeon_device *rdev)
 482 {
 483         uint32_t tmp;
 484
 485         radeon_gart_restore(rdev);
 486         /* discard memory request outside of configured range */
 487         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 488         WREG32(RADEON_AIC_CNTL, tmp);
 489         /* set address range for PCI address translate */
 490         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 491         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 492         /* set PCI GART page-table base address */
 493         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 494         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 495         WREG32(RADEON_AIC_CNTL, tmp);
 496         r100_pci_gart_tlb_flush(rdev);
 497         rdev->gart.ready = true;
 498         return 0;
 499 }
 500
 501 void r100_pci_gart_disable(struct radeon_device *rdev)
 502 {
 503         uint32_t tmp;
 504
 505         /* discard memory request outside of configured range */
 506         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 507         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 508         WREG32(RADEON_AIC_LO_ADDR, 0);
 509         WREG32(RADEON_AIC_HI_ADDR, 0);
 510 }
 511
 512 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 513 {
 514         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 515                 return -EINVAL;
 516         }
 517         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 518         return 0;
 519 }
 520
 521 void r100_pci_gart_fini(struct radeon_device *rdev)
 522 {
 523         radeon_gart_fini(rdev);
 524         r100_pci_gart_disable(rdev);
 525         radeon_gart_table_ram_free(rdev);
 526 }
 527
 528 int r100_irq_set(struct radeon_device *rdev)
 529 {
 530         uint32_t tmp = 0;
 531
 532         if (!rdev->irq.installed) {
 533                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 534                 WREG32(R_000040_GEN_INT_CNTL, 0);
 535                 return -EINVAL;
 536         }
 537         if (rdev->irq.sw_int) {
 538                 tmp |= RADEON_SW_INT_ENABLE;
 539         }
 540         if (rdev->irq.gui_idle) {
 541                 tmp |= RADEON_GUI_IDLE_MASK;
 542         }
 543         if (rdev->irq.crtc_vblank_int[0]) {
 544                 tmp |= RADEON_CRTC_VBLANK_MASK;
 545         }
 546         if (rdev->irq.crtc_vblank_int[1]) {
 547                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 548         }
 549         if (rdev->irq.hpd[0]) {
 550                 tmp |= RADEON_FP_DETECT_MASK;
 551         }
 552         if (rdev->irq.hpd[1]) {
 553                 tmp |= RADEON_FP2_DETECT_MASK;
 554         }
 555         WREG32(RADEON_GEN_INT_CNTL, tmp);
 556         return 0;
 557 }
 558
 559 void r100_irq_disable(struct radeon_device *rdev)
 560 {
 561         u32 tmp;
 562
 563         WREG32(R_000040_GEN_INT_CNTL, 0);
 564         /* Wait and acknowledge irq */
 565         mdelay(1);
 566         tmp = RREG32(R_000044_GEN_INT_STATUS);
 567         WREG32(R_000044_GEN_INT_STATUS, tmp);
 568 }
 569
 570 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 571 {
 572         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 573         uint32_t irq_mask = RADEON_SW_INT_TEST |
 574                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 575                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 576
 577         /* the interrupt works, but the status bit is permanently asserted */
 578         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 579                 if (!rdev->irq.gui_idle_acked)
 580                         irq_mask |= RADEON_GUI_IDLE_STAT;
 581         }
 582
 583         if (irqs) {
 584                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 585         }
 586         return irqs & irq_mask;
 587 }
 588
 589 int r100_irq_process(struct radeon_device *rdev)
 590 {
 591         uint32_t status, msi_rearm;
 592         bool queue_hotplug = false;
 593
 594         /* reset gui idle ack.  the status bit is broken */
 595         rdev->irq.gui_idle_acked = false;
 596
 597         status = r100_irq_ack(rdev);
 598         if (!status) {
 599                 return IRQ_NONE;
 600         }
 601         if (rdev->shutdown) {
 602                 return IRQ_NONE;
 603         }
 604         while (status) {
 605                 /* SW interrupt */
 606                 if (status & RADEON_SW_INT_TEST) {
 607                         radeon_fence_process(rdev);
 608                 }
 609                 /* gui idle interrupt */
 610                 if (status & RADEON_GUI_IDLE_STAT) {
 611                         rdev->irq.gui_idle_acked = true;
 612                         rdev->pm.gui_idle = true;
 613                         wake_up(&rdev->irq.idle_queue);
 614                 }
 615                 /* Vertical blank interrupts */
 616                 if (status & RADEON_CRTC_VBLANK_STAT) {
 617                         drm_handle_vblank(rdev->ddev, 0);
 618                         rdev->pm.vblank_sync = true;
 619                         wake_up(&rdev->irq.vblank_queue);
 620                 }
 621                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 622                         drm_handle_vblank(rdev->ddev, 1);
 623                         rdev->pm.vblank_sync = true;
 624                         wake_up(&rdev->irq.vblank_queue);
 625                 }
 626                 if (status & RADEON_FP_DETECT_STAT) {
 627                         queue_hotplug = true;
 628                         DRM_DEBUG("HPD1\n");
 629                 }
 630                 if (status & RADEON_FP2_DETECT_STAT) {
 631                         queue_hotplug = true;
 632                         DRM_DEBUG("HPD2\n");
 633                 }
 634                 status = r100_irq_ack(rdev);
 635         }
 636         /* reset gui idle ack.  the status bit is broken */
 637         rdev->irq.gui_idle_acked = false;
 638         if (queue_hotplug)
 639                 queue_work(rdev->wq, &rdev->hotplug_work);
 640         if (rdev->msi_enabled) {
 641                 switch (rdev->family) {
 642                 case CHIP_RS400:
 643                 case CHIP_RS480:
 644                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 645                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 646                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 647                         break;
 648                 default:
 649                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 650                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 651                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 652                         break;
 653                 }
 654         }
 655         return IRQ_HANDLED;
 656 }
 657
 658 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 659 {
 660         if (crtc == 0)
 661                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 662         else
 663                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 664 }
 665
 666 /* Who ever call radeon_fence_emit should call ring_lock and ask
 667  * for enough space (today caller are ib schedule and buffer move) */
 668 void r100_fence_ring_emit(struct radeon_device *rdev,
 669                           struct radeon_fence *fence)
 670 {
 671         /* We have to make sure that caches are flushed before
 672          * CPU might read something from VRAM. */
 673         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 674         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 675         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 676         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 677         /* Wait until IDLE & CLEAN */
 678         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 679         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 680         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 681         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 682                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 683         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 684         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 685         /* Emit fence sequence & fire IRQ */
 686         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 687         radeon_ring_write(rdev, fence->seq);
 688         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 689         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 690 }
 691
 692 int r100_wb_init(struct radeon_device *rdev)
 693 {
 694         int r;
 695
 696         if (rdev->wb.wb_obj == NULL) {
 697                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 698                                         RADEON_GEM_DOMAIN_GTT,
 699                                         &rdev->wb.wb_obj);
 700                 if (r) {
 701                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 702                         return r;
 703                 }
 704                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 705                 if (unlikely(r != 0))
 706                         return r;
 707                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 708                                         &rdev->wb.gpu_addr);
 709                 if (r) {
 710                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 711                         radeon_bo_unreserve(rdev->wb.wb_obj);
 712                         return r;
 713                 }
 714                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 715                 radeon_bo_unreserve(rdev->wb.wb_obj);
 716                 if (r) {
 717                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 718                         return r;
 719                 }
 720         }
 721         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 722         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 723                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 724         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 725         return 0;
 726 }
 727
 728 void r100_wb_disable(struct radeon_device *rdev)
 729 {
 730         WREG32(R_000770_SCRATCH_UMSK, 0);
 731 }
 732
 733 void r100_wb_fini(struct radeon_device *rdev)
 734 {
 735         int r;
 736
 737         r100_wb_disable(rdev);
 738         if (rdev->wb.wb_obj) {
 739                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 740                 if (unlikely(r != 0)) {
 741                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 742                         return;
 743                 }
 744                 radeon_bo_kunmap(rdev->wb.wb_obj);
 745                 radeon_bo_unpin(rdev->wb.wb_obj);
 746                 radeon_bo_unreserve(rdev->wb.wb_obj);
 747                 radeon_bo_unref(&rdev->wb.wb_obj);
 748                 rdev->wb.wb = NULL;
 749                 rdev->wb.wb_obj = NULL;
 750         }
 751 }
 752
 753 int r100_copy_blit(struct radeon_device *rdev,
 754                    uint64_t src_offset,
 755                    uint64_t dst_offset,
 756                    unsigned num_pages,
 757                    struct radeon_fence *fence)
 758 {
 759         uint32_t cur_pages;
 760         uint32_t stride_bytes = PAGE_SIZE;
 761         uint32_t pitch;
 762         uint32_t stride_pixels;
 763         unsigned ndw;
 764         int num_loops;
 765         int r = 0;
 766
 767         /* radeon limited to 16k stride */
 768         stride_bytes &= 0x3fff;
 769         /* radeon pitch is /64 */
 770         pitch = stride_bytes / 64;
 771         stride_pixels = stride_bytes / 4;
 772         num_loops = DIV_ROUND_UP(num_pages, 8191);
 773
 774         /* Ask for enough room for blit + flush + fence */
 775         ndw = 64 + (10 * num_loops);
 776         r = radeon_ring_lock(rdev, ndw);
 777         if (r) {
 778                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 779                 return -EINVAL;
 780         }
 781         while (num_pages > 0) {
 782                 cur_pages = num_pages;
 783                 if (cur_pages > 8191) {
 784                         cur_pages = 8191;
 785                 }
 786                 num_pages -= cur_pages;
 787
 788                 /* pages are in Y direction - height
 789                    page width in X direction - width */
 790                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 791                 radeon_ring_write(rdev,
 792                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 793                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 794                                   RADEON_GMC_SRC_CLIPPING |
 795                                   RADEON_GMC_DST_CLIPPING |
 796                                   RADEON_GMC_BRUSH_NONE |
 797                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 798                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 799                                   RADEON_ROP3_S |
 800                                   RADEON_DP_SRC_SOURCE_MEMORY |
 801                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 802                                   RADEON_GMC_WR_MSK_DIS);
 803                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 804                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 805                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 806                 radeon_ring_write(rdev, 0);
 807                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 808                 radeon_ring_write(rdev, num_pages);
 809                 radeon_ring_write(rdev, num_pages);
 810                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 811         }
 812         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 813         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 814         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 815         radeon_ring_write(rdev,
 816                           RADEON_WAIT_2D_IDLECLEAN |
 817                           RADEON_WAIT_HOST_IDLECLEAN |
 818                           RADEON_WAIT_DMA_GUI_IDLE);
 819         if (fence) {
 820                 r = radeon_fence_emit(rdev, fence);
 821         }
 822         radeon_ring_unlock_commit(rdev);
 823         return r;
 824 }
 825
 826 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 827 {
 828         unsigned i;
 829         u32 tmp;
 830
 831         for (i = 0; i < rdev->usec_timeout; i++) {
 832                 tmp = RREG32(R_000E40_RBBM_STATUS);
 833                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 834                         return 0;
 835                 }
 836                 udelay(1);
 837         }
 838         return -1;
 839 }
 840
 841 void r100_ring_start(struct radeon_device *rdev)
 842 {
 843         int r;
 844
 845         r = radeon_ring_lock(rdev, 2);
 846         if (r) {
 847                 return;
 848         }
 849         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 850         radeon_ring_write(rdev,
 851                           RADEON_ISYNC_ANY2D_IDLE3D |
 852                           RADEON_ISYNC_ANY3D_IDLE2D |
 853                           RADEON_ISYNC_WAIT_IDLEGUI |
 854                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 855         radeon_ring_unlock_commit(rdev);
 856 }
 857
 858
 859 /* Load the microcode for the CP */
 860 static int r100_cp_init_microcode(struct radeon_device *rdev)
 861 {
 862         struct platform_device *pdev;
 863         const char *fw_name = NULL;
 864         int err;
 865
 866         DRM_DEBUG("\n");
 867
 868         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 869         err = IS_ERR(pdev);
 870         if (err) {
 871                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 872                 return -EINVAL;
 873         }
 874         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 875             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 876             (rdev->family == CHIP_RS200)) {
 877                 DRM_INFO("Loading R100 Microcode\n");
 878                 fw_name = FIRMWARE_R100;
 879         } else if ((rdev->family == CHIP_R200) ||
 880                    (rdev->family == CHIP_RV250) ||
 881                    (rdev->family == CHIP_RV280) ||
 882                    (rdev->family == CHIP_RS300)) {
 883                 DRM_INFO("Loading R200 Microcode\n");
 884                 fw_name = FIRMWARE_R200;
 885         } else if ((rdev->family == CHIP_R300) ||
 886                    (rdev->family == CHIP_R350) ||
 887                    (rdev->family == CHIP_RV350) ||
 888                    (rdev->family == CHIP_RV380) ||
 889                    (rdev->family == CHIP_RS400) ||
 890                    (rdev->family == CHIP_RS480)) {
 891                 DRM_INFO("Loading R300 Microcode\n");
 892                 fw_name = FIRMWARE_R300;
 893         } else if ((rdev->family == CHIP_R420) ||
 894                    (rdev->family == CHIP_R423) ||
 895                    (rdev->family == CHIP_RV410)) {
 896                 DRM_INFO("Loading R400 Microcode\n");
 897                 fw_name = FIRMWARE_R420;
 898         } else if ((rdev->family == CHIP_RS690) ||
 899                    (rdev->family == CHIP_RS740)) {
 900                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 901                 fw_name = FIRMWARE_RS690;
 902         } else if (rdev->family == CHIP_RS600) {
 903                 DRM_INFO("Loading RS600 Microcode\n");
 904                 fw_name = FIRMWARE_RS600;
 905         } else if ((rdev->family == CHIP_RV515) ||
 906                    (rdev->family == CHIP_R520) ||
 907                    (rdev->family == CHIP_RV530) ||
 908                    (rdev->family == CHIP_R580) ||
 909                    (rdev->family == CHIP_RV560) ||
 910                    (rdev->family == CHIP_RV570)) {
 911                 DRM_INFO("Loading R500 Microcode\n");
 912                 fw_name = FIRMWARE_R520;
 913         }
 914
 915         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 916         platform_device_unregister(pdev);
 917         if (err) {
 918                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 919                        fw_name);
 920         } else if (rdev->me_fw->size % 8) {
 921                 printk(KERN_ERR
 922                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 923                        rdev->me_fw->size, fw_name);
 924                 err = -EINVAL;
 925                 release_firmware(rdev->me_fw);
 926                 rdev->me_fw = NULL;
 927         }
 928         return err;
 929 }
 930
 931 static void r100_cp_load_microcode(struct radeon_device *rdev)
 932 {
 933         const __be32 *fw_data;
 934         int i, size;
 935
 936         if (r100_gui_wait_for_idle(rdev)) {
 937                 printk(KERN_WARNING "Failed to wait GUI idle while "
 938                        "programming pipes. Bad things might happen.\n");
 939         }
 940
 941         if (rdev->me_fw) {
 942                 size = rdev->me_fw->size / 4;
 943                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 944                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 945                 for (i = 0; i < size; i += 2) {
 946                         WREG32(RADEON_CP_ME_RAM_DATAH,
 947                                be32_to_cpup(&fw_data[i]));
 948                         WREG32(RADEON_CP_ME_RAM_DATAL,
 949                                be32_to_cpup(&fw_data[i + 1]));
 950                 }
 951         }
 952 }
 953
 954 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 955 {
 956         unsigned rb_bufsz;
 957         unsigned rb_blksz;
 958         unsigned max_fetch;
 959         unsigned pre_write_timer;
 960         unsigned pre_write_limit;
 961         unsigned indirect2_start;
 962         unsigned indirect1_start;
 963         uint32_t tmp;
 964         int r;
 965
 966         if (r100_debugfs_cp_init(rdev)) {
 967                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 968         }
 969         if (!rdev->me_fw) {
 970                 r = r100_cp_init_microcode(rdev);
 971                 if (r) {
 972                         DRM_ERROR("Failed to load firmware!\n");
 973                         return r;
 974                 }
 975         }
 976
 977         /* Align ring size */
 978         rb_bufsz = drm_order(ring_size / 8);
 979         ring_size = (1 << (rb_bufsz + 1)) * 4;
 980         r100_cp_load_microcode(rdev);
 981         r = radeon_ring_init(rdev, ring_size);
 982         if (r) {
 983                 return r;
 984         }
 985         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 986          * the rptr copy in system ram */
 987         rb_blksz = 9;
 988         /* cp will read 128bytes at a time (4 dwords) */
 989         max_fetch = 1;
 990         rdev->cp.align_mask = 16 - 1;
 991         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 992         pre_write_timer = 64;
 993         /* Force CP_RB_WPTR write if written more than one time before the
 994          * delay expire
 995          */
 996         pre_write_limit = 0;
 997         /* Setup the cp cache like this (cache size is 96 dwords) :
 998          *      RING            0  to 15
 999          *      INDIRECT1       16 to 79
1000          *      INDIRECT2       80 to 95
1001          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1002          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1003          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1004          * Idea being that most of the gpu cmd will be through indirect1 buffer
1005          * so it gets the bigger cache.
1006          */
1007         indirect2_start = 80;
1008         indirect1_start = 16;
1009         /* cp setup */
1010         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1011         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1012                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1013                REG_SET(RADEON_MAX_FETCH, max_fetch) |
1014                RADEON_RB_NO_UPDATE);
1015 #ifdef __BIG_ENDIAN
1016         tmp |= RADEON_BUF_SWAP_32BIT;
1017 #endif
1018         WREG32(RADEON_CP_RB_CNTL, tmp);
1019
1020         /* Set ring address */
1021         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1022         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1023         /* Force read & write ptr to 0 */
1024         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1025         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1026         WREG32(RADEON_CP_RB_WPTR, 0);
1027         WREG32(RADEON_CP_RB_CNTL, tmp);
1028         udelay(10);
1029         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1030         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1031         /* protect against crazy HW on resume */
1032         rdev->cp.wptr &= rdev->cp.ptr_mask;
1033         /* Set cp mode to bus mastering & enable cp*/
1034         WREG32(RADEON_CP_CSQ_MODE,
1035                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1036                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1037         WREG32(0x718, 0);
1038         WREG32(0x744, 0x00004D4D);
1039         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1040         radeon_ring_start(rdev);
1041         r = radeon_ring_test(rdev);
1042         if (r) {
1043                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1044                 return r;
1045         }
1046         rdev->cp.ready = true;
1047         return 0;
1048 }
1049
1050 void r100_cp_fini(struct radeon_device *rdev)
1051 {
1052         if (r100_cp_wait_for_idle(rdev)) {
1053                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1054         }
1055         /* Disable ring */
1056         r100_cp_disable(rdev);
1057         radeon_ring_fini(rdev);
1058         DRM_INFO("radeon: cp finalized\n");
1059 }
1060
1061 void r100_cp_disable(struct radeon_device *rdev)
1062 {
1063         /* Disable ring */
1064         rdev->cp.ready = false;
1065         WREG32(RADEON_CP_CSQ_MODE, 0);
1066         WREG32(RADEON_CP_CSQ_CNTL, 0);
1067         if (r100_gui_wait_for_idle(rdev)) {
1068                 printk(KERN_WARNING "Failed to wait GUI idle while "
1069                        "programming pipes. Bad things might happen.\n");
1070         }
1071 }
1072
1073 void r100_cp_commit(struct radeon_device *rdev)
1074 {
1075         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1076         (void)RREG32(RADEON_CP_RB_WPTR);
1077 }
1078
1079
1080 /*
1081  * CS functions
1082  */
1083 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1084                           struct radeon_cs_packet *pkt,
1085                           const unsigned *auth, unsigned n,
1086                           radeon_packet0_check_t check)
1087 {
1088         unsigned reg;
1089         unsigned i, j, m;
1090         unsigned idx;
1091         int r;
1092
1093         idx = pkt->idx + 1;
1094         reg = pkt->reg;
1095         /* Check that register fall into register range
1096          * determined by the number of entry (n) in the
1097          * safe register bitmap.
1098          */
1099         if (pkt->one_reg_wr) {
1100                 if ((reg >> 7) > n) {
1101                         return -EINVAL;
1102                 }
1103         } else {
1104                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1105                         return -EINVAL;
1106                 }
1107         }
1108         for (i = 0; i <= pkt->count; i++, idx++) {
1109                 j = (reg >> 7);
1110                 m = 1 << ((reg >> 2) & 31);
1111                 if (auth[j] & m) {
1112                         r = check(p, pkt, idx, reg);
1113                         if (r) {
1114                                 return r;
1115                         }
1116                 }
1117                 if (pkt->one_reg_wr) {
1118                         if (!(auth[j] & m)) {
1119                                 break;
1120                         }
1121                 } else {
1122                         reg += 4;
1123                 }
1124         }
1125         return 0;
1126 }
1127
1128 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1129                          struct radeon_cs_packet *pkt)
1130 {
1131         volatile uint32_t *ib;
1132         unsigned i;
1133         unsigned idx;
1134
1135         ib = p->ib->ptr;
1136         idx = pkt->idx;
1137         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1138                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1139         }
1140 }
1141
1142 /**
1143  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1144  * @parser:     parser structure holding parsing context.
1145  * @pkt:        where to store packet informations
1146  *
1147  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1148  * if packet is bigger than remaining ib size. or if packets is unknown.
1149  **/
1150 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1151                          struct radeon_cs_packet *pkt,
1152                          unsigned idx)
1153 {
1154         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1155         uint32_t header;
1156
1157         if (idx >= ib_chunk->length_dw) {
1158                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1159                           idx, ib_chunk->length_dw);
1160                 return -EINVAL;
1161         }
1162         header = radeon_get_ib_value(p, idx);
1163         pkt->idx = idx;
1164         pkt->type = CP_PACKET_GET_TYPE(header);
1165         pkt->count = CP_PACKET_GET_COUNT(header);
1166         switch (pkt->type) {
1167         case PACKET_TYPE0:
1168                 pkt->reg = CP_PACKET0_GET_REG(header);
1169                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1170                 break;
1171         case PACKET_TYPE3:
1172                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1173                 break;
1174         case PACKET_TYPE2:
1175                 pkt->count = -1;
1176                 break;
1177         default:
1178                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1179                 return -EINVAL;
1180         }
1181         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1182                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1183                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1184                 return -EINVAL;
1185         }
1186         return 0;
1187 }
1188
1189 /**
1190  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1191  * @parser:             parser structure holding parsing context.
1192  *
1193  * Userspace sends a special sequence for VLINE waits.
1194  * PACKET0 - VLINE_START_END + value
1195  * PACKET0 - WAIT_UNTIL +_value
1196  * RELOC (P3) - crtc_id in reloc.
1197  *
1198  * This function parses this and relocates the VLINE START END
1199  * and WAIT UNTIL packets to the correct crtc.
1200  * It also detects a switched off crtc and nulls out the
1201  * wait in that case.
1202  */
1203 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1204 {
1205         struct drm_mode_object *obj;
1206         struct drm_crtc *crtc;
1207         struct radeon_crtc *radeon_crtc;
1208         struct radeon_cs_packet p3reloc, waitreloc;
1209         int crtc_id;
1210         int r;
1211         uint32_t header, h_idx, reg;
1212         volatile uint32_t *ib;
1213
1214         ib = p->ib->ptr;
1215
1216         /* parse the wait until */
1217         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1218         if (r)
1219                 return r;
1220
1221         /* check its a wait until and only 1 count */
1222         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1223             waitreloc.count != 0) {
1224                 DRM_ERROR("vline wait had illegal wait until segment\n");
1225                 r = -EINVAL;
1226                 return r;
1227         }
1228
1229         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1230                 DRM_ERROR("vline wait had illegal wait until\n");
1231                 r = -EINVAL;
1232                 return r;
1233         }
1234
1235         /* jump over the NOP */
1236         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1237         if (r)
1238                 return r;
1239
1240         h_idx = p->idx - 2;
1241         p->idx += waitreloc.count + 2;
1242         p->idx += p3reloc.count + 2;
1243
1244         header = radeon_get_ib_value(p, h_idx);
1245         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1246         reg = CP_PACKET0_GET_REG(header);
1247         mutex_lock(&p->rdev->ddev->mode_config.mutex);
1248         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1249         if (!obj) {
1250                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1251                 r = -EINVAL;
1252                 goto out;
1253         }
1254         crtc = obj_to_crtc(obj);
1255         radeon_crtc = to_radeon_crtc(crtc);
1256         crtc_id = radeon_crtc->crtc_id;
1257
1258         if (!crtc->enabled) {
1259                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1260                 ib[h_idx + 2] = PACKET2(0);
1261                 ib[h_idx + 3] = PACKET2(0);
1262         } else if (crtc_id == 1) {
1263                 switch (reg) {
1264                 case AVIVO_D1MODE_VLINE_START_END:
1265                         header &= ~R300_CP_PACKET0_REG_MASK;
1266                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1267                         break;
1268                 case RADEON_CRTC_GUI_TRIG_VLINE:
1269                         header &= ~R300_CP_PACKET0_REG_MASK;
1270                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1271                         break;
1272                 default:
1273                         DRM_ERROR("unknown crtc reloc\n");
1274                         r = -EINVAL;
1275                         goto out;
1276                 }
1277                 ib[h_idx] = header;
1278                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1279         }
1280 out:
1281         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1282         return r;
1283 }
1284
1285 /**
1286  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1287  * @parser:             parser structure holding parsing context.
1288  * @data:               pointer to relocation data
1289  * @offset_start:       starting offset
1290  * @offset_mask:        offset mask (to align start offset on)
1291  * @reloc:              reloc informations
1292  *
1293  * Check next packet is relocation packet3, do bo validation and compute
1294  * GPU offset using the provided start.
1295  **/
1296 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1297                               struct radeon_cs_reloc **cs_reloc)
1298 {
1299         struct radeon_cs_chunk *relocs_chunk;
1300         struct radeon_cs_packet p3reloc;
1301         unsigned idx;
1302         int r;
1303
1304         if (p->chunk_relocs_idx == -1) {
1305                 DRM_ERROR("No relocation chunk !\n");
1306                 return -EINVAL;
1307         }
1308         *cs_reloc = NULL;
1309         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1310         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1311         if (r) {
1312                 return r;
1313         }
1314         p->idx += p3reloc.count + 2;
1315         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1316                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1317                           p3reloc.idx);
1318                 r100_cs_dump_packet(p, &p3reloc);
1319                 return -EINVAL;
1320         }
1321         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1322         if (idx >= relocs_chunk->length_dw) {
1323                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1324                           idx, relocs_chunk->length_dw);
1325                 r100_cs_dump_packet(p, &p3reloc);
1326                 return -EINVAL;
1327         }
1328         /* FIXME: we assume reloc size is 4 dwords */
1329         *cs_reloc = p->relocs_ptr[(idx / 4)];
1330         return 0;
1331 }
1332
1333 static int r100_get_vtx_size(uint32_t vtx_fmt)
1334 {
1335         int vtx_size;
1336         vtx_size = 2;
1337         /* ordered according to bits in spec */
1338         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1339                 vtx_size++;
1340         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1341                 vtx_size += 3;
1342         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1343                 vtx_size++;
1344         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1345                 vtx_size++;
1346         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1347                 vtx_size += 3;
1348         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1349                 vtx_size++;
1350         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1351                 vtx_size++;
1352         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1353                 vtx_size += 2;
1354         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1355                 vtx_size += 2;
1356         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1357                 vtx_size++;
1358         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1359                 vtx_size += 2;
1360         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1361                 vtx_size++;
1362         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1363                 vtx_size += 2;
1364         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1365                 vtx_size++;
1366         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1367                 vtx_size++;
1368         /* blend weight */
1369         if (vtx_fmt & (0x7 << 15))
1370                 vtx_size += (vtx_fmt >> 15) & 0x7;
1371         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1372                 vtx_size += 3;
1373         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1374                 vtx_size += 2;
1375         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1376                 vtx_size++;
1377         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1378                 vtx_size++;
1379         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1380                 vtx_size++;
1381         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1382                 vtx_size++;
1383         return vtx_size;
1384 }
1385
1386 static int r100_packet0_check(struct radeon_cs_parser *p,
1387                               struct radeon_cs_packet *pkt,
1388                               unsigned idx, unsigned reg)
1389 {
1390         struct radeon_cs_reloc *reloc;
1391         struct r100_cs_track *track;
1392         volatile uint32_t *ib;
1393         uint32_t tmp;
1394         int r;
1395         int i, face;
1396         u32 tile_flags = 0;
1397         u32 idx_value;
1398
1399         ib = p->ib->ptr;
1400         track = (struct r100_cs_track *)p->track;
1401
1402         idx_value = radeon_get_ib_value(p, idx);
1403
1404         switch (reg) {
1405         case RADEON_CRTC_GUI_TRIG_VLINE:
1406                 r = r100_cs_packet_parse_vline(p);
1407                 if (r) {
1408                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1409                                   idx, reg);
1410                         r100_cs_dump_packet(p, pkt);
1411                         return r;
1412                 }
1413                 break;
1414                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1415                  * range access */
1416         case RADEON_DST_PITCH_OFFSET:
1417         case RADEON_SRC_PITCH_OFFSET:
1418                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1419                 if (r)
1420                         return r;
1421                 break;
1422         case RADEON_RB3D_DEPTHOFFSET:
1423                 r = r100_cs_packet_next_reloc(p, &reloc);
1424                 if (r) {
1425                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1426                                   idx, reg);
1427                         r100_cs_dump_packet(p, pkt);
1428                         return r;
1429                 }
1430                 track->zb.robj = reloc->robj;
1431                 track->zb.offset = idx_value;
1432                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1433                 break;
1434         case RADEON_RB3D_COLOROFFSET:
1435                 r = r100_cs_packet_next_reloc(p, &reloc);
1436                 if (r) {
1437                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1438                                   idx, reg);
1439                         r100_cs_dump_packet(p, pkt);
1440                         return r;
1441                 }
1442                 track->cb[0].robj = reloc->robj;
1443                 track->cb[0].offset = idx_value;
1444                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1445                 break;
1446         case RADEON_PP_TXOFFSET_0:
1447         case RADEON_PP_TXOFFSET_1:
1448         case RADEON_PP_TXOFFSET_2:
1449                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1450                 r = r100_cs_packet_next_reloc(p, &reloc);
1451                 if (r) {
1452                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1453                                   idx, reg);
1454                         r100_cs_dump_packet(p, pkt);
1455                         return r;
1456                 }
1457                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1458                 track->textures[i].robj = reloc->robj;
1459                 break;
1460         case RADEON_PP_CUBIC_OFFSET_T0_0:
1461         case RADEON_PP_CUBIC_OFFSET_T0_1:
1462         case RADEON_PP_CUBIC_OFFSET_T0_2:
1463         case RADEON_PP_CUBIC_OFFSET_T0_3:
1464         case RADEON_PP_CUBIC_OFFSET_T0_4:
1465                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1466                 r = r100_cs_packet_next_reloc(p, &reloc);
1467                 if (r) {
1468                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1469                                   idx, reg);
1470                         r100_cs_dump_packet(p, pkt);
1471                         return r;
1472                 }
1473                 track->textures[0].cube_info[i].offset = idx_value;
1474                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1475                 track->textures[0].cube_info[i].robj = reloc->robj;
1476                 break;
1477         case RADEON_PP_CUBIC_OFFSET_T1_0:
1478         case RADEON_PP_CUBIC_OFFSET_T1_1:
1479         case RADEON_PP_CUBIC_OFFSET_T1_2:
1480         case RADEON_PP_CUBIC_OFFSET_T1_3:
1481         case RADEON_PP_CUBIC_OFFSET_T1_4:
1482                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1483                 r = r100_cs_packet_next_reloc(p, &reloc);
1484                 if (r) {
1485                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1486                                   idx, reg);
1487                         r100_cs_dump_packet(p, pkt);
1488                         return r;
1489                 }
1490                 track->textures[1].cube_info[i].offset = idx_value;
1491                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1492                 track->textures[1].cube_info[i].robj = reloc->robj;
1493                 break;
1494         case RADEON_PP_CUBIC_OFFSET_T2_0:
1495         case RADEON_PP_CUBIC_OFFSET_T2_1:
1496         case RADEON_PP_CUBIC_OFFSET_T2_2:
1497         case RADEON_PP_CUBIC_OFFSET_T2_3:
1498         case RADEON_PP_CUBIC_OFFSET_T2_4:
1499                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1500                 r = r100_cs_packet_next_reloc(p, &reloc);
1501                 if (r) {
1502                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1503                                   idx, reg);
1504                         r100_cs_dump_packet(p, pkt);
1505                         return r;
1506                 }
1507                 track->textures[2].cube_info[i].offset = idx_value;
1508                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1509                 track->textures[2].cube_info[i].robj = reloc->robj;
1510                 break;
1511         case RADEON_RE_WIDTH_HEIGHT:
1512                 track->maxy = ((idx_value >> 16) & 0x7FF);
1513                 break;
1514         case RADEON_RB3D_COLORPITCH:
1515                 r = r100_cs_packet_next_reloc(p, &reloc);
1516                 if (r) {
1517                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1518                                   idx, reg);
1519                         r100_cs_dump_packet(p, pkt);
1520                         return r;
1521                 }
1522
1523                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1524                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1525                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1526                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1527
1528                 tmp = idx_value & ~(0x7 << 16);
1529                 tmp |= tile_flags;
1530                 ib[idx] = tmp;
1531
1532                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1533                 break;
1534         case RADEON_RB3D_DEPTHPITCH:
1535                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1536                 break;
1537         case RADEON_RB3D_CNTL:
1538                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1539                 case 7:
1540                 case 8:
1541                 case 9:
1542                 case 11:
1543                 case 12:
1544                         track->cb[0].cpp = 1;
1545                         break;
1546                 case 3:
1547                 case 4:
1548                 case 15:
1549                         track->cb[0].cpp = 2;
1550                         break;
1551                 case 6:
1552                         track->cb[0].cpp = 4;
1553                         break;
1554                 default:
1555                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1556                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1557                         return -EINVAL;
1558                 }
1559                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1560                 break;
1561         case RADEON_RB3D_ZSTENCILCNTL:
1562                 switch (idx_value & 0xf) {
1563                 case 0:
1564                         track->zb.cpp = 2;
1565                         break;
1566                 case 2:
1567                 case 3:
1568                 case 4:
1569                 case 5:
1570                 case 9:
1571                 case 11:
1572                         track->zb.cpp = 4;
1573                         break;
1574                 default:
1575                         break;
1576                 }
1577                 break;
1578         case RADEON_RB3D_ZPASS_ADDR:
1579                 r = r100_cs_packet_next_reloc(p, &reloc);
1580                 if (r) {
1581                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1582                                   idx, reg);
1583                         r100_cs_dump_packet(p, pkt);
1584                         return r;
1585                 }
1586                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1587                 break;
1588         case RADEON_PP_CNTL:
1589                 {
1590                         uint32_t temp = idx_value >> 4;
1591                         for (i = 0; i < track->num_texture; i++)
1592                                 track->textures[i].enabled = !!(temp & (1 << i));
1593                 }
1594                 break;
1595         case RADEON_SE_VF_CNTL:
1596                 track->vap_vf_cntl = idx_value;
1597                 break;
1598         case RADEON_SE_VTX_FMT:
1599                 track->vtx_size = r100_get_vtx_size(idx_value);
1600                 break;
1601         case RADEON_PP_TEX_SIZE_0:
1602         case RADEON_PP_TEX_SIZE_1:
1603         case RADEON_PP_TEX_SIZE_2:
1604                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1605                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1606                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1607                 break;
1608         case RADEON_PP_TEX_PITCH_0:
1609         case RADEON_PP_TEX_PITCH_1:
1610         case RADEON_PP_TEX_PITCH_2:
1611                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1612                 track->textures[i].pitch = idx_value + 32;
1613                 break;
1614         case RADEON_PP_TXFILTER_0:
1615         case RADEON_PP_TXFILTER_1:
1616         case RADEON_PP_TXFILTER_2:
1617                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1618                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1619                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1620                 tmp = (idx_value >> 23) & 0x7;
1621                 if (tmp == 2 || tmp == 6)
1622                         track->textures[i].roundup_w = false;
1623                 tmp = (idx_value >> 27) & 0x7;
1624                 if (tmp == 2 || tmp == 6)
1625                         track->textures[i].roundup_h = false;
1626                 break;
1627         case RADEON_PP_TXFORMAT_0:
1628         case RADEON_PP_TXFORMAT_1:
1629         case RADEON_PP_TXFORMAT_2:
1630                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1631                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1632                         track->textures[i].use_pitch = 1;
1633                 } else {
1634                         track->textures[i].use_pitch = 0;
1635                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1636                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1637                 }
1638                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1639                         track->textures[i].tex_coord_type = 2;
1640                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1641                 case RADEON_TXFORMAT_I8:
1642                 case RADEON_TXFORMAT_RGB332:
1643                 case RADEON_TXFORMAT_Y8:
1644                         track->textures[i].cpp = 1;
1645                         break;
1646                 case RADEON_TXFORMAT_AI88:
1647                 case RADEON_TXFORMAT_ARGB1555:
1648                 case RADEON_TXFORMAT_RGB565:
1649                 case RADEON_TXFORMAT_ARGB4444:
1650                 case RADEON_TXFORMAT_VYUY422:
1651                 case RADEON_TXFORMAT_YVYU422:
1652                 case RADEON_TXFORMAT_SHADOW16:
1653                 case RADEON_TXFORMAT_LDUDV655:
1654                 case RADEON_TXFORMAT_DUDV88:
1655                         track->textures[i].cpp = 2;
1656                         break;
1657                 case RADEON_TXFORMAT_ARGB8888:
1658                 case RADEON_TXFORMAT_RGBA8888:
1659                 case RADEON_TXFORMAT_SHADOW32:
1660                 case RADEON_TXFORMAT_LDUDUV8888:
1661                         track->textures[i].cpp = 4;
1662                         break;
1663                 case RADEON_TXFORMAT_DXT1:
1664                         track->textures[i].cpp = 1;
1665                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1666                         break;
1667                 case RADEON_TXFORMAT_DXT23:
1668                 case RADEON_TXFORMAT_DXT45:
1669                         track->textures[i].cpp = 1;
1670                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1671                         break;
1672                 }
1673                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1674                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1675                 break;
1676         case RADEON_PP_CUBIC_FACES_0:
1677         case RADEON_PP_CUBIC_FACES_1:
1678         case RADEON_PP_CUBIC_FACES_2:
1679                 tmp = idx_value;
1680                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1681                 for (face = 0; face < 4; face++) {
1682                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1683                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1684                 }
1685                 break;
1686         default:
1687                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1688                        reg, idx);
1689                 return -EINVAL;
1690         }
1691         return 0;
1692 }
1693
1694 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1695                                          struct radeon_cs_packet *pkt,
1696                                          struct radeon_bo *robj)
1697 {
1698         unsigned idx;
1699         u32 value;
1700         idx = pkt->idx + 1;
1701         value = radeon_get_ib_value(p, idx + 2);
1702         if ((value + 1) > radeon_bo_size(robj)) {
1703                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1704                           "(need %u have %lu) !\n",
1705                           value + 1,
1706                           radeon_bo_size(robj));
1707                 return -EINVAL;
1708         }
1709         return 0;
1710 }
1711
1712 static int r100_packet3_check(struct radeon_cs_parser *p,
1713                               struct radeon_cs_packet *pkt)
1714 {
1715         struct radeon_cs_reloc *reloc;
1716         struct r100_cs_track *track;
1717         unsigned idx;
1718         volatile uint32_t *ib;
1719         int r;
1720
1721         ib = p->ib->ptr;
1722         idx = pkt->idx + 1;
1723         track = (struct r100_cs_track *)p->track;
1724         switch (pkt->opcode) {
1725         case PACKET3_3D_LOAD_VBPNTR:
1726                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1727                 if (r)
1728                         return r;
1729                 break;
1730         case PACKET3_INDX_BUFFER:
1731                 r = r100_cs_packet_next_reloc(p, &reloc);
1732                 if (r) {
1733                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1734                         r100_cs_dump_packet(p, pkt);
1735                         return r;
1736                 }
1737                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1738                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1739                 if (r) {
1740                         return r;
1741                 }
1742                 break;
1743         case 0x23:
1744                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1745                 r = r100_cs_packet_next_reloc(p, &reloc);
1746                 if (r) {
1747                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1748                         r100_cs_dump_packet(p, pkt);
1749                         return r;
1750                 }
1751                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1752                 track->num_arrays = 1;
1753                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1754
1755                 track->arrays[0].robj = reloc->robj;
1756                 track->arrays[0].esize = track->vtx_size;
1757
1758                 track->max_indx = radeon_get_ib_value(p, idx+1);
1759
1760                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1761                 track->immd_dwords = pkt->count - 1;
1762                 r = r100_cs_track_check(p->rdev, track);
1763                 if (r)
1764                         return r;
1765                 break;
1766         case PACKET3_3D_DRAW_IMMD:
1767                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1768                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1769                         return -EINVAL;
1770                 }
1771                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1772                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1773                 track->immd_dwords = pkt->count - 1;
1774                 r = r100_cs_track_check(p->rdev, track);
1775                 if (r)
1776                         return r;
1777                 break;
1778                 /* triggers drawing using in-packet vertex data */
1779         case PACKET3_3D_DRAW_IMMD_2:
1780                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1781                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1782                         return -EINVAL;
1783                 }
1784                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1785                 track->immd_dwords = pkt->count;
1786                 r = r100_cs_track_check(p->rdev, track);
1787                 if (r)
1788                         return r;
1789                 break;
1790                 /* triggers drawing using in-packet vertex data */
1791         case PACKET3_3D_DRAW_VBUF_2:
1792                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1793                 r = r100_cs_track_check(p->rdev, track);
1794                 if (r)
1795                         return r;
1796                 break;
1797                 /* triggers drawing of vertex buffers setup elsewhere */
1798         case PACKET3_3D_DRAW_INDX_2:
1799                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1800                 r = r100_cs_track_check(p->rdev, track);
1801                 if (r)
1802                         return r;
1803                 break;
1804                 /* triggers drawing using indices to vertex buffer */
1805         case PACKET3_3D_DRAW_VBUF:
1806                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1807                 r = r100_cs_track_check(p->rdev, track);
1808                 if (r)
1809                         return r;
1810                 break;
1811                 /* triggers drawing of vertex buffers setup elsewhere */
1812         case PACKET3_3D_DRAW_INDX:
1813                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1814                 r = r100_cs_track_check(p->rdev, track);
1815                 if (r)
1816                         return r;
1817                 break;
1818                 /* triggers drawing using indices to vertex buffer */
1819         case PACKET3_NOP:
1820                 break;
1821         default:
1822                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1823                 return -EINVAL;
1824         }
1825         return 0;
1826 }
1827
1828 int r100_cs_parse(struct radeon_cs_parser *p)
1829 {
1830         struct radeon_cs_packet pkt;
1831         struct r100_cs_track *track;
1832         int r;
1833
1834         track = kzalloc(sizeof(*track), GFP_KERNEL);
1835         r100_cs_track_clear(p->rdev, track);
1836         p->track = track;
1837         do {
1838                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1839                 if (r) {
1840                         return r;
1841                 }
1842                 p->idx += pkt.count + 2;
1843                 switch (pkt.type) {
1844                         case PACKET_TYPE0:
1845                                 if (p->rdev->family >= CHIP_R200)
1846                                         r = r100_cs_parse_packet0(p, &pkt,
1847                                                                   p->rdev->config.r100.reg_safe_bm,
1848                                                                   p->rdev->config.r100.reg_safe_bm_size,
1849                                                                   &r200_packet0_check);
1850                                 else
1851                                         r = r100_cs_parse_packet0(p, &pkt,
1852                                                                   p->rdev->config.r100.reg_safe_bm,
1853                                                                   p->rdev->config.r100.reg_safe_bm_size,
1854                                                                   &r100_packet0_check);
1855                                 break;
1856                         case PACKET_TYPE2:
1857                                 break;
1858                         case PACKET_TYPE3:
1859                                 r = r100_packet3_check(p, &pkt);
1860                                 break;
1861                         default:
1862                                 DRM_ERROR("Unknown packet type %d !\n",
1863                                           pkt.type);
1864                                 return -EINVAL;
1865                 }
1866                 if (r) {
1867                         return r;
1868                 }
1869         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1870         return 0;
1871 }
1872
1873
1874 /*
1875  * Global GPU functions
1876  */
1877 void r100_errata(struct radeon_device *rdev)
1878 {
1879         rdev->pll_errata = 0;
1880
1881         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1882                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1883         }
1884
1885         if (rdev->family == CHIP_RV100 ||
1886             rdev->family == CHIP_RS100 ||
1887             rdev->family == CHIP_RS200) {
1888                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1889         }
1890 }
1891
1892 /* Wait for vertical sync on primary CRTC */
1893 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1894 {
1895         uint32_t crtc_gen_cntl, tmp;
1896         int i;
1897
1898         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1899         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1900             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1901                 return;
1902         }
1903         /* Clear the CRTC_VBLANK_SAVE bit */
1904         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1905         for (i = 0; i < rdev->usec_timeout; i++) {
1906                 tmp = RREG32(RADEON_CRTC_STATUS);
1907                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1908                         return;
1909                 }
1910                 DRM_UDELAY(1);
1911         }
1912 }
1913
1914 /* Wait for vertical sync on secondary CRTC */
1915 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1916 {
1917         uint32_t crtc2_gen_cntl, tmp;
1918         int i;
1919
1920         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1921         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1922             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1923                 return;
1924
1925         /* Clear the CRTC_VBLANK_SAVE bit */
1926         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1927         for (i = 0; i < rdev->usec_timeout; i++) {
1928                 tmp = RREG32(RADEON_CRTC2_STATUS);
1929                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1930                         return;
1931                 }
1932                 DRM_UDELAY(1);
1933         }
1934 }
1935
1936 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1937 {
1938         unsigned i;
1939         uint32_t tmp;
1940
1941         for (i = 0; i < rdev->usec_timeout; i++) {
1942                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1943                 if (tmp >= n) {
1944                         return 0;
1945                 }
1946                 DRM_UDELAY(1);
1947         }
1948         return -1;
1949 }
1950
1951 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1952 {
1953         unsigned i;
1954         uint32_t tmp;
1955
1956         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1957                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1958                        " Bad things might happen.\n");
1959         }
1960         for (i = 0; i < rdev->usec_timeout; i++) {
1961                 tmp = RREG32(RADEON_RBBM_STATUS);
1962                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1963                         return 0;
1964                 }
1965                 DRM_UDELAY(1);
1966         }
1967         return -1;
1968 }
1969
1970 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1971 {
1972         unsigned i;
1973         uint32_t tmp;
1974
1975         for (i = 0; i < rdev->usec_timeout; i++) {
1976                 /* read MC_STATUS */
1977                 tmp = RREG32(RADEON_MC_STATUS);
1978                 if (tmp & RADEON_MC_IDLE) {
1979                         return 0;
1980                 }
1981                 DRM_UDELAY(1);
1982         }
1983         return -1;
1984 }
1985
1986 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1987 {
1988         lockup->last_cp_rptr = cp->rptr;
1989         lockup->last_jiffies = jiffies;
1990 }
1991
1992 /**
1993  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1994  * @rdev:       radeon device structure
1995  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1996  * @cp:         radeon_cp structure holding CP information
1997  *
1998  * We don't need to initialize the lockup tracking information as we will either
1999  * have CP rptr to a different value of jiffies wrap around which will force
2000  * initialization of the lockup tracking informations.
2001  *
2002  * A possible false positivie is if we get call after while and last_cp_rptr ==
2003  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2004  * if the elapsed time since last call is bigger than 2 second than we return
2005  * false and update the tracking information. Due to this the caller must call
2006  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2007  * the fencing code should be cautious about that.
2008  *
2009  * Caller should write to the ring to force CP to do something so we don't get
2010  * false positive when CP is just gived nothing to do.
2011  *
2012  **/
2013 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2014 {
2015         unsigned long cjiffies, elapsed;
2016
2017         cjiffies = jiffies;
2018         if (!time_after(cjiffies, lockup->last_jiffies)) {
2019                 /* likely a wrap around */
2020                 lockup->last_cp_rptr = cp->rptr;
2021                 lockup->last_jiffies = jiffies;
2022                 return false;
2023         }
2024         if (cp->rptr != lockup->last_cp_rptr) {
2025                 /* CP is still working no lockup */
2026                 lockup->last_cp_rptr = cp->rptr;
2027                 lockup->last_jiffies = jiffies;
2028                 return false;
2029         }
2030         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2031         if (elapsed >= 3000) {
2032                 /* very likely the improbable case where current
2033                  * rptr is equal to last recorded, a while ago, rptr
2034                  * this is more likely a false positive update tracking
2035                  * information which should force us to be recall at
2036                  * latter point
2037                  */
2038                 lockup->last_cp_rptr = cp->rptr;
2039                 lockup->last_jiffies = jiffies;
2040                 return false;
2041         }
2042         if (elapsed >= 1000) {
2043                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2044                 return true;
2045         }
2046         /* give a chance to the GPU ... */
2047         return false;
2048 }
2049
2050 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2051 {
2052         u32 rbbm_status;
2053         int r;
2054
2055         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2056         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2057                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2058                 return false;
2059         }
2060         /* force CP activities */
2061         r = radeon_ring_lock(rdev, 2);
2062         if (!r) {
2063                 /* PACKET2 NOP */
2064                 radeon_ring_write(rdev, 0x80000000);
2065                 radeon_ring_write(rdev, 0x80000000);
2066                 radeon_ring_unlock_commit(rdev);
2067         }
2068         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2069         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2070 }
2071
2072 void r100_bm_disable(struct radeon_device *rdev)
2073 {
2074         u32 tmp;
2075
2076         /* disable bus mastering */
2077         tmp = RREG32(R_000030_BUS_CNTL);
2078         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2079         mdelay(1);
2080         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2081         mdelay(1);
2082         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2083         tmp = RREG32(RADEON_BUS_CNTL);
2084         mdelay(1);
2085         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2086         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2087         mdelay(1);
2088 }
2089
2090 int r100_asic_reset(struct radeon_device *rdev)
2091 {
2092         struct r100_mc_save save;
2093         u32 status, tmp;
2094
2095         r100_mc_stop(rdev, &save);
2096         status = RREG32(R_000E40_RBBM_STATUS);
2097         if (!G_000E40_GUI_ACTIVE(status)) {
2098                 return 0;
2099         }
2100         status = RREG32(R_000E40_RBBM_STATUS);
2101         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2102         /* stop CP */
2103         WREG32(RADEON_CP_CSQ_CNTL, 0);
2104         tmp = RREG32(RADEON_CP_RB_CNTL);
2105         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2106         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2107         WREG32(RADEON_CP_RB_WPTR, 0);
2108         WREG32(RADEON_CP_RB_CNTL, tmp);
2109         /* save PCI state */
2110         pci_save_state(rdev->pdev);
2111         /* disable bus mastering */
2112         r100_bm_disable(rdev);
2113         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2114                                         S_0000F0_SOFT_RESET_RE(1) |
2115                                         S_0000F0_SOFT_RESET_PP(1) |
2116                                         S_0000F0_SOFT_RESET_RB(1));
2117         RREG32(R_0000F0_RBBM_SOFT_RESET);
2118         mdelay(500);
2119         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2120         mdelay(1);
2121         status = RREG32(R_000E40_RBBM_STATUS);
2122         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2123         /* reset CP */
2124         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2125         RREG32(R_0000F0_RBBM_SOFT_RESET);
2126         mdelay(500);
2127         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2128         mdelay(1);
2129         status = RREG32(R_000E40_RBBM_STATUS);
2130         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2131         /* restore PCI & busmastering */
2132         pci_restore_state(rdev->pdev);
2133         r100_enable_bm(rdev);
2134         /* Check if GPU is idle */
2135         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2136                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2137                 dev_err(rdev->dev, "failed to reset GPU\n");
2138                 rdev->gpu_lockup = true;
2139                 return -1;
2140         }
2141         r100_mc_resume(rdev, &save);
2142         dev_info(rdev->dev, "GPU reset succeed\n");
2143         return 0;
2144 }
2145
2146 void r100_set_common_regs(struct radeon_device *rdev)
2147 {
2148         struct drm_device *dev = rdev->ddev;
2149         bool force_dac2 = false;
2150         u32 tmp;
2151
2152         /* set these so they don't interfere with anything */
2153         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2154         WREG32(RADEON_SUBPIC_CNTL, 0);
2155         WREG32(RADEON_VIPH_CONTROL, 0);
2156         WREG32(RADEON_I2C_CNTL_1, 0);
2157         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2158         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2159         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2160
2161         /* always set up dac2 on rn50 and some rv100 as lots
2162          * of servers seem to wire it up to a VGA port but
2163          * don't report it in the bios connector
2164          * table.
2165          */
2166         switch (dev->pdev->device) {
2167                 /* RN50 */
2168         case 0x515e:
2169         case 0x5969:
2170                 force_dac2 = true;
2171                 break;
2172                 /* RV100*/
2173         case 0x5159:
2174         case 0x515a:
2175                 /* DELL triple head servers */
2176                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2177                     ((dev->pdev->subsystem_device == 0x016c) ||
2178                      (dev->pdev->subsystem_device == 0x016d) ||
2179                      (dev->pdev->subsystem_device == 0x016e) ||
2180                      (dev->pdev->subsystem_device == 0x016f) ||
2181                      (dev->pdev->subsystem_device == 0x0170) ||
2182                      (dev->pdev->subsystem_device == 0x017d) ||
2183                      (dev->pdev->subsystem_device == 0x017e) ||
2184                      (dev->pdev->subsystem_device == 0x0183) ||
2185                      (dev->pdev->subsystem_device == 0x018a) ||
2186                      (dev->pdev->subsystem_device == 0x019a)))
2187                         force_dac2 = true;
2188                 break;
2189         }
2190
2191         if (force_dac2) {
2192                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2193                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2194                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2195
2196                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2197                    enable it, even it's detected.
2198                 */
2199
2200                 /* force it to crtc0 */
2201                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2202                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2203                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2204
2205                 /* set up the TV DAC */
2206                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2207                                  RADEON_TV_DAC_STD_MASK |
2208                                  RADEON_TV_DAC_RDACPD |
2209                                  RADEON_TV_DAC_GDACPD |
2210                                  RADEON_TV_DAC_BDACPD |
2211                                  RADEON_TV_DAC_BGADJ_MASK |
2212                                  RADEON_TV_DAC_DACADJ_MASK);
2213                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2214                                 RADEON_TV_DAC_NHOLD |
2215                                 RADEON_TV_DAC_STD_PS2 |
2216                                 (0x58 << 16));
2217
2218                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2219                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2220                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2221         }
2222
2223         /* switch PM block to ACPI mode */
2224         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2225         tmp &= ~RADEON_PM_MODE_SEL;
2226         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2227
2228 }
2229
2230 /*
2231  * VRAM info
2232  */
2233 static void r100_vram_get_type(struct radeon_device *rdev)
2234 {
2235         uint32_t tmp;
2236
2237         rdev->mc.vram_is_ddr = false;
2238         if (rdev->flags & RADEON_IS_IGP)
2239                 rdev->mc.vram_is_ddr = true;
2240         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2241                 rdev->mc.vram_is_ddr = true;
2242         if ((rdev->family == CHIP_RV100) ||
2243             (rdev->family == CHIP_RS100) ||
2244             (rdev->family == CHIP_RS200)) {
2245                 tmp = RREG32(RADEON_MEM_CNTL);
2246                 if (tmp & RV100_HALF_MODE) {
2247                         rdev->mc.vram_width = 32;
2248                 } else {
2249                         rdev->mc.vram_width = 64;
2250                 }
2251                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2252                         rdev->mc.vram_width /= 4;
2253                         rdev->mc.vram_is_ddr = true;
2254                 }
2255         } else if (rdev->family <= CHIP_RV280) {
2256                 tmp = RREG32(RADEON_MEM_CNTL);
2257                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2258                         rdev->mc.vram_width = 128;
2259                 } else {
2260                         rdev->mc.vram_width = 64;
2261                 }
2262         } else {
2263                 /* newer IGPs */
2264                 rdev->mc.vram_width = 128;
2265         }
2266 }
2267
2268 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2269 {
2270         u32 aper_size;
2271         u8 byte;
2272
2273         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2274
2275         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2276          * that is has the 2nd generation multifunction PCI interface
2277          */
2278         if (rdev->family == CHIP_RV280 ||
2279             rdev->family >= CHIP_RV350) {
2280                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2281                        ~RADEON_HDP_APER_CNTL);
2282                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2283                 return aper_size * 2;
2284         }
2285
2286         /* Older cards have all sorts of funny issues to deal with. First
2287          * check if it's a multifunction card by reading the PCI config
2288          * header type... Limit those to one aperture size
2289          */
2290         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2291         if (byte & 0x80) {
2292                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2293                 DRM_INFO("Limiting VRAM to one aperture\n");
2294                 return aper_size;
2295         }
2296
2297         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2298          * have set it up. We don't write this as it's broken on some ASICs but
2299          * we expect the BIOS to have done the right thing (might be too optimistic...)
2300          */
2301         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2302                 return aper_size * 2;
2303         return aper_size;
2304 }
2305
2306 void r100_vram_init_sizes(struct radeon_device *rdev)
2307 {
2308         u64 config_aper_size;
2309
2310         /* work out accessible VRAM */
2311         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2312         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2313         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2314         /* FIXME we don't use the second aperture yet when we could use it */
2315         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2316                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2317         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2318         if (rdev->flags & RADEON_IS_IGP) {
2319                 uint32_t tom;
2320                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2321                 tom = RREG32(RADEON_NB_TOM);
2322                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2323                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2324                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2325         } else {
2326                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2327                 /* Some production boards of m6 will report 0
2328                  * if it's 8 MB
2329                  */
2330                 if (rdev->mc.real_vram_size == 0) {
2331                         rdev->mc.real_vram_size = 8192 * 1024;
2332                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2333                 }
2334                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2335                  * Novell bug 204882 + along with lots of ubuntu ones
2336                  */
2337                 if (config_aper_size > rdev->mc.real_vram_size)
2338                         rdev->mc.mc_vram_size = config_aper_size;
2339                 else
2340                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2341         }
2342 }
2343
2344 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2345 {
2346         uint32_t temp;
2347
2348         temp = RREG32(RADEON_CONFIG_CNTL);
2349         if (state == false) {
2350                 temp &= ~(1<<8);
2351                 temp |= (1<<9);
2352         } else {
2353                 temp &= ~(1<<9);
2354         }
2355         WREG32(RADEON_CONFIG_CNTL, temp);
2356 }
2357
2358 void r100_mc_init(struct radeon_device *rdev)
2359 {
2360         u64 base;
2361
2362         r100_vram_get_type(rdev);
2363         r100_vram_init_sizes(rdev);
2364         base = rdev->mc.aper_base;
2365         if (rdev->flags & RADEON_IS_IGP)
2366                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2367         radeon_vram_location(rdev, &rdev->mc, base);
2368         if (!(rdev->flags & RADEON_IS_AGP))
2369                 radeon_gtt_location(rdev, &rdev->mc);
2370         radeon_update_bandwidth_info(rdev);
2371 }
2372
2373
2374 /*
2375  * Indirect registers accessor
2376  */
2377 void r100_pll_errata_after_index(struct radeon_device *rdev)
2378 {
2379         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2380                 return;
2381         }
2382         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2383         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2384 }
2385
2386 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2387 {
2388         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2389          * or the chip could hang on a subsequent access
2390          */
2391         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2392                 udelay(5000);
2393         }
2394
2395         /* This function is required to workaround a hardware bug in some (all?)
2396          * revisions of the R300.  This workaround should be called after every
2397          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2398          * may not be correct.
2399          */
2400         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2401                 uint32_t save, tmp;
2402
2403                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2404                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2405                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2406                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2407                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2408         }
2409 }
2410
2411 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2412 {
2413         uint32_t data;
2414
2415         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2416         r100_pll_errata_after_index(rdev);
2417         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2418         r100_pll_errata_after_data(rdev);
2419         return data;
2420 }
2421
2422 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2423 {
2424         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2425         r100_pll_errata_after_index(rdev);
2426         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2427         r100_pll_errata_after_data(rdev);
2428 }
2429
2430 void r100_set_safe_registers(struct radeon_device *rdev)
2431 {
2432         if (ASIC_IS_RN50(rdev)) {
2433                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2434                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2435         } else if (rdev->family < CHIP_R200) {
2436                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2437                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2438         } else {
2439                 r200_set_safe_registers(rdev);
2440         }
2441 }
2442
2443 /*
2444  * Debugfs info
2445  */
2446 #if defined(CONFIG_DEBUG_FS)
2447 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2448 {
2449         struct drm_info_node *node = (struct drm_info_node *) m->private;
2450         struct drm_device *dev = node->minor->dev;
2451         struct radeon_device *rdev = dev->dev_private;
2452         uint32_t reg, value;
2453         unsigned i;
2454
2455         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2456         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2457         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2458         for (i = 0; i < 64; i++) {
2459                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2460                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2461                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2462                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2463                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2464         }
2465         return 0;
2466 }
2467
2468 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2469 {
2470         struct drm_info_node *node = (struct drm_info_node *) m->private;
2471         struct drm_device *dev = node->minor->dev;
2472         struct radeon_device *rdev = dev->dev_private;
2473         uint32_t rdp, wdp;
2474         unsigned count, i, j;
2475
2476         radeon_ring_free_size(rdev);
2477         rdp = RREG32(RADEON_CP_RB_RPTR);
2478         wdp = RREG32(RADEON_CP_RB_WPTR);
2479         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2480         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2481         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2482         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2483         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2484         seq_printf(m, "%u dwords in ring\n", count);
2485         for (j = 0; j <= count; j++) {
2486                 i = (rdp + j) & rdev->cp.ptr_mask;
2487                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2488         }
2489         return 0;
2490 }
2491
2492
2493 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2494 {
2495         struct drm_info_node *node = (struct drm_info_node *) m->private;
2496         struct drm_device *dev = node->minor->dev;
2497         struct radeon_device *rdev = dev->dev_private;
2498         uint32_t csq_stat, csq2_stat, tmp;
2499         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2500         unsigned i;
2501
2502         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2503         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2504         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2505         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2506         r_rptr = (csq_stat >> 0) & 0x3ff;
2507         r_wptr = (csq_stat >> 10) & 0x3ff;
2508         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2509         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2510         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2511         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2512         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2513         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2514         seq_printf(m, "Ring rptr %u\n", r_rptr);
2515         seq_printf(m, "Ring wptr %u\n", r_wptr);
2516         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2517         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2518         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2519         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2520         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2521          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2522         seq_printf(m, "Ring fifo:\n");
2523         for (i = 0; i < 256; i++) {
2524                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2525                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2526                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2527         }
2528         seq_printf(m, "Indirect1 fifo:\n");
2529         for (i = 256; i <= 512; i++) {
2530                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2531                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2532                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2533         }
2534         seq_printf(m, "Indirect2 fifo:\n");
2535         for (i = 640; i < ib1_wptr; i++) {
2536                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2537                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2538                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2539         }
2540         return 0;
2541 }
2542
2543 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2544 {
2545         struct drm_info_node *node = (struct drm_info_node *) m->private;
2546         struct drm_device *dev = node->minor->dev;
2547         struct radeon_device *rdev = dev->dev_private;
2548         uint32_t tmp;
2549
2550         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2551         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2552         tmp = RREG32(RADEON_MC_FB_LOCATION);
2553         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2554         tmp = RREG32(RADEON_BUS_CNTL);
2555         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2556         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2557         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2558         tmp = RREG32(RADEON_AGP_BASE);
2559         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2560         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2561         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2562         tmp = RREG32(0x01D0);
2563         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2564         tmp = RREG32(RADEON_AIC_LO_ADDR);
2565         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2566         tmp = RREG32(RADEON_AIC_HI_ADDR);
2567         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2568         tmp = RREG32(0x01E4);
2569         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2570         return 0;
2571 }
2572
2573 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2574         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2575 };
2576
2577 static struct drm_info_list r100_debugfs_cp_list[] = {
2578         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2579         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2580 };
2581
2582 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2583         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2584 };
2585 #endif
2586
2587 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2588 {
2589 #if defined(CONFIG_DEBUG_FS)
2590         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2591 #else
2592         return 0;
2593 #endif
2594 }
2595
2596 int r100_debugfs_cp_init(struct radeon_device *rdev)
2597 {
2598 #if defined(CONFIG_DEBUG_FS)
2599         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2600 #else
2601         return 0;
2602 #endif
2603 }
2604
2605 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2606 {
2607 #if defined(CONFIG_DEBUG_FS)
2608         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2609 #else
2610         return 0;
2611 #endif
2612 }
2613
2614 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2615                          uint32_t tiling_flags, uint32_t pitch,
2616                          uint32_t offset, uint32_t obj_size)
2617 {
2618         int surf_index = reg * 16;
2619         int flags = 0;
2620
2621         /* r100/r200 divide by 16 */
2622         if (rdev->family < CHIP_R300)
2623                 flags = pitch / 16;
2624         else
2625                 flags = pitch / 8;
2626
2627         if (rdev->family <= CHIP_RS200) {
2628                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2629                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2630                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2631                 if (tiling_flags & RADEON_TILING_MACRO)
2632                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2633         } else if (rdev->family <= CHIP_RV280) {
2634                 if (tiling_flags & (RADEON_TILING_MACRO))
2635                         flags |= R200_SURF_TILE_COLOR_MACRO;
2636                 if (tiling_flags & RADEON_TILING_MICRO)
2637                         flags |= R200_SURF_TILE_COLOR_MICRO;
2638         } else {
2639                 if (tiling_flags & RADEON_TILING_MACRO)
2640                         flags |= R300_SURF_TILE_MACRO;
2641                 if (tiling_flags & RADEON_TILING_MICRO)
2642                         flags |= R300_SURF_TILE_MICRO;
2643         }
2644
2645         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2646                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2647         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2648                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2649
2650         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2651         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2652         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2653         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2654         return 0;
2655 }
2656
2657 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2658 {
2659         int surf_index = reg * 16;
2660         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2661 }
2662
2663 void r100_bandwidth_update(struct radeon_device *rdev)
2664 {
2665         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2666         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2667         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2668         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2669         fixed20_12 memtcas_ff[8] = {
2670                 fixed_init(1),
2671                 fixed_init(2),
2672                 fixed_init(3),
2673                 fixed_init(0),
2674                 fixed_init_half(1),
2675                 fixed_init_half(2),
2676                 fixed_init(0),
2677         };
2678         fixed20_12 memtcas_rs480_ff[8] = {
2679                 fixed_init(0),
2680                 fixed_init(1),
2681                 fixed_init(2),
2682                 fixed_init(3),
2683                 fixed_init(0),
2684                 fixed_init_half(1),
2685                 fixed_init_half(2),
2686                 fixed_init_half(3),
2687         };
2688         fixed20_12 memtcas2_ff[8] = {
2689                 fixed_init(0),
2690                 fixed_init(1),
2691                 fixed_init(2),
2692                 fixed_init(3),
2693                 fixed_init(4),
2694                 fixed_init(5),
2695                 fixed_init(6),
2696                 fixed_init(7),
2697         };
2698         fixed20_12 memtrbs[8] = {
2699                 fixed_init(1),
2700                 fixed_init_half(1),
2701                 fixed_init(2),
2702                 fixed_init_half(2),
2703                 fixed_init(3),
2704                 fixed_init_half(3),
2705                 fixed_init(4),
2706                 fixed_init_half(4)
2707         };
2708         fixed20_12 memtrbs_r4xx[8] = {
2709                 fixed_init(4),
2710                 fixed_init(5),
2711                 fixed_init(6),
2712                 fixed_init(7),
2713                 fixed_init(8),
2714                 fixed_init(9),
2715                 fixed_init(10),
2716                 fixed_init(11)
2717         };
2718         fixed20_12 min_mem_eff;
2719         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2720         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2721         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2722                 disp_drain_rate2, read_return_rate;
2723         fixed20_12 time_disp1_drop_priority;
2724         int c;
2725         int cur_size = 16;       /* in octawords */
2726         int critical_point = 0, critical_point2;
2727 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2728         int stop_req, max_stop_req;
2729         struct drm_display_mode *mode1 = NULL;
2730         struct drm_display_mode *mode2 = NULL;
2731         uint32_t pixel_bytes1 = 0;
2732         uint32_t pixel_bytes2 = 0;
2733
2734         radeon_update_display_priority(rdev);
2735
2736         if (rdev->mode_info.crtcs[0]->base.enabled) {
2737                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2738                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2739         }
2740         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2741                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2742                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2743                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2744                 }
2745         }
2746
2747         min_mem_eff.full = rfixed_const_8(0);
2748         /* get modes */
2749         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2750                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2751                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2752                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2753                 /* check crtc enables */
2754                 if (mode2)
2755                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2756                 if (mode1)
2757                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2758                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2759         }
2760
2761         /*
2762          * determine is there is enough bw for current mode
2763          */
2764         sclk_ff = rdev->pm.sclk;
2765         mclk_ff = rdev->pm.mclk;
2766
2767         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2768         temp_ff.full = rfixed_const(temp);
2769         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2770
2771         pix_clk.full = 0;
2772         pix_clk2.full = 0;
2773         peak_disp_bw.full = 0;
2774         if (mode1) {
2775                 temp_ff.full = rfixed_const(1000);
2776                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2777                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2778                 temp_ff.full = rfixed_const(pixel_bytes1);
2779                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2780         }
2781         if (mode2) {
2782                 temp_ff.full = rfixed_const(1000);
2783                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2784                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2785                 temp_ff.full = rfixed_const(pixel_bytes2);
2786                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2787         }
2788
2789         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2790         if (peak_disp_bw.full >= mem_bw.full) {
2791                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2792                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2793         }
2794
2795         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2796         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2797         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2798                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2799                 mem_trp  = ((temp & 0x3)) + 1;
2800                 mem_tras = ((temp & 0x70) >> 4) + 1;
2801         } else if (rdev->family == CHIP_R300 ||
2802                    rdev->family == CHIP_R350) { /* r300, r350 */
2803                 mem_trcd = (temp & 0x7) + 1;
2804                 mem_trp = ((temp >> 8) & 0x7) + 1;
2805                 mem_tras = ((temp >> 11) & 0xf) + 4;
2806         } else if (rdev->family == CHIP_RV350 ||
2807                    rdev->family <= CHIP_RV380) {
2808                 /* rv3x0 */
2809                 mem_trcd = (temp & 0x7) + 3;
2810                 mem_trp = ((temp >> 8) & 0x7) + 3;
2811                 mem_tras = ((temp >> 11) & 0xf) + 6;
2812         } else if (rdev->family == CHIP_R420 ||
2813                    rdev->family == CHIP_R423 ||
2814                    rdev->family == CHIP_RV410) {
2815                 /* r4xx */
2816                 mem_trcd = (temp & 0xf) + 3;
2817                 if (mem_trcd > 15)
2818                         mem_trcd = 15;
2819                 mem_trp = ((temp >> 8) & 0xf) + 3;
2820                 if (mem_trp > 15)
2821                         mem_trp = 15;
2822                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2823                 if (mem_tras > 31)
2824                         mem_tras = 31;
2825         } else { /* RV200, R200 */
2826                 mem_trcd = (temp & 0x7) + 1;
2827                 mem_trp = ((temp >> 8) & 0x7) + 1;
2828                 mem_tras = ((temp >> 12) & 0xf) + 4;
2829         }
2830         /* convert to FF */
2831         trcd_ff.full = rfixed_const(mem_trcd);
2832         trp_ff.full = rfixed_const(mem_trp);
2833         tras_ff.full = rfixed_const(mem_tras);
2834
2835         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2836         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2837         data = (temp & (7 << 20)) >> 20;
2838         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2839                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2840                         tcas_ff = memtcas_rs480_ff[data];
2841                 else
2842                         tcas_ff = memtcas_ff[data];
2843         } else
2844                 tcas_ff = memtcas2_ff[data];
2845
2846         if (rdev->family == CHIP_RS400 ||
2847             rdev->family == CHIP_RS480) {
2848                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2849                 data = (temp >> 23) & 0x7;
2850                 if (data < 5)
2851                         tcas_ff.full += rfixed_const(data);
2852         }
2853
2854         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2855                 /* on the R300, Tcas is included in Trbs.
2856                  */
2857                 temp = RREG32(RADEON_MEM_CNTL);
2858                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2859                 if (data == 1) {
2860                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2861                                 temp = RREG32(R300_MC_IND_INDEX);
2862                                 temp &= ~R300_MC_IND_ADDR_MASK;
2863                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2864                                 WREG32(R300_MC_IND_INDEX, temp);
2865                                 temp = RREG32(R300_MC_IND_DATA);
2866                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2867                         } else {
2868                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2869                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2870                         }
2871                 } else {
2872                         temp = RREG32(R300_MC_READ_CNTL_AB);
2873                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2874                 }
2875                 if (rdev->family == CHIP_RV410 ||
2876                     rdev->family == CHIP_R420 ||
2877                     rdev->family == CHIP_R423)
2878                         trbs_ff = memtrbs_r4xx[data];
2879                 else
2880                         trbs_ff = memtrbs[data];
2881                 tcas_ff.full += trbs_ff.full;
2882         }
2883
2884         sclk_eff_ff.full = sclk_ff.full;
2885
2886         if (rdev->flags & RADEON_IS_AGP) {
2887                 fixed20_12 agpmode_ff;
2888                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2889                 temp_ff.full = rfixed_const_666(16);
2890                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2891         }
2892         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2893
2894         if (ASIC_IS_R300(rdev)) {
2895                 sclk_delay_ff.full = rfixed_const(250);
2896         } else {
2897                 if ((rdev->family == CHIP_RV100) ||
2898                     rdev->flags & RADEON_IS_IGP) {
2899                         if (rdev->mc.vram_is_ddr)
2900                                 sclk_delay_ff.full = rfixed_const(41);
2901                         else
2902                                 sclk_delay_ff.full = rfixed_const(33);
2903                 } else {
2904                         if (rdev->mc.vram_width == 128)
2905                                 sclk_delay_ff.full = rfixed_const(57);
2906                         else
2907                                 sclk_delay_ff.full = rfixed_const(41);
2908                 }
2909         }
2910
2911         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2912
2913         if (rdev->mc.vram_is_ddr) {
2914                 if (rdev->mc.vram_width == 32) {
2915                         k1.full = rfixed_const(40);
2916                         c  = 3;
2917                 } else {
2918                         k1.full = rfixed_const(20);
2919                         c  = 1;
2920                 }
2921         } else {
2922                 k1.full = rfixed_const(40);
2923                 c  = 3;
2924         }
2925
2926         temp_ff.full = rfixed_const(2);
2927         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2928         temp_ff.full = rfixed_const(c);
2929         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2930         temp_ff.full = rfixed_const(4);
2931         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2932         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2933         mc_latency_mclk.full += k1.full;
2934
2935         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2936         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2937
2938         /*
2939           HW cursor time assuming worst case of full size colour cursor.
2940         */
2941         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2942         temp_ff.full += trcd_ff.full;
2943         if (temp_ff.full < tras_ff.full)
2944                 temp_ff.full = tras_ff.full;
2945         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2946
2947         temp_ff.full = rfixed_const(cur_size);
2948         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2949         /*
2950           Find the total latency for the display data.
2951         */
2952         disp_latency_overhead.full = rfixed_const(8);
2953         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2954         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2955         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2956
2957         if (mc_latency_mclk.full > mc_latency_sclk.full)
2958                 disp_latency.full = mc_latency_mclk.full;
2959         else
2960                 disp_latency.full = mc_latency_sclk.full;
2961
2962         /* setup Max GRPH_STOP_REQ default value */
2963         if (ASIC_IS_RV100(rdev))
2964                 max_stop_req = 0x5c;
2965         else
2966                 max_stop_req = 0x7c;
2967
2968         if (mode1) {
2969                 /*  CRTC1
2970                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2971                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2972                 */
2973                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2974
2975                 if (stop_req > max_stop_req)
2976                         stop_req = max_stop_req;
2977
2978                 /*
2979                   Find the drain rate of the display buffer.
2980                 */
2981                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2982                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2983
2984                 /*
2985                   Find the critical point of the display buffer.
2986                 */
2987                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2988                 crit_point_ff.full += rfixed_const_half(0);
2989
2990                 critical_point = rfixed_trunc(crit_point_ff);
2991
2992                 if (rdev->disp_priority == 2) {
2993                         critical_point = 0;
2994                 }
2995
2996                 /*
2997                   The critical point should never be above max_stop_req-4.  Setting
2998                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2999                 */
3000                 if (max_stop_req - critical_point < 4)
3001                         critical_point = 0;
3002
3003                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3004                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3005                         critical_point = 0x10;
3006                 }
3007
3008                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3009                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3010                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3011                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3012                 if ((rdev->family == CHIP_R350) &&
3013                     (stop_req > 0x15)) {
3014                         stop_req -= 0x10;
3015                 }
3016                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3017                 temp |= RADEON_GRPH_BUFFER_SIZE;
3018                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3019                           RADEON_GRPH_CRITICAL_AT_SOF |
3020                           RADEON_GRPH_STOP_CNTL);
3021                 /*
3022                   Write the result into the register.
3023                 */
3024                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3025                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3026
3027 #if 0
3028                 if ((rdev->family == CHIP_RS400) ||
3029                     (rdev->family == CHIP_RS480)) {
3030                         /* attempt to program RS400 disp regs correctly ??? */
3031                         temp = RREG32(RS400_DISP1_REG_CNTL);
3032                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3033                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3034                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3035                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3036                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3037                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3038                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3039                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3040                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3041                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3042                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3043                 }
3044 #endif
3045
3046                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3047                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3048                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3049         }
3050
3051         if (mode2) {
3052                 u32 grph2_cntl;
3053                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3054
3055                 if (stop_req > max_stop_req)
3056                         stop_req = max_stop_req;
3057
3058                 /*
3059                   Find the drain rate of the display buffer.
3060                 */
3061                 temp_ff.full = rfixed_const((16/pixel_bytes2));
3062                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
3063
3064                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3065                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3066                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3067                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3068                 if ((rdev->family == CHIP_R350) &&
3069                     (stop_req > 0x15)) {
3070                         stop_req -= 0x10;
3071                 }
3072                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3073                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3074                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3075                           RADEON_GRPH_CRITICAL_AT_SOF |
3076                           RADEON_GRPH_STOP_CNTL);
3077
3078                 if ((rdev->family == CHIP_RS100) ||
3079                     (rdev->family == CHIP_RS200))
3080                         critical_point2 = 0;
3081                 else {
3082                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3083                         temp_ff.full = rfixed_const(temp);
3084                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
3085                         if (sclk_ff.full < temp_ff.full)
3086                                 temp_ff.full = sclk_ff.full;
3087
3088                         read_return_rate.full = temp_ff.full;
3089
3090                         if (mode1) {
3091                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3092                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
3093                         } else {
3094                                 time_disp1_drop_priority.full = 0;
3095                         }
3096                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3097                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
3098                         crit_point_ff.full += rfixed_const_half(0);
3099
3100                         critical_point2 = rfixed_trunc(crit_point_ff);
3101
3102                         if (rdev->disp_priority == 2) {
3103                                 critical_point2 = 0;
3104                         }
3105
3106                         if (max_stop_req - critical_point2 < 4)
3107                                 critical_point2 = 0;
3108
3109                 }
3110
3111                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3112                         /* some R300 cards have problem with this set to 0 */
3113                         critical_point2 = 0x10;
3114                 }
3115
3116                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3117                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3118
3119                 if ((rdev->family == CHIP_RS400) ||
3120                     (rdev->family == CHIP_RS480)) {
3121 #if 0
3122                         /* attempt to program RS400 disp2 regs correctly ??? */
3123                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3124                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3125                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3126                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3127                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3128                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3129                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3130                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3131                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3132                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3133                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3134                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3135 #endif
3136                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3137                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3138                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3139                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3140                 }
3141
3142                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3143                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3144         }
3145 }
3146
3147 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3148 {
3149         DRM_ERROR("pitch                      %d\n", t->pitch);
3150         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3151         DRM_ERROR("width                      %d\n", t->width);
3152         DRM_ERROR("width_11                   %d\n", t->width_11);
3153         DRM_ERROR("height                     %d\n", t->height);
3154         DRM_ERROR("height_11                  %d\n", t->height_11);
3155         DRM_ERROR("num levels                 %d\n", t->num_levels);
3156         DRM_ERROR("depth                      %d\n", t->txdepth);
3157         DRM_ERROR("bpp                        %d\n", t->cpp);
3158         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3159         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3160         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3161         DRM_ERROR("compress format            %d\n", t->compress_format);
3162 }
3163
3164 static int r100_cs_track_cube(struct radeon_device *rdev,
3165                               struct r100_cs_track *track, unsigned idx)
3166 {
3167         unsigned face, w, h;
3168         struct radeon_bo *cube_robj;
3169         unsigned long size;
3170
3171         for (face = 0; face < 5; face++) {
3172                 cube_robj = track->textures[idx].cube_info[face].robj;
3173                 w = track->textures[idx].cube_info[face].width;
3174                 h = track->textures[idx].cube_info[face].height;
3175
3176                 size = w * h;
3177                 size *= track->textures[idx].cpp;
3178
3179                 size += track->textures[idx].cube_info[face].offset;
3180
3181                 if (size > radeon_bo_size(cube_robj)) {
3182                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3183                                   size, radeon_bo_size(cube_robj));
3184                         r100_cs_track_texture_print(&track->textures[idx]);
3185                         return -1;
3186                 }
3187         }
3188         return 0;
3189 }
3190
3191 static int r100_track_compress_size(int compress_format, int w, int h)
3192 {
3193         int block_width, block_height, block_bytes;
3194         int wblocks, hblocks;
3195         int min_wblocks;
3196         int sz;
3197
3198         block_width = 4;
3199         block_height = 4;
3200
3201         switch (compress_format) {
3202         case R100_TRACK_COMP_DXT1:
3203                 block_bytes = 8;
3204                 min_wblocks = 4;
3205                 break;
3206         default:
3207         case R100_TRACK_COMP_DXT35:
3208                 block_bytes = 16;
3209                 min_wblocks = 2;
3210                 break;
3211         }
3212
3213         hblocks = (h + block_height - 1) / block_height;
3214         wblocks = (w + block_width - 1) / block_width;
3215         if (wblocks < min_wblocks)
3216                 wblocks = min_wblocks;
3217         sz = wblocks * hblocks * block_bytes;
3218         return sz;
3219 }
3220
3221 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3222                                        struct r100_cs_track *track)
3223 {
3224         struct radeon_bo *robj;
3225         unsigned long size;
3226         unsigned u, i, w, h, d;
3227         int ret;
3228
3229         for (u = 0; u < track->num_texture; u++) {
3230                 if (!track->textures[u].enabled)
3231                         continue;
3232                 robj = track->textures[u].robj;
3233                 if (robj == NULL) {
3234                         DRM_ERROR("No texture bound to unit %u\n", u);
3235                         return -EINVAL;
3236                 }
3237                 size = 0;
3238                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3239                         if (track->textures[u].use_pitch) {
3240                                 if (rdev->family < CHIP_R300)
3241                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3242                                 else
3243                                         w = track->textures[u].pitch / (1 << i);
3244                         } else {
3245                                 w = track->textures[u].width;
3246                                 if (rdev->family >= CHIP_RV515)
3247                                         w |= track->textures[u].width_11;
3248                                 w = w / (1 << i);
3249                                 if (track->textures[u].roundup_w)
3250                                         w = roundup_pow_of_two(w);
3251                         }
3252                         h = track->textures[u].height;
3253                         if (rdev->family >= CHIP_RV515)
3254                                 h |= track->textures[u].height_11;
3255                         h = h / (1 << i);
3256                         if (track->textures[u].roundup_h)
3257                                 h = roundup_pow_of_two(h);
3258                         if (track->textures[u].tex_coord_type == 1) {
3259                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3260                                 if (!d)
3261                                         d = 1;
3262                         } else {
3263                                 d = 1;
3264                         }
3265                         if (track->textures[u].compress_format) {
3266
3267                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3268                                 /* compressed textures are block based */
3269                         } else
3270                                 size += w * h * d;
3271                 }
3272                 size *= track->textures[u].cpp;
3273
3274                 switch (track->textures[u].tex_coord_type) {
3275                 case 0:
3276                 case 1:
3277                         break;
3278                 case 2:
3279                         if (track->separate_cube) {
3280                                 ret = r100_cs_track_cube(rdev, track, u);
3281                                 if (ret)
3282                                         return ret;
3283                         } else
3284                                 size *= 6;
3285                         break;
3286                 default:
3287                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3288                                   "%u\n", track->textures[u].tex_coord_type, u);
3289                         return -EINVAL;
3290                 }
3291                 if (size > radeon_bo_size(robj)) {
3292                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3293                                   "%lu\n", u, size, radeon_bo_size(robj));
3294                         r100_cs_track_texture_print(&track->textures[u]);
3295                         return -EINVAL;
3296                 }
3297         }
3298         return 0;
3299 }
3300
3301 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3302 {
3303         unsigned i;
3304         unsigned long size;
3305         unsigned prim_walk;
3306         unsigned nverts;
3307
3308         for (i = 0; i < track->num_cb; i++) {
3309                 if (track->cb[i].robj == NULL) {
3310                         if (!(track->fastfill || track->color_channel_mask ||
3311                               track->blend_read_enable)) {
3312                                 continue;
3313                         }
3314                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3315                         return -EINVAL;
3316                 }
3317                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3318                 size += track->cb[i].offset;
3319                 if (size > radeon_bo_size(track->cb[i].robj)) {
3320                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3321                                   "(need %lu have %lu) !\n", i, size,
3322                                   radeon_bo_size(track->cb[i].robj));
3323                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3324                                   i, track->cb[i].pitch, track->cb[i].cpp,
3325                                   track->cb[i].offset, track->maxy);
3326                         return -EINVAL;
3327                 }
3328         }
3329         if (track->z_enabled) {
3330                 if (track->zb.robj == NULL) {
3331                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3332                         return -EINVAL;
3333                 }
3334                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3335                 size += track->zb.offset;
3336                 if (size > radeon_bo_size(track->zb.robj)) {
3337                         DRM_ERROR("[drm] Buffer too small for z buffer "
3338                                   "(need %lu have %lu) !\n", size,
3339                                   radeon_bo_size(track->zb.robj));
3340                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3341                                   track->zb.pitch, track->zb.cpp,
3342                                   track->zb.offset, track->maxy);
3343                         return -EINVAL;
3344                 }
3345         }
3346         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3347         if (track->vap_vf_cntl & (1 << 14)) {
3348                 nverts = track->vap_alt_nverts;
3349         } else {
3350                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3351         }
3352         switch (prim_walk) {
3353         case 1:
3354                 for (i = 0; i < track->num_arrays; i++) {
3355                         size = track->arrays[i].esize * track->max_indx * 4;
3356                         if (track->arrays[i].robj == NULL) {
3357                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3358                                           "bound\n", prim_walk, i);
3359                                 return -EINVAL;
3360                         }
3361                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3362                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3363                                         "need %lu dwords have %lu dwords\n",
3364                                         prim_walk, i, size >> 2,
3365                                         radeon_bo_size(track->arrays[i].robj)
3366                                         >> 2);
3367                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3368                                 return -EINVAL;
3369                         }
3370                 }
3371                 break;
3372         case 2:
3373                 for (i = 0; i < track->num_arrays; i++) {
3374                         size = track->arrays[i].esize * (nverts - 1) * 4;
3375                         if (track->arrays[i].robj == NULL) {
3376                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3377                                           "bound\n", prim_walk, i);
3378                                 return -EINVAL;
3379                         }
3380                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3381                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3382                                         "need %lu dwords have %lu dwords\n",
3383                                         prim_walk, i, size >> 2,
3384                                         radeon_bo_size(track->arrays[i].robj)
3385                                         >> 2);
3386                                 return -EINVAL;
3387                         }
3388                 }
3389                 break;
3390         case 3:
3391                 size = track->vtx_size * nverts;
3392                 if (size != track->immd_dwords) {
3393                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3394                                   track->immd_dwords, size);
3395                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3396                                   nverts, track->vtx_size);
3397                         return -EINVAL;
3398                 }
3399                 break;
3400         default:
3401                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3402                           prim_walk);
3403                 return -EINVAL;
3404         }
3405         return r100_cs_track_texture_check(rdev, track);
3406 }
3407
3408 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3409 {
3410         unsigned i, face;
3411
3412         if (rdev->family < CHIP_R300) {
3413                 track->num_cb = 1;
3414                 if (rdev->family <= CHIP_RS200)
3415                         track->num_texture = 3;
3416                 else
3417                         track->num_texture = 6;
3418                 track->maxy = 2048;
3419                 track->separate_cube = 1;
3420         } else {
3421                 track->num_cb = 4;
3422                 track->num_texture = 16;
3423                 track->maxy = 4096;
3424                 track->separate_cube = 0;
3425         }
3426
3427         for (i = 0; i < track->num_cb; i++) {
3428                 track->cb[i].robj = NULL;
3429                 track->cb[i].pitch = 8192;
3430                 track->cb[i].cpp = 16;
3431                 track->cb[i].offset = 0;
3432         }
3433         track->z_enabled = true;
3434         track->zb.robj = NULL;
3435         track->zb.pitch = 8192;
3436         track->zb.cpp = 4;
3437         track->zb.offset = 0;
3438         track->vtx_size = 0x7F;
3439         track->immd_dwords = 0xFFFFFFFFUL;
3440         track->num_arrays = 11;
3441         track->max_indx = 0x00FFFFFFUL;
3442         for (i = 0; i < track->num_arrays; i++) {
3443                 track->arrays[i].robj = NULL;
3444                 track->arrays[i].esize = 0x7F;
3445         }
3446         for (i = 0; i < track->num_texture; i++) {
3447                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3448                 track->textures[i].pitch = 16536;
3449                 track->textures[i].width = 16536;
3450                 track->textures[i].height = 16536;
3451                 track->textures[i].width_11 = 1 << 11;
3452                 track->textures[i].height_11 = 1 << 11;
3453                 track->textures[i].num_levels = 12;
3454                 if (rdev->family <= CHIP_RS200) {
3455                         track->textures[i].tex_coord_type = 0;
3456                         track->textures[i].txdepth = 0;
3457                 } else {
3458                         track->textures[i].txdepth = 16;
3459                         track->textures[i].tex_coord_type = 1;
3460                 }
3461                 track->textures[i].cpp = 64;
3462                 track->textures[i].robj = NULL;
3463                 /* CS IB emission code makes sure texture unit are disabled */
3464                 track->textures[i].enabled = false;
3465                 track->textures[i].roundup_w = true;
3466                 track->textures[i].roundup_h = true;
3467                 if (track->separate_cube)
3468                         for (face = 0; face < 5; face++) {
3469                                 track->textures[i].cube_info[face].robj = NULL;
3470                                 track->textures[i].cube_info[face].width = 16536;
3471                                 track->textures[i].cube_info[face].height = 16536;
3472                                 track->textures[i].cube_info[face].offset = 0;
3473                         }
3474         }
3475 }
3476
3477 int r100_ring_test(struct radeon_device *rdev)
3478 {
3479         uint32_t scratch;
3480         uint32_t tmp = 0;
3481         unsigned i;
3482         int r;
3483
3484         r = radeon_scratch_get(rdev, &scratch);
3485         if (r) {
3486                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3487                 return r;
3488         }
3489         WREG32(scratch, 0xCAFEDEAD);
3490         r = radeon_ring_lock(rdev, 2);
3491         if (r) {
3492                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3493                 radeon_scratch_free(rdev, scratch);
3494                 return r;
3495         }
3496         radeon_ring_write(rdev, PACKET0(scratch, 0));
3497         radeon_ring_write(rdev, 0xDEADBEEF);
3498         radeon_ring_unlock_commit(rdev);
3499         for (i = 0; i < rdev->usec_timeout; i++) {
3500                 tmp = RREG32(scratch);
3501                 if (tmp == 0xDEADBEEF) {
3502                         break;
3503                 }
3504                 DRM_UDELAY(1);
3505         }
3506         if (i < rdev->usec_timeout) {
3507                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3508         } else {
3509                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3510                           scratch, tmp);
3511                 r = -EINVAL;
3512         }
3513         radeon_scratch_free(rdev, scratch);
3514         return r;
3515 }
3516
3517 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3518 {
3519         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3520         radeon_ring_write(rdev, ib->gpu_addr);
3521         radeon_ring_write(rdev, ib->length_dw);
3522 }
3523
3524 int r100_ib_test(struct radeon_device *rdev)
3525 {
3526         struct radeon_ib *ib;
3527         uint32_t scratch;
3528         uint32_t tmp = 0;
3529         unsigned i;
3530         int r;
3531
3532         r = radeon_scratch_get(rdev, &scratch);
3533         if (r) {
3534                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3535                 return r;
3536         }
3537         WREG32(scratch, 0xCAFEDEAD);
3538         r = radeon_ib_get(rdev, &ib);
3539         if (r) {
3540                 return r;
3541         }
3542         ib->ptr[0] = PACKET0(scratch, 0);
3543         ib->ptr[1] = 0xDEADBEEF;
3544         ib->ptr[2] = PACKET2(0);
3545         ib->ptr[3] = PACKET2(0);
3546         ib->ptr[4] = PACKET2(0);
3547         ib->ptr[5] = PACKET2(0);
3548         ib->ptr[6] = PACKET2(0);
3549         ib->ptr[7] = PACKET2(0);
3550         ib->length_dw = 8;
3551         r = radeon_ib_schedule(rdev, ib);
3552         if (r) {
3553                 radeon_scratch_free(rdev, scratch);
3554                 radeon_ib_free(rdev, &ib);
3555                 return r;
3556         }
3557         r = radeon_fence_wait(ib->fence, false);
3558         if (r) {
3559                 return r;
3560         }
3561         for (i = 0; i < rdev->usec_timeout; i++) {
3562                 tmp = RREG32(scratch);
3563                 if (tmp == 0xDEADBEEF) {
3564                         break;
3565                 }
3566                 DRM_UDELAY(1);
3567         }
3568         if (i < rdev->usec_timeout) {
3569                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3570         } else {
3571                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3572                           scratch, tmp);
3573                 r = -EINVAL;
3574         }
3575         radeon_scratch_free(rdev, scratch);
3576         radeon_ib_free(rdev, &ib);
3577         return r;
3578 }
3579
3580 void r100_ib_fini(struct radeon_device *rdev)
3581 {
3582         radeon_ib_pool_fini(rdev);
3583 }
3584
3585 int r100_ib_init(struct radeon_device *rdev)
3586 {
3587         int r;
3588
3589         r = radeon_ib_pool_init(rdev);
3590         if (r) {
3591                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3592                 r100_ib_fini(rdev);
3593                 return r;
3594         }
3595         r = r100_ib_test(rdev);
3596         if (r) {
3597                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3598                 r100_ib_fini(rdev);
3599                 return r;
3600         }
3601         return 0;
3602 }
3603
3604 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3605 {
3606         /* Shutdown CP we shouldn't need to do that but better be safe than
3607          * sorry
3608          */
3609         rdev->cp.ready = false;
3610         WREG32(R_000740_CP_CSQ_CNTL, 0);
3611
3612         /* Save few CRTC registers */
3613         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3614         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3615         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3616         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3617         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3618                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3619                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3620         }
3621
3622         /* Disable VGA aperture access */
3623         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3624         /* Disable cursor, overlay, crtc */
3625         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3626         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3627                                         S_000054_CRTC_DISPLAY_DIS(1));
3628         WREG32(R_000050_CRTC_GEN_CNTL,
3629                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3630                         S_000050_CRTC_DISP_REQ_EN_B(1));
3631         WREG32(R_000420_OV0_SCALE_CNTL,
3632                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3633         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3634         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3635                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3636                                                 S_000360_CUR2_LOCK(1));
3637                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3638                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3639                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3640                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3641                 WREG32(R_000360_CUR2_OFFSET,
3642                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3643         }
3644 }
3645
3646 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3647 {
3648         /* Update base address for crtc */
3649         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3650         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3651                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3652         }
3653         /* Restore CRTC registers */
3654         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3655         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3656         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3657         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3658                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3659         }
3660 }
3661
3662 void r100_vga_render_disable(struct radeon_device *rdev)
3663 {
3664         u32 tmp;
3665
3666         tmp = RREG8(R_0003C2_GENMO_WT);
3667         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3668 }
3669
3670 static void r100_debugfs(struct radeon_device *rdev)
3671 {
3672         int r;
3673
3674         r = r100_debugfs_mc_info_init(rdev);
3675         if (r)
3676                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3677 }
3678
3679 static void r100_mc_program(struct radeon_device *rdev)
3680 {
3681         struct r100_mc_save save;
3682
3683         /* Stops all mc clients */
3684         r100_mc_stop(rdev, &save);
3685         if (rdev->flags & RADEON_IS_AGP) {
3686                 WREG32(R_00014C_MC_AGP_LOCATION,
3687                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3688                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3689                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3690                 if (rdev->family > CHIP_RV200)
3691                         WREG32(R_00015C_AGP_BASE_2,
3692                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3693         } else {
3694                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3695                 WREG32(R_000170_AGP_BASE, 0);
3696                 if (rdev->family > CHIP_RV200)
3697                         WREG32(R_00015C_AGP_BASE_2, 0);
3698         }
3699         /* Wait for mc idle */
3700         if (r100_mc_wait_for_idle(rdev))
3701                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3702         /* Program MC, should be a 32bits limited address space */
3703         WREG32(R_000148_MC_FB_LOCATION,
3704                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3705                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3706         r100_mc_resume(rdev, &save);
3707 }
3708
3709 void r100_clock_startup(struct radeon_device *rdev)
3710 {
3711         u32 tmp;
3712
3713         if (radeon_dynclks != -1 && radeon_dynclks)
3714                 radeon_legacy_set_clock_gating(rdev, 1);
3715         /* We need to force on some of the block */
3716         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3717         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3718         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3719                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3720         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3721 }
3722
3723 static int r100_startup(struct radeon_device *rdev)
3724 {
3725         int r;
3726
3727         /* set common regs */
3728         r100_set_common_regs(rdev);
3729         /* program mc */
3730         r100_mc_program(rdev);
3731         /* Resume clock */
3732         r100_clock_startup(rdev);
3733         /* Initialize GPU configuration (# pipes, ...) */
3734 //      r100_gpu_init(rdev);
3735         /* Initialize GART (initialize after TTM so we can allocate
3736          * memory through TTM but finalize after TTM) */
3737         r100_enable_bm(rdev);
3738         if (rdev->flags & RADEON_IS_PCI) {
3739                 r = r100_pci_gart_enable(rdev);
3740                 if (r)
3741                         return r;
3742         }
3743         /* Enable IRQ */
3744         r100_irq_set(rdev);
3745         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3746         /* 1M ring buffer */
3747         r = r100_cp_init(rdev, 1024 * 1024);
3748         if (r) {
3749                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3750                 return r;
3751         }
3752         r = r100_wb_init(rdev);
3753         if (r)
3754                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3755         r = r100_ib_init(rdev);
3756         if (r) {
3757                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3758                 return r;
3759         }
3760         return 0;
3761 }
3762
3763 int r100_resume(struct radeon_device *rdev)
3764 {
3765         /* Make sur GART are not working */
3766         if (rdev->flags & RADEON_IS_PCI)
3767                 r100_pci_gart_disable(rdev);
3768         /* Resume clock before doing reset */
3769         r100_clock_startup(rdev);
3770         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3771         if (radeon_asic_reset(rdev)) {
3772                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3773                         RREG32(R_000E40_RBBM_STATUS),
3774                         RREG32(R_0007C0_CP_STAT));
3775         }
3776         /* post */
3777         radeon_combios_asic_init(rdev->ddev);
3778         /* Resume clock after posting */
3779         r100_clock_startup(rdev);
3780         /* Initialize surface registers */
3781         radeon_surface_init(rdev);
3782         return r100_startup(rdev);
3783 }
3784
3785 int r100_suspend(struct radeon_device *rdev)
3786 {
3787         r100_cp_disable(rdev);
3788         r100_wb_disable(rdev);
3789         r100_irq_disable(rdev);
3790         if (rdev->flags & RADEON_IS_PCI)
3791                 r100_pci_gart_disable(rdev);
3792         return 0;
3793 }
3794
3795 void r100_fini(struct radeon_device *rdev)
3796 {
3797         radeon_pm_fini(rdev);
3798         r100_cp_fini(rdev);
3799         r100_wb_fini(rdev);
3800         r100_ib_fini(rdev);
3801         radeon_gem_fini(rdev);
3802         if (rdev->flags & RADEON_IS_PCI)
3803                 r100_pci_gart_fini(rdev);
3804         radeon_agp_fini(rdev);
3805         radeon_irq_kms_fini(rdev);
3806         radeon_fence_driver_fini(rdev);
3807         radeon_bo_fini(rdev);
3808         radeon_atombios_fini(rdev);
3809         kfree(rdev->bios);
3810         rdev->bios = NULL;
3811 }
3812
3813 int r100_init(struct radeon_device *rdev)
3814 {
3815         int r;
3816
3817         /* Register debugfs file specific to this group of asics */
3818         r100_debugfs(rdev);
3819         /* Disable VGA */
3820         r100_vga_render_disable(rdev);
3821         /* Initialize scratch registers */
3822         radeon_scratch_init(rdev);
3823         /* Initialize surface registers */
3824         radeon_surface_init(rdev);
3825         /* TODO: disable VGA need to use VGA request */
3826         /* BIOS*/
3827         if (!radeon_get_bios(rdev)) {
3828                 if (ASIC_IS_AVIVO(rdev))
3829                         return -EINVAL;
3830         }
3831         if (rdev->is_atom_bios) {
3832                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3833                 return -EINVAL;
3834         } else {
3835                 r = radeon_combios_init(rdev);
3836                 if (r)
3837                         return r;
3838         }
3839         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3840         if (radeon_asic_reset(rdev)) {
3841                 dev_warn(rdev->dev,
3842                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3843                         RREG32(R_000E40_RBBM_STATUS),
3844                         RREG32(R_0007C0_CP_STAT));
3845         }
3846         /* check if cards are posted or not */
3847         if (radeon_boot_test_post_card(rdev) == false)
3848                 return -EINVAL;
3849         /* Set asic errata */
3850         r100_errata(rdev);
3851         /* Initialize clocks */
3852         radeon_get_clock_info(rdev->ddev);
3853         /* Initialize power management */
3854         radeon_pm_init(rdev);
3855         /* initialize AGP */
3856         if (rdev->flags & RADEON_IS_AGP) {
3857                 r = radeon_agp_init(rdev);
3858                 if (r) {
3859                         radeon_agp_disable(rdev);
3860                 }
3861         }
3862         /* initialize VRAM */
3863         r100_mc_init(rdev);
3864         /* Fence driver */
3865         r = radeon_fence_driver_init(rdev);
3866         if (r)
3867                 return r;
3868         r = radeon_irq_kms_init(rdev);
3869         if (r)
3870                 return r;
3871         /* Memory manager */
3872         r = radeon_bo_init(rdev);
3873         if (r)
3874                 return r;
3875         if (rdev->flags & RADEON_IS_PCI) {
3876                 r = r100_pci_gart_init(rdev);
3877                 if (r)
3878                         return r;
3879         }
3880         r100_set_safe_registers(rdev);
3881         rdev->accel_working = true;
3882         r = r100_startup(rdev);
3883         if (r) {
3884                 /* Somethings want wront with the accel init stop accel */
3885                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3886                 r100_cp_fini(rdev);
3887                 r100_wb_fini(rdev);
3888                 r100_ib_fini(rdev);
3889                 radeon_irq_kms_fini(rdev);
3890                 if (rdev->flags & RADEON_IS_PCI)
3891                         r100_pci_gart_fini(rdev);
3892                 rdev->accel_working = false;
3893         }
3894         return 0;
3895 }