2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
62 #include "r100_track.h"
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71 bool connected = false;
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
88 void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
92 bool connected = r100_hpd_sense(rdev, hpd);
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
116 void r100_hpd_init(struct radeon_device *rdev)
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
125 rdev->irq.hpd[0] = true;
128 rdev->irq.hpd[1] = true;
134 if (rdev->irq.installed)
138 void r100_hpd_fini(struct radeon_device *rdev)
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
147 rdev->irq.hpd[0] = false;
150 rdev->irq.hpd[1] = false;
161 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
169 int r100_pci_gart_init(struct radeon_device *rdev)
173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188 void r100_enable_bm(struct radeon_device *rdev)
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
196 int r100_pci_gart_enable(struct radeon_device *rdev)
200 radeon_gart_restore(rdev);
201 /* discard memory request outside of configured range */
202 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
203 WREG32(RADEON_AIC_CNTL, tmp);
204 /* set address range for PCI address translate */
205 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
206 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
216 void r100_pci_gart_disable(struct radeon_device *rdev)
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
227 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
236 void r100_pci_gart_fini(struct radeon_device *rdev)
238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
243 int r100_irq_set(struct radeon_device *rdev)
247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
267 WREG32(RADEON_GEN_INT_CNTL, tmp);
271 void r100_irq_disable(struct radeon_device *rdev)
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
282 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
292 return irqs & irq_mask;
295 int r100_irq_process(struct radeon_device *rdev)
297 uint32_t status, msi_rearm;
298 bool queue_hotplug = false;
300 status = r100_irq_ack(rdev);
304 if (rdev->shutdown) {
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
315 wake_up(&rdev->irq.vblank_queue);
317 if (status & RADEON_CRTC2_VBLANK_STAT) {
318 drm_handle_vblank(rdev->ddev, 1);
319 wake_up(&rdev->irq.vblank_queue);
321 if (status & RADEON_FP_DETECT_STAT) {
322 queue_hotplug = true;
325 if (status & RADEON_FP2_DETECT_STAT) {
326 queue_hotplug = true;
329 status = r100_irq_ack(rdev);
332 queue_work(rdev->wq, &rdev->hotplug_work);
333 if (rdev->msi_enabled) {
334 switch (rdev->family) {
337 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
338 WREG32(RADEON_AIC_CNTL, msi_rearm);
339 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
342 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
343 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
344 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
351 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
354 return RREG32(RADEON_CRTC_CRNT_FRAME);
356 return RREG32(RADEON_CRTC2_CRNT_FRAME);
359 /* Who ever call radeon_fence_emit should call ring_lock and ask
360 * for enough space (today caller are ib schedule and buffer move) */
361 void r100_fence_ring_emit(struct radeon_device *rdev,
362 struct radeon_fence *fence)
364 /* We have to make sure that caches are flushed before
365 * CPU might read something from VRAM. */
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
368 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
369 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
370 /* Wait until IDLE & CLEAN */
371 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
372 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
373 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
374 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
375 RADEON_HDP_READ_BUFFER_INVALIDATE);
376 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
377 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
378 /* Emit fence sequence & fire IRQ */
379 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
380 radeon_ring_write(rdev, fence->seq);
381 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
382 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
385 int r100_wb_init(struct radeon_device *rdev)
389 if (rdev->wb.wb_obj == NULL) {
390 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
391 RADEON_GEM_DOMAIN_GTT,
394 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
397 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
398 if (unlikely(r != 0))
400 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
403 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
404 radeon_bo_unreserve(rdev->wb.wb_obj);
407 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
408 radeon_bo_unreserve(rdev->wb.wb_obj);
410 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
414 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
415 WREG32(R_00070C_CP_RB_RPTR_ADDR,
416 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
417 WREG32(R_000770_SCRATCH_UMSK, 0xff);
421 void r100_wb_disable(struct radeon_device *rdev)
423 WREG32(R_000770_SCRATCH_UMSK, 0);
426 void r100_wb_fini(struct radeon_device *rdev)
430 r100_wb_disable(rdev);
431 if (rdev->wb.wb_obj) {
432 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
433 if (unlikely(r != 0)) {
434 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
437 radeon_bo_kunmap(rdev->wb.wb_obj);
438 radeon_bo_unpin(rdev->wb.wb_obj);
439 radeon_bo_unreserve(rdev->wb.wb_obj);
440 radeon_bo_unref(&rdev->wb.wb_obj);
442 rdev->wb.wb_obj = NULL;
446 int r100_copy_blit(struct radeon_device *rdev,
450 struct radeon_fence *fence)
453 uint32_t stride_bytes = PAGE_SIZE;
455 uint32_t stride_pixels;
460 /* radeon limited to 16k stride */
461 stride_bytes &= 0x3fff;
462 /* radeon pitch is /64 */
463 pitch = stride_bytes / 64;
464 stride_pixels = stride_bytes / 4;
465 num_loops = DIV_ROUND_UP(num_pages, 8191);
467 /* Ask for enough room for blit + flush + fence */
468 ndw = 64 + (10 * num_loops);
469 r = radeon_ring_lock(rdev, ndw);
471 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
474 while (num_pages > 0) {
475 cur_pages = num_pages;
476 if (cur_pages > 8191) {
479 num_pages -= cur_pages;
481 /* pages are in Y direction - height
482 page width in X direction - width */
483 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
484 radeon_ring_write(rdev,
485 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
486 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
487 RADEON_GMC_SRC_CLIPPING |
488 RADEON_GMC_DST_CLIPPING |
489 RADEON_GMC_BRUSH_NONE |
490 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
491 RADEON_GMC_SRC_DATATYPE_COLOR |
493 RADEON_DP_SRC_SOURCE_MEMORY |
494 RADEON_GMC_CLR_CMP_CNTL_DIS |
495 RADEON_GMC_WR_MSK_DIS);
496 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
497 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
498 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
499 radeon_ring_write(rdev, 0);
500 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
501 radeon_ring_write(rdev, num_pages);
502 radeon_ring_write(rdev, num_pages);
503 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
505 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
506 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
507 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
508 radeon_ring_write(rdev,
509 RADEON_WAIT_2D_IDLECLEAN |
510 RADEON_WAIT_HOST_IDLECLEAN |
511 RADEON_WAIT_DMA_GUI_IDLE);
513 r = radeon_fence_emit(rdev, fence);
515 radeon_ring_unlock_commit(rdev);
519 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
524 for (i = 0; i < rdev->usec_timeout; i++) {
525 tmp = RREG32(R_000E40_RBBM_STATUS);
526 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
534 void r100_ring_start(struct radeon_device *rdev)
538 r = radeon_ring_lock(rdev, 2);
542 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
543 radeon_ring_write(rdev,
544 RADEON_ISYNC_ANY2D_IDLE3D |
545 RADEON_ISYNC_ANY3D_IDLE2D |
546 RADEON_ISYNC_WAIT_IDLEGUI |
547 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
548 radeon_ring_unlock_commit(rdev);
552 /* Load the microcode for the CP */
553 static int r100_cp_init_microcode(struct radeon_device *rdev)
555 struct platform_device *pdev;
556 const char *fw_name = NULL;
561 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
564 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
567 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
568 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
569 (rdev->family == CHIP_RS200)) {
570 DRM_INFO("Loading R100 Microcode\n");
571 fw_name = FIRMWARE_R100;
572 } else if ((rdev->family == CHIP_R200) ||
573 (rdev->family == CHIP_RV250) ||
574 (rdev->family == CHIP_RV280) ||
575 (rdev->family == CHIP_RS300)) {
576 DRM_INFO("Loading R200 Microcode\n");
577 fw_name = FIRMWARE_R200;
578 } else if ((rdev->family == CHIP_R300) ||
579 (rdev->family == CHIP_R350) ||
580 (rdev->family == CHIP_RV350) ||
581 (rdev->family == CHIP_RV380) ||
582 (rdev->family == CHIP_RS400) ||
583 (rdev->family == CHIP_RS480)) {
584 DRM_INFO("Loading R300 Microcode\n");
585 fw_name = FIRMWARE_R300;
586 } else if ((rdev->family == CHIP_R420) ||
587 (rdev->family == CHIP_R423) ||
588 (rdev->family == CHIP_RV410)) {
589 DRM_INFO("Loading R400 Microcode\n");
590 fw_name = FIRMWARE_R420;
591 } else if ((rdev->family == CHIP_RS690) ||
592 (rdev->family == CHIP_RS740)) {
593 DRM_INFO("Loading RS690/RS740 Microcode\n");
594 fw_name = FIRMWARE_RS690;
595 } else if (rdev->family == CHIP_RS600) {
596 DRM_INFO("Loading RS600 Microcode\n");
597 fw_name = FIRMWARE_RS600;
598 } else if ((rdev->family == CHIP_RV515) ||
599 (rdev->family == CHIP_R520) ||
600 (rdev->family == CHIP_RV530) ||
601 (rdev->family == CHIP_R580) ||
602 (rdev->family == CHIP_RV560) ||
603 (rdev->family == CHIP_RV570)) {
604 DRM_INFO("Loading R500 Microcode\n");
605 fw_name = FIRMWARE_R520;
608 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
609 platform_device_unregister(pdev);
611 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
613 } else if (rdev->me_fw->size % 8) {
615 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
616 rdev->me_fw->size, fw_name);
618 release_firmware(rdev->me_fw);
624 static void r100_cp_load_microcode(struct radeon_device *rdev)
626 const __be32 *fw_data;
629 if (r100_gui_wait_for_idle(rdev)) {
630 printk(KERN_WARNING "Failed to wait GUI idle while "
631 "programming pipes. Bad things might happen.\n");
635 size = rdev->me_fw->size / 4;
636 fw_data = (const __be32 *)&rdev->me_fw->data[0];
637 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
638 for (i = 0; i < size; i += 2) {
639 WREG32(RADEON_CP_ME_RAM_DATAH,
640 be32_to_cpup(&fw_data[i]));
641 WREG32(RADEON_CP_ME_RAM_DATAL,
642 be32_to_cpup(&fw_data[i + 1]));
647 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
652 unsigned pre_write_timer;
653 unsigned pre_write_limit;
654 unsigned indirect2_start;
655 unsigned indirect1_start;
659 if (r100_debugfs_cp_init(rdev)) {
660 DRM_ERROR("Failed to register debugfs file for CP !\n");
663 tmp = RREG32(RADEON_CP_CSQ_STAT);
664 if ((tmp & (1 << 31))) {
665 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
666 WREG32(RADEON_CP_CSQ_MODE, 0);
667 WREG32(RADEON_CP_CSQ_CNTL, 0);
668 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
669 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
671 WREG32(RADEON_RBBM_SOFT_RESET, 0);
672 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
674 tmp = RREG32(RADEON_CP_CSQ_STAT);
675 if ((tmp & (1 << 31))) {
676 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
679 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
683 r = r100_cp_init_microcode(rdev);
685 DRM_ERROR("Failed to load firmware!\n");
690 /* Align ring size */
691 rb_bufsz = drm_order(ring_size / 8);
692 ring_size = (1 << (rb_bufsz + 1)) * 4;
693 r100_cp_load_microcode(rdev);
694 r = radeon_ring_init(rdev, ring_size);
698 /* Each time the cp read 1024 bytes (16 dword/quadword) update
699 * the rptr copy in system ram */
701 /* cp will read 128bytes at a time (4 dwords) */
703 rdev->cp.align_mask = 16 - 1;
704 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
705 pre_write_timer = 64;
706 /* Force CP_RB_WPTR write if written more than one time before the
710 /* Setup the cp cache like this (cache size is 96 dwords) :
714 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
715 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
716 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
717 * Idea being that most of the gpu cmd will be through indirect1 buffer
718 * so it gets the bigger cache.
720 indirect2_start = 80;
721 indirect1_start = 16;
723 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
724 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
725 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
726 REG_SET(RADEON_MAX_FETCH, max_fetch) |
727 RADEON_RB_NO_UPDATE);
729 tmp |= RADEON_BUF_SWAP_32BIT;
731 WREG32(RADEON_CP_RB_CNTL, tmp);
733 /* Set ring address */
734 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
735 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
736 /* Force read & write ptr to 0 */
737 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
738 WREG32(RADEON_CP_RB_RPTR_WR, 0);
739 WREG32(RADEON_CP_RB_WPTR, 0);
740 WREG32(RADEON_CP_RB_CNTL, tmp);
742 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
743 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
744 /* Set cp mode to bus mastering & enable cp*/
745 WREG32(RADEON_CP_CSQ_MODE,
746 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
747 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
749 WREG32(0x744, 0x00004D4D);
750 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
751 radeon_ring_start(rdev);
752 r = radeon_ring_test(rdev);
754 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
757 rdev->cp.ready = true;
761 void r100_cp_fini(struct radeon_device *rdev)
763 if (r100_cp_wait_for_idle(rdev)) {
764 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
767 r100_cp_disable(rdev);
768 radeon_ring_fini(rdev);
769 DRM_INFO("radeon: cp finalized\n");
772 void r100_cp_disable(struct radeon_device *rdev)
775 rdev->cp.ready = false;
776 WREG32(RADEON_CP_CSQ_MODE, 0);
777 WREG32(RADEON_CP_CSQ_CNTL, 0);
778 if (r100_gui_wait_for_idle(rdev)) {
779 printk(KERN_WARNING "Failed to wait GUI idle while "
780 "programming pipes. Bad things might happen.\n");
784 int r100_cp_reset(struct radeon_device *rdev)
790 reinit_cp = rdev->cp.ready;
791 rdev->cp.ready = false;
792 WREG32(RADEON_CP_CSQ_MODE, 0);
793 WREG32(RADEON_CP_CSQ_CNTL, 0);
794 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
795 (void)RREG32(RADEON_RBBM_SOFT_RESET);
797 WREG32(RADEON_RBBM_SOFT_RESET, 0);
798 /* Wait to prevent race in RBBM_STATUS */
800 for (i = 0; i < rdev->usec_timeout; i++) {
801 tmp = RREG32(RADEON_RBBM_STATUS);
802 if (!(tmp & (1 << 16))) {
803 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
806 return r100_cp_init(rdev, rdev->cp.ring_size);
812 tmp = RREG32(RADEON_RBBM_STATUS);
813 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
817 void r100_cp_commit(struct radeon_device *rdev)
819 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
820 (void)RREG32(RADEON_CP_RB_WPTR);
827 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
828 struct radeon_cs_packet *pkt,
829 const unsigned *auth, unsigned n,
830 radeon_packet0_check_t check)
839 /* Check that register fall into register range
840 * determined by the number of entry (n) in the
841 * safe register bitmap.
843 if (pkt->one_reg_wr) {
844 if ((reg >> 7) > n) {
848 if (((reg + (pkt->count << 2)) >> 7) > n) {
852 for (i = 0; i <= pkt->count; i++, idx++) {
854 m = 1 << ((reg >> 2) & 31);
856 r = check(p, pkt, idx, reg);
861 if (pkt->one_reg_wr) {
862 if (!(auth[j] & m)) {
872 void r100_cs_dump_packet(struct radeon_cs_parser *p,
873 struct radeon_cs_packet *pkt)
875 volatile uint32_t *ib;
881 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
882 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
887 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
888 * @parser: parser structure holding parsing context.
889 * @pkt: where to store packet informations
891 * Assume that chunk_ib_index is properly set. Will return -EINVAL
892 * if packet is bigger than remaining ib size. or if packets is unknown.
894 int r100_cs_packet_parse(struct radeon_cs_parser *p,
895 struct radeon_cs_packet *pkt,
898 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
901 if (idx >= ib_chunk->length_dw) {
902 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
903 idx, ib_chunk->length_dw);
906 header = radeon_get_ib_value(p, idx);
908 pkt->type = CP_PACKET_GET_TYPE(header);
909 pkt->count = CP_PACKET_GET_COUNT(header);
912 pkt->reg = CP_PACKET0_GET_REG(header);
913 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
916 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
922 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
925 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
926 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
927 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
934 * r100_cs_packet_next_vline() - parse userspace VLINE packet
935 * @parser: parser structure holding parsing context.
937 * Userspace sends a special sequence for VLINE waits.
938 * PACKET0 - VLINE_START_END + value
939 * PACKET0 - WAIT_UNTIL +_value
940 * RELOC (P3) - crtc_id in reloc.
942 * This function parses this and relocates the VLINE START END
943 * and WAIT UNTIL packets to the correct crtc.
944 * It also detects a switched off crtc and nulls out the
947 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
949 struct drm_mode_object *obj;
950 struct drm_crtc *crtc;
951 struct radeon_crtc *radeon_crtc;
952 struct radeon_cs_packet p3reloc, waitreloc;
955 uint32_t header, h_idx, reg;
956 volatile uint32_t *ib;
960 /* parse the wait until */
961 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
965 /* check its a wait until and only 1 count */
966 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
967 waitreloc.count != 0) {
968 DRM_ERROR("vline wait had illegal wait until segment\n");
973 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
974 DRM_ERROR("vline wait had illegal wait until\n");
979 /* jump over the NOP */
980 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
985 p->idx += waitreloc.count + 2;
986 p->idx += p3reloc.count + 2;
988 header = radeon_get_ib_value(p, h_idx);
989 crtc_id = radeon_get_ib_value(p, h_idx + 5);
990 reg = CP_PACKET0_GET_REG(header);
991 mutex_lock(&p->rdev->ddev->mode_config.mutex);
992 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
994 DRM_ERROR("cannot find crtc %d\n", crtc_id);
998 crtc = obj_to_crtc(obj);
999 radeon_crtc = to_radeon_crtc(crtc);
1000 crtc_id = radeon_crtc->crtc_id;
1002 if (!crtc->enabled) {
1003 /* if the CRTC isn't enabled - we need to nop out the wait until */
1004 ib[h_idx + 2] = PACKET2(0);
1005 ib[h_idx + 3] = PACKET2(0);
1006 } else if (crtc_id == 1) {
1008 case AVIVO_D1MODE_VLINE_START_END:
1009 header &= ~R300_CP_PACKET0_REG_MASK;
1010 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1012 case RADEON_CRTC_GUI_TRIG_VLINE:
1013 header &= ~R300_CP_PACKET0_REG_MASK;
1014 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1017 DRM_ERROR("unknown crtc reloc\n");
1022 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1025 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1030 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1031 * @parser: parser structure holding parsing context.
1032 * @data: pointer to relocation data
1033 * @offset_start: starting offset
1034 * @offset_mask: offset mask (to align start offset on)
1035 * @reloc: reloc informations
1037 * Check next packet is relocation packet3, do bo validation and compute
1038 * GPU offset using the provided start.
1040 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1041 struct radeon_cs_reloc **cs_reloc)
1043 struct radeon_cs_chunk *relocs_chunk;
1044 struct radeon_cs_packet p3reloc;
1048 if (p->chunk_relocs_idx == -1) {
1049 DRM_ERROR("No relocation chunk !\n");
1053 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1054 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1058 p->idx += p3reloc.count + 2;
1059 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1060 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1062 r100_cs_dump_packet(p, &p3reloc);
1065 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1066 if (idx >= relocs_chunk->length_dw) {
1067 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1068 idx, relocs_chunk->length_dw);
1069 r100_cs_dump_packet(p, &p3reloc);
1072 /* FIXME: we assume reloc size is 4 dwords */
1073 *cs_reloc = p->relocs_ptr[(idx / 4)];
1077 static int r100_get_vtx_size(uint32_t vtx_fmt)
1081 /* ordered according to bits in spec */
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1113 if (vtx_fmt & (0x7 << 15))
1114 vtx_size += (vtx_fmt >> 15) & 0x7;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1119 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1121 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1123 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1125 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1130 static int r100_packet0_check(struct radeon_cs_parser *p,
1131 struct radeon_cs_packet *pkt,
1132 unsigned idx, unsigned reg)
1134 struct radeon_cs_reloc *reloc;
1135 struct r100_cs_track *track;
1136 volatile uint32_t *ib;
1144 track = (struct r100_cs_track *)p->track;
1146 idx_value = radeon_get_ib_value(p, idx);
1149 case RADEON_CRTC_GUI_TRIG_VLINE:
1150 r = r100_cs_packet_parse_vline(p);
1152 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1154 r100_cs_dump_packet(p, pkt);
1158 /* FIXME: only allow PACKET3 blit? easier to check for out of
1160 case RADEON_DST_PITCH_OFFSET:
1161 case RADEON_SRC_PITCH_OFFSET:
1162 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1166 case RADEON_RB3D_DEPTHOFFSET:
1167 r = r100_cs_packet_next_reloc(p, &reloc);
1169 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1171 r100_cs_dump_packet(p, pkt);
1174 track->zb.robj = reloc->robj;
1175 track->zb.offset = idx_value;
1176 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1178 case RADEON_RB3D_COLOROFFSET:
1179 r = r100_cs_packet_next_reloc(p, &reloc);
1181 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1183 r100_cs_dump_packet(p, pkt);
1186 track->cb[0].robj = reloc->robj;
1187 track->cb[0].offset = idx_value;
1188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1190 case RADEON_PP_TXOFFSET_0:
1191 case RADEON_PP_TXOFFSET_1:
1192 case RADEON_PP_TXOFFSET_2:
1193 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1194 r = r100_cs_packet_next_reloc(p, &reloc);
1196 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1198 r100_cs_dump_packet(p, pkt);
1201 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1202 track->textures[i].robj = reloc->robj;
1204 case RADEON_PP_CUBIC_OFFSET_T0_0:
1205 case RADEON_PP_CUBIC_OFFSET_T0_1:
1206 case RADEON_PP_CUBIC_OFFSET_T0_2:
1207 case RADEON_PP_CUBIC_OFFSET_T0_3:
1208 case RADEON_PP_CUBIC_OFFSET_T0_4:
1209 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1210 r = r100_cs_packet_next_reloc(p, &reloc);
1212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1214 r100_cs_dump_packet(p, pkt);
1217 track->textures[0].cube_info[i].offset = idx_value;
1218 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1219 track->textures[0].cube_info[i].robj = reloc->robj;
1221 case RADEON_PP_CUBIC_OFFSET_T1_0:
1222 case RADEON_PP_CUBIC_OFFSET_T1_1:
1223 case RADEON_PP_CUBIC_OFFSET_T1_2:
1224 case RADEON_PP_CUBIC_OFFSET_T1_3:
1225 case RADEON_PP_CUBIC_OFFSET_T1_4:
1226 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1227 r = r100_cs_packet_next_reloc(p, &reloc);
1229 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1231 r100_cs_dump_packet(p, pkt);
1234 track->textures[1].cube_info[i].offset = idx_value;
1235 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1236 track->textures[1].cube_info[i].robj = reloc->robj;
1238 case RADEON_PP_CUBIC_OFFSET_T2_0:
1239 case RADEON_PP_CUBIC_OFFSET_T2_1:
1240 case RADEON_PP_CUBIC_OFFSET_T2_2:
1241 case RADEON_PP_CUBIC_OFFSET_T2_3:
1242 case RADEON_PP_CUBIC_OFFSET_T2_4:
1243 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1244 r = r100_cs_packet_next_reloc(p, &reloc);
1246 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1248 r100_cs_dump_packet(p, pkt);
1251 track->textures[2].cube_info[i].offset = idx_value;
1252 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1253 track->textures[2].cube_info[i].robj = reloc->robj;
1255 case RADEON_RE_WIDTH_HEIGHT:
1256 track->maxy = ((idx_value >> 16) & 0x7FF);
1258 case RADEON_RB3D_COLORPITCH:
1259 r = r100_cs_packet_next_reloc(p, &reloc);
1261 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1263 r100_cs_dump_packet(p, pkt);
1267 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1268 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1269 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1270 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1272 tmp = idx_value & ~(0x7 << 16);
1276 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1278 case RADEON_RB3D_DEPTHPITCH:
1279 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1281 case RADEON_RB3D_CNTL:
1282 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1288 track->cb[0].cpp = 1;
1293 track->cb[0].cpp = 2;
1296 track->cb[0].cpp = 4;
1299 DRM_ERROR("Invalid color buffer format (%d) !\n",
1300 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1303 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1305 case RADEON_RB3D_ZSTENCILCNTL:
1306 switch (idx_value & 0xf) {
1322 case RADEON_RB3D_ZPASS_ADDR:
1323 r = r100_cs_packet_next_reloc(p, &reloc);
1325 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1327 r100_cs_dump_packet(p, pkt);
1330 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1332 case RADEON_PP_CNTL:
1334 uint32_t temp = idx_value >> 4;
1335 for (i = 0; i < track->num_texture; i++)
1336 track->textures[i].enabled = !!(temp & (1 << i));
1339 case RADEON_SE_VF_CNTL:
1340 track->vap_vf_cntl = idx_value;
1342 case RADEON_SE_VTX_FMT:
1343 track->vtx_size = r100_get_vtx_size(idx_value);
1345 case RADEON_PP_TEX_SIZE_0:
1346 case RADEON_PP_TEX_SIZE_1:
1347 case RADEON_PP_TEX_SIZE_2:
1348 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1349 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1350 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1352 case RADEON_PP_TEX_PITCH_0:
1353 case RADEON_PP_TEX_PITCH_1:
1354 case RADEON_PP_TEX_PITCH_2:
1355 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1356 track->textures[i].pitch = idx_value + 32;
1358 case RADEON_PP_TXFILTER_0:
1359 case RADEON_PP_TXFILTER_1:
1360 case RADEON_PP_TXFILTER_2:
1361 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1362 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1363 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1364 tmp = (idx_value >> 23) & 0x7;
1365 if (tmp == 2 || tmp == 6)
1366 track->textures[i].roundup_w = false;
1367 tmp = (idx_value >> 27) & 0x7;
1368 if (tmp == 2 || tmp == 6)
1369 track->textures[i].roundup_h = false;
1371 case RADEON_PP_TXFORMAT_0:
1372 case RADEON_PP_TXFORMAT_1:
1373 case RADEON_PP_TXFORMAT_2:
1374 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1375 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1376 track->textures[i].use_pitch = 1;
1378 track->textures[i].use_pitch = 0;
1379 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1380 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1382 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1383 track->textures[i].tex_coord_type = 2;
1384 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1385 case RADEON_TXFORMAT_I8:
1386 case RADEON_TXFORMAT_RGB332:
1387 case RADEON_TXFORMAT_Y8:
1388 track->textures[i].cpp = 1;
1390 case RADEON_TXFORMAT_AI88:
1391 case RADEON_TXFORMAT_ARGB1555:
1392 case RADEON_TXFORMAT_RGB565:
1393 case RADEON_TXFORMAT_ARGB4444:
1394 case RADEON_TXFORMAT_VYUY422:
1395 case RADEON_TXFORMAT_YVYU422:
1396 case RADEON_TXFORMAT_SHADOW16:
1397 case RADEON_TXFORMAT_LDUDV655:
1398 case RADEON_TXFORMAT_DUDV88:
1399 track->textures[i].cpp = 2;
1401 case RADEON_TXFORMAT_ARGB8888:
1402 case RADEON_TXFORMAT_RGBA8888:
1403 case RADEON_TXFORMAT_SHADOW32:
1404 case RADEON_TXFORMAT_LDUDUV8888:
1405 track->textures[i].cpp = 4;
1407 case RADEON_TXFORMAT_DXT1:
1408 track->textures[i].cpp = 1;
1409 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1411 case RADEON_TXFORMAT_DXT23:
1412 case RADEON_TXFORMAT_DXT45:
1413 track->textures[i].cpp = 1;
1414 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1417 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1418 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1420 case RADEON_PP_CUBIC_FACES_0:
1421 case RADEON_PP_CUBIC_FACES_1:
1422 case RADEON_PP_CUBIC_FACES_2:
1424 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1425 for (face = 0; face < 4; face++) {
1426 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1427 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1431 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1438 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1439 struct radeon_cs_packet *pkt,
1440 struct radeon_bo *robj)
1445 value = radeon_get_ib_value(p, idx + 2);
1446 if ((value + 1) > radeon_bo_size(robj)) {
1447 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1448 "(need %u have %lu) !\n",
1450 radeon_bo_size(robj));
1456 static int r100_packet3_check(struct radeon_cs_parser *p,
1457 struct radeon_cs_packet *pkt)
1459 struct radeon_cs_reloc *reloc;
1460 struct r100_cs_track *track;
1462 volatile uint32_t *ib;
1467 track = (struct r100_cs_track *)p->track;
1468 switch (pkt->opcode) {
1469 case PACKET3_3D_LOAD_VBPNTR:
1470 r = r100_packet3_load_vbpntr(p, pkt, idx);
1474 case PACKET3_INDX_BUFFER:
1475 r = r100_cs_packet_next_reloc(p, &reloc);
1477 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1478 r100_cs_dump_packet(p, pkt);
1481 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1482 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1488 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1489 r = r100_cs_packet_next_reloc(p, &reloc);
1491 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1492 r100_cs_dump_packet(p, pkt);
1495 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1496 track->num_arrays = 1;
1497 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1499 track->arrays[0].robj = reloc->robj;
1500 track->arrays[0].esize = track->vtx_size;
1502 track->max_indx = radeon_get_ib_value(p, idx+1);
1504 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1505 track->immd_dwords = pkt->count - 1;
1506 r = r100_cs_track_check(p->rdev, track);
1510 case PACKET3_3D_DRAW_IMMD:
1511 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1512 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1515 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1516 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1517 track->immd_dwords = pkt->count - 1;
1518 r = r100_cs_track_check(p->rdev, track);
1522 /* triggers drawing using in-packet vertex data */
1523 case PACKET3_3D_DRAW_IMMD_2:
1524 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1525 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1528 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1529 track->immd_dwords = pkt->count;
1530 r = r100_cs_track_check(p->rdev, track);
1534 /* triggers drawing using in-packet vertex data */
1535 case PACKET3_3D_DRAW_VBUF_2:
1536 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1537 r = r100_cs_track_check(p->rdev, track);
1541 /* triggers drawing of vertex buffers setup elsewhere */
1542 case PACKET3_3D_DRAW_INDX_2:
1543 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1544 r = r100_cs_track_check(p->rdev, track);
1548 /* triggers drawing using indices to vertex buffer */
1549 case PACKET3_3D_DRAW_VBUF:
1550 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1551 r = r100_cs_track_check(p->rdev, track);
1555 /* triggers drawing of vertex buffers setup elsewhere */
1556 case PACKET3_3D_DRAW_INDX:
1557 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1558 r = r100_cs_track_check(p->rdev, track);
1562 /* triggers drawing using indices to vertex buffer */
1566 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1572 int r100_cs_parse(struct radeon_cs_parser *p)
1574 struct radeon_cs_packet pkt;
1575 struct r100_cs_track *track;
1578 track = kzalloc(sizeof(*track), GFP_KERNEL);
1579 r100_cs_track_clear(p->rdev, track);
1582 r = r100_cs_packet_parse(p, &pkt, p->idx);
1586 p->idx += pkt.count + 2;
1589 if (p->rdev->family >= CHIP_R200)
1590 r = r100_cs_parse_packet0(p, &pkt,
1591 p->rdev->config.r100.reg_safe_bm,
1592 p->rdev->config.r100.reg_safe_bm_size,
1593 &r200_packet0_check);
1595 r = r100_cs_parse_packet0(p, &pkt,
1596 p->rdev->config.r100.reg_safe_bm,
1597 p->rdev->config.r100.reg_safe_bm_size,
1598 &r100_packet0_check);
1603 r = r100_packet3_check(p, &pkt);
1606 DRM_ERROR("Unknown packet type %d !\n",
1613 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1619 * Global GPU functions
1621 void r100_errata(struct radeon_device *rdev)
1623 rdev->pll_errata = 0;
1625 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1626 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1629 if (rdev->family == CHIP_RV100 ||
1630 rdev->family == CHIP_RS100 ||
1631 rdev->family == CHIP_RS200) {
1632 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1636 /* Wait for vertical sync on primary CRTC */
1637 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1639 uint32_t crtc_gen_cntl, tmp;
1642 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1643 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1644 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1647 /* Clear the CRTC_VBLANK_SAVE bit */
1648 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1649 for (i = 0; i < rdev->usec_timeout; i++) {
1650 tmp = RREG32(RADEON_CRTC_STATUS);
1651 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1658 /* Wait for vertical sync on secondary CRTC */
1659 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1661 uint32_t crtc2_gen_cntl, tmp;
1664 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1665 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1666 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1669 /* Clear the CRTC_VBLANK_SAVE bit */
1670 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1671 for (i = 0; i < rdev->usec_timeout; i++) {
1672 tmp = RREG32(RADEON_CRTC2_STATUS);
1673 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1680 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1685 for (i = 0; i < rdev->usec_timeout; i++) {
1686 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1695 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1700 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1701 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1702 " Bad things might happen.\n");
1704 for (i = 0; i < rdev->usec_timeout; i++) {
1705 tmp = RREG32(RADEON_RBBM_STATUS);
1706 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1714 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1719 for (i = 0; i < rdev->usec_timeout; i++) {
1720 /* read MC_STATUS */
1721 tmp = RREG32(RADEON_MC_STATUS);
1722 if (tmp & RADEON_MC_IDLE) {
1730 void r100_gpu_init(struct radeon_device *rdev)
1732 /* TODO: anythings to do here ? pipes ? */
1733 r100_hdp_reset(rdev);
1736 void r100_hdp_reset(struct radeon_device *rdev)
1740 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1742 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1743 (void)RREG32(RADEON_HOST_PATH_CNTL);
1745 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1746 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1747 (void)RREG32(RADEON_HOST_PATH_CNTL);
1750 int r100_rb2d_reset(struct radeon_device *rdev)
1755 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1756 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1758 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1759 /* Wait to prevent race in RBBM_STATUS */
1761 for (i = 0; i < rdev->usec_timeout; i++) {
1762 tmp = RREG32(RADEON_RBBM_STATUS);
1763 if (!(tmp & (1 << 26))) {
1764 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1770 tmp = RREG32(RADEON_RBBM_STATUS);
1771 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1775 int r100_gpu_reset(struct radeon_device *rdev)
1779 /* reset order likely matter */
1780 status = RREG32(RADEON_RBBM_STATUS);
1782 r100_hdp_reset(rdev);
1784 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1785 r100_rb2d_reset(rdev);
1787 /* TODO: reset 3D engine */
1789 status = RREG32(RADEON_RBBM_STATUS);
1790 if (status & (1 << 16)) {
1791 r100_cp_reset(rdev);
1793 /* Check if GPU is idle */
1794 status = RREG32(RADEON_RBBM_STATUS);
1795 if (status & RADEON_RBBM_ACTIVE) {
1796 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1799 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1803 void r100_set_common_regs(struct radeon_device *rdev)
1805 struct drm_device *dev = rdev->ddev;
1806 bool force_dac2 = false;
1808 /* set these so they don't interfere with anything */
1809 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1810 WREG32(RADEON_SUBPIC_CNTL, 0);
1811 WREG32(RADEON_VIPH_CONTROL, 0);
1812 WREG32(RADEON_I2C_CNTL_1, 0);
1813 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1814 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1815 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1817 /* always set up dac2 on rn50 and some rv100 as lots
1818 * of servers seem to wire it up to a VGA port but
1819 * don't report it in the bios connector
1822 switch (dev->pdev->device) {
1831 /* DELL triple head servers */
1832 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1833 ((dev->pdev->subsystem_device == 0x016c) ||
1834 (dev->pdev->subsystem_device == 0x016d) ||
1835 (dev->pdev->subsystem_device == 0x016e) ||
1836 (dev->pdev->subsystem_device == 0x016f) ||
1837 (dev->pdev->subsystem_device == 0x0170) ||
1838 (dev->pdev->subsystem_device == 0x017d) ||
1839 (dev->pdev->subsystem_device == 0x017e) ||
1840 (dev->pdev->subsystem_device == 0x0183) ||
1841 (dev->pdev->subsystem_device == 0x018a) ||
1842 (dev->pdev->subsystem_device == 0x019a)))
1848 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1849 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1850 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1852 /* For CRT on DAC2, don't turn it on if BIOS didn't
1853 enable it, even it's detected.
1856 /* force it to crtc0 */
1857 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1858 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1859 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1861 /* set up the TV DAC */
1862 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1863 RADEON_TV_DAC_STD_MASK |
1864 RADEON_TV_DAC_RDACPD |
1865 RADEON_TV_DAC_GDACPD |
1866 RADEON_TV_DAC_BDACPD |
1867 RADEON_TV_DAC_BGADJ_MASK |
1868 RADEON_TV_DAC_DACADJ_MASK);
1869 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1870 RADEON_TV_DAC_NHOLD |
1871 RADEON_TV_DAC_STD_PS2 |
1874 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1875 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1876 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1883 static void r100_vram_get_type(struct radeon_device *rdev)
1887 rdev->mc.vram_is_ddr = false;
1888 if (rdev->flags & RADEON_IS_IGP)
1889 rdev->mc.vram_is_ddr = true;
1890 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1891 rdev->mc.vram_is_ddr = true;
1892 if ((rdev->family == CHIP_RV100) ||
1893 (rdev->family == CHIP_RS100) ||
1894 (rdev->family == CHIP_RS200)) {
1895 tmp = RREG32(RADEON_MEM_CNTL);
1896 if (tmp & RV100_HALF_MODE) {
1897 rdev->mc.vram_width = 32;
1899 rdev->mc.vram_width = 64;
1901 if (rdev->flags & RADEON_SINGLE_CRTC) {
1902 rdev->mc.vram_width /= 4;
1903 rdev->mc.vram_is_ddr = true;
1905 } else if (rdev->family <= CHIP_RV280) {
1906 tmp = RREG32(RADEON_MEM_CNTL);
1907 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1908 rdev->mc.vram_width = 128;
1910 rdev->mc.vram_width = 64;
1914 rdev->mc.vram_width = 128;
1918 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1923 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1925 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1926 * that is has the 2nd generation multifunction PCI interface
1928 if (rdev->family == CHIP_RV280 ||
1929 rdev->family >= CHIP_RV350) {
1930 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1931 ~RADEON_HDP_APER_CNTL);
1932 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1933 return aper_size * 2;
1936 /* Older cards have all sorts of funny issues to deal with. First
1937 * check if it's a multifunction card by reading the PCI config
1938 * header type... Limit those to one aperture size
1940 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1942 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1943 DRM_INFO("Limiting VRAM to one aperture\n");
1947 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1948 * have set it up. We don't write this as it's broken on some ASICs but
1949 * we expect the BIOS to have done the right thing (might be too optimistic...)
1951 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1952 return aper_size * 2;
1956 void r100_vram_init_sizes(struct radeon_device *rdev)
1958 u64 config_aper_size;
1960 /* work out accessible VRAM */
1961 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1962 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1963 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1964 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1965 if (rdev->flags & RADEON_IS_IGP) {
1967 /* read NB_TOM to get the amount of ram stolen for the GPU */
1968 tom = RREG32(RADEON_NB_TOM);
1969 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1970 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1971 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1973 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1974 /* Some production boards of m6 will report 0
1977 if (rdev->mc.real_vram_size == 0) {
1978 rdev->mc.real_vram_size = 8192 * 1024;
1979 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1981 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1982 * Novell bug 204882 + along with lots of ubuntu ones
1984 if (config_aper_size > rdev->mc.real_vram_size)
1985 rdev->mc.mc_vram_size = config_aper_size;
1987 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1989 /* FIXME remove this once we support unmappable VRAM */
1990 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1991 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1992 rdev->mc.real_vram_size = rdev->mc.aper_size;
1996 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2000 temp = RREG32(RADEON_CONFIG_CNTL);
2001 if (state == false) {
2007 WREG32(RADEON_CONFIG_CNTL, temp);
2010 void r100_mc_init(struct radeon_device *rdev)
2014 r100_vram_get_type(rdev);
2015 r100_vram_init_sizes(rdev);
2016 base = rdev->mc.aper_base;
2017 if (rdev->flags & RADEON_IS_IGP)
2018 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2019 radeon_vram_location(rdev, &rdev->mc, base);
2020 if (!(rdev->flags & RADEON_IS_AGP))
2021 radeon_gtt_location(rdev, &rdev->mc);
2026 * Indirect registers accessor
2028 void r100_pll_errata_after_index(struct radeon_device *rdev)
2030 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2033 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2034 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2037 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2039 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2040 * or the chip could hang on a subsequent access
2042 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2046 /* This function is required to workaround a hardware bug in some (all?)
2047 * revisions of the R300. This workaround should be called after every
2048 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2049 * may not be correct.
2051 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2054 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2055 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2056 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2057 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2058 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2062 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2066 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2067 r100_pll_errata_after_index(rdev);
2068 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2069 r100_pll_errata_after_data(rdev);
2073 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2075 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2076 r100_pll_errata_after_index(rdev);
2077 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2078 r100_pll_errata_after_data(rdev);
2081 void r100_set_safe_registers(struct radeon_device *rdev)
2083 if (ASIC_IS_RN50(rdev)) {
2084 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2085 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2086 } else if (rdev->family < CHIP_R200) {
2087 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2088 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2090 r200_set_safe_registers(rdev);
2097 #if defined(CONFIG_DEBUG_FS)
2098 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2100 struct drm_info_node *node = (struct drm_info_node *) m->private;
2101 struct drm_device *dev = node->minor->dev;
2102 struct radeon_device *rdev = dev->dev_private;
2103 uint32_t reg, value;
2106 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2107 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2108 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2109 for (i = 0; i < 64; i++) {
2110 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2111 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2112 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2113 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2114 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2119 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2121 struct drm_info_node *node = (struct drm_info_node *) m->private;
2122 struct drm_device *dev = node->minor->dev;
2123 struct radeon_device *rdev = dev->dev_private;
2125 unsigned count, i, j;
2127 radeon_ring_free_size(rdev);
2128 rdp = RREG32(RADEON_CP_RB_RPTR);
2129 wdp = RREG32(RADEON_CP_RB_WPTR);
2130 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2131 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2132 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2133 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2134 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2135 seq_printf(m, "%u dwords in ring\n", count);
2136 for (j = 0; j <= count; j++) {
2137 i = (rdp + j) & rdev->cp.ptr_mask;
2138 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2144 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2146 struct drm_info_node *node = (struct drm_info_node *) m->private;
2147 struct drm_device *dev = node->minor->dev;
2148 struct radeon_device *rdev = dev->dev_private;
2149 uint32_t csq_stat, csq2_stat, tmp;
2150 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2153 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2154 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2155 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2156 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2157 r_rptr = (csq_stat >> 0) & 0x3ff;
2158 r_wptr = (csq_stat >> 10) & 0x3ff;
2159 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2160 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2161 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2162 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2163 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2164 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2165 seq_printf(m, "Ring rptr %u\n", r_rptr);
2166 seq_printf(m, "Ring wptr %u\n", r_wptr);
2167 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2168 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2169 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2170 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2171 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2172 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2173 seq_printf(m, "Ring fifo:\n");
2174 for (i = 0; i < 256; i++) {
2175 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2176 tmp = RREG32(RADEON_CP_CSQ_DATA);
2177 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2179 seq_printf(m, "Indirect1 fifo:\n");
2180 for (i = 256; i <= 512; i++) {
2181 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2182 tmp = RREG32(RADEON_CP_CSQ_DATA);
2183 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2185 seq_printf(m, "Indirect2 fifo:\n");
2186 for (i = 640; i < ib1_wptr; i++) {
2187 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2188 tmp = RREG32(RADEON_CP_CSQ_DATA);
2189 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2194 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2196 struct drm_info_node *node = (struct drm_info_node *) m->private;
2197 struct drm_device *dev = node->minor->dev;
2198 struct radeon_device *rdev = dev->dev_private;
2201 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2202 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2203 tmp = RREG32(RADEON_MC_FB_LOCATION);
2204 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2205 tmp = RREG32(RADEON_BUS_CNTL);
2206 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2207 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2208 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2209 tmp = RREG32(RADEON_AGP_BASE);
2210 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2211 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2212 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2213 tmp = RREG32(0x01D0);
2214 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2215 tmp = RREG32(RADEON_AIC_LO_ADDR);
2216 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2217 tmp = RREG32(RADEON_AIC_HI_ADDR);
2218 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2219 tmp = RREG32(0x01E4);
2220 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2224 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2225 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2228 static struct drm_info_list r100_debugfs_cp_list[] = {
2229 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2230 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2233 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2234 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2238 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2240 #if defined(CONFIG_DEBUG_FS)
2241 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2247 int r100_debugfs_cp_init(struct radeon_device *rdev)
2249 #if defined(CONFIG_DEBUG_FS)
2250 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2256 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2258 #if defined(CONFIG_DEBUG_FS)
2259 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2265 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2266 uint32_t tiling_flags, uint32_t pitch,
2267 uint32_t offset, uint32_t obj_size)
2269 int surf_index = reg * 16;
2272 /* r100/r200 divide by 16 */
2273 if (rdev->family < CHIP_R300)
2278 if (rdev->family <= CHIP_RS200) {
2279 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2280 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2281 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2282 if (tiling_flags & RADEON_TILING_MACRO)
2283 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2284 } else if (rdev->family <= CHIP_RV280) {
2285 if (tiling_flags & (RADEON_TILING_MACRO))
2286 flags |= R200_SURF_TILE_COLOR_MACRO;
2287 if (tiling_flags & RADEON_TILING_MICRO)
2288 flags |= R200_SURF_TILE_COLOR_MICRO;
2290 if (tiling_flags & RADEON_TILING_MACRO)
2291 flags |= R300_SURF_TILE_MACRO;
2292 if (tiling_flags & RADEON_TILING_MICRO)
2293 flags |= R300_SURF_TILE_MICRO;
2296 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2297 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2298 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2299 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2301 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2302 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2303 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2304 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2308 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2310 int surf_index = reg * 16;
2311 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2314 void r100_bandwidth_update(struct radeon_device *rdev)
2316 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2317 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2318 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2319 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2320 fixed20_12 memtcas_ff[8] = {
2329 fixed20_12 memtcas_rs480_ff[8] = {
2339 fixed20_12 memtcas2_ff[8] = {
2349 fixed20_12 memtrbs[8] = {
2359 fixed20_12 memtrbs_r4xx[8] = {
2369 fixed20_12 min_mem_eff;
2370 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2371 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2372 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2373 disp_drain_rate2, read_return_rate;
2374 fixed20_12 time_disp1_drop_priority;
2376 int cur_size = 16; /* in octawords */
2377 int critical_point = 0, critical_point2;
2378 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2379 int stop_req, max_stop_req;
2380 struct drm_display_mode *mode1 = NULL;
2381 struct drm_display_mode *mode2 = NULL;
2382 uint32_t pixel_bytes1 = 0;
2383 uint32_t pixel_bytes2 = 0;
2385 if (rdev->mode_info.crtcs[0]->base.enabled) {
2386 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2387 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2389 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2390 if (rdev->mode_info.crtcs[1]->base.enabled) {
2391 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2392 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2396 min_mem_eff.full = rfixed_const_8(0);
2398 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2399 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2400 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2401 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2402 /* check crtc enables */
2404 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2406 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2407 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2411 * determine is there is enough bw for current mode
2413 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2414 temp_ff.full = rfixed_const(100);
2415 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2416 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2417 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2419 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2420 temp_ff.full = rfixed_const(temp);
2421 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2425 peak_disp_bw.full = 0;
2427 temp_ff.full = rfixed_const(1000);
2428 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2429 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2430 temp_ff.full = rfixed_const(pixel_bytes1);
2431 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2434 temp_ff.full = rfixed_const(1000);
2435 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2436 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2437 temp_ff.full = rfixed_const(pixel_bytes2);
2438 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2441 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2442 if (peak_disp_bw.full >= mem_bw.full) {
2443 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2444 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2447 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2448 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2449 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2450 mem_trcd = ((temp >> 2) & 0x3) + 1;
2451 mem_trp = ((temp & 0x3)) + 1;
2452 mem_tras = ((temp & 0x70) >> 4) + 1;
2453 } else if (rdev->family == CHIP_R300 ||
2454 rdev->family == CHIP_R350) { /* r300, r350 */
2455 mem_trcd = (temp & 0x7) + 1;
2456 mem_trp = ((temp >> 8) & 0x7) + 1;
2457 mem_tras = ((temp >> 11) & 0xf) + 4;
2458 } else if (rdev->family == CHIP_RV350 ||
2459 rdev->family <= CHIP_RV380) {
2461 mem_trcd = (temp & 0x7) + 3;
2462 mem_trp = ((temp >> 8) & 0x7) + 3;
2463 mem_tras = ((temp >> 11) & 0xf) + 6;
2464 } else if (rdev->family == CHIP_R420 ||
2465 rdev->family == CHIP_R423 ||
2466 rdev->family == CHIP_RV410) {
2468 mem_trcd = (temp & 0xf) + 3;
2471 mem_trp = ((temp >> 8) & 0xf) + 3;
2474 mem_tras = ((temp >> 12) & 0x1f) + 6;
2477 } else { /* RV200, R200 */
2478 mem_trcd = (temp & 0x7) + 1;
2479 mem_trp = ((temp >> 8) & 0x7) + 1;
2480 mem_tras = ((temp >> 12) & 0xf) + 4;
2483 trcd_ff.full = rfixed_const(mem_trcd);
2484 trp_ff.full = rfixed_const(mem_trp);
2485 tras_ff.full = rfixed_const(mem_tras);
2487 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2488 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2489 data = (temp & (7 << 20)) >> 20;
2490 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2491 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2492 tcas_ff = memtcas_rs480_ff[data];
2494 tcas_ff = memtcas_ff[data];
2496 tcas_ff = memtcas2_ff[data];
2498 if (rdev->family == CHIP_RS400 ||
2499 rdev->family == CHIP_RS480) {
2500 /* extra cas latency stored in bits 23-25 0-4 clocks */
2501 data = (temp >> 23) & 0x7;
2503 tcas_ff.full += rfixed_const(data);
2506 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2507 /* on the R300, Tcas is included in Trbs.
2509 temp = RREG32(RADEON_MEM_CNTL);
2510 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2512 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2513 temp = RREG32(R300_MC_IND_INDEX);
2514 temp &= ~R300_MC_IND_ADDR_MASK;
2515 temp |= R300_MC_READ_CNTL_CD_mcind;
2516 WREG32(R300_MC_IND_INDEX, temp);
2517 temp = RREG32(R300_MC_IND_DATA);
2518 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2520 temp = RREG32(R300_MC_READ_CNTL_AB);
2521 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2524 temp = RREG32(R300_MC_READ_CNTL_AB);
2525 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2527 if (rdev->family == CHIP_RV410 ||
2528 rdev->family == CHIP_R420 ||
2529 rdev->family == CHIP_R423)
2530 trbs_ff = memtrbs_r4xx[data];
2532 trbs_ff = memtrbs[data];
2533 tcas_ff.full += trbs_ff.full;
2536 sclk_eff_ff.full = sclk_ff.full;
2538 if (rdev->flags & RADEON_IS_AGP) {
2539 fixed20_12 agpmode_ff;
2540 agpmode_ff.full = rfixed_const(radeon_agpmode);
2541 temp_ff.full = rfixed_const_666(16);
2542 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2544 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2546 if (ASIC_IS_R300(rdev)) {
2547 sclk_delay_ff.full = rfixed_const(250);
2549 if ((rdev->family == CHIP_RV100) ||
2550 rdev->flags & RADEON_IS_IGP) {
2551 if (rdev->mc.vram_is_ddr)
2552 sclk_delay_ff.full = rfixed_const(41);
2554 sclk_delay_ff.full = rfixed_const(33);
2556 if (rdev->mc.vram_width == 128)
2557 sclk_delay_ff.full = rfixed_const(57);
2559 sclk_delay_ff.full = rfixed_const(41);
2563 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2565 if (rdev->mc.vram_is_ddr) {
2566 if (rdev->mc.vram_width == 32) {
2567 k1.full = rfixed_const(40);
2570 k1.full = rfixed_const(20);
2574 k1.full = rfixed_const(40);
2578 temp_ff.full = rfixed_const(2);
2579 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2580 temp_ff.full = rfixed_const(c);
2581 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2582 temp_ff.full = rfixed_const(4);
2583 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2584 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2585 mc_latency_mclk.full += k1.full;
2587 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2588 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2591 HW cursor time assuming worst case of full size colour cursor.
2593 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2594 temp_ff.full += trcd_ff.full;
2595 if (temp_ff.full < tras_ff.full)
2596 temp_ff.full = tras_ff.full;
2597 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2599 temp_ff.full = rfixed_const(cur_size);
2600 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2602 Find the total latency for the display data.
2604 disp_latency_overhead.full = rfixed_const(8);
2605 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2606 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2607 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2609 if (mc_latency_mclk.full > mc_latency_sclk.full)
2610 disp_latency.full = mc_latency_mclk.full;
2612 disp_latency.full = mc_latency_sclk.full;
2614 /* setup Max GRPH_STOP_REQ default value */
2615 if (ASIC_IS_RV100(rdev))
2616 max_stop_req = 0x5c;
2618 max_stop_req = 0x7c;
2622 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2623 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2625 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2627 if (stop_req > max_stop_req)
2628 stop_req = max_stop_req;
2631 Find the drain rate of the display buffer.
2633 temp_ff.full = rfixed_const((16/pixel_bytes1));
2634 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2637 Find the critical point of the display buffer.
2639 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2640 crit_point_ff.full += rfixed_const_half(0);
2642 critical_point = rfixed_trunc(crit_point_ff);
2644 if (rdev->disp_priority == 2) {
2649 The critical point should never be above max_stop_req-4. Setting
2650 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2652 if (max_stop_req - critical_point < 4)
2655 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2656 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2657 critical_point = 0x10;
2660 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2661 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2662 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2663 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2664 if ((rdev->family == CHIP_R350) &&
2665 (stop_req > 0x15)) {
2668 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2669 temp |= RADEON_GRPH_BUFFER_SIZE;
2670 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2671 RADEON_GRPH_CRITICAL_AT_SOF |
2672 RADEON_GRPH_STOP_CNTL);
2674 Write the result into the register.
2676 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2677 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2680 if ((rdev->family == CHIP_RS400) ||
2681 (rdev->family == CHIP_RS480)) {
2682 /* attempt to program RS400 disp regs correctly ??? */
2683 temp = RREG32(RS400_DISP1_REG_CNTL);
2684 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2685 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2686 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2687 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2688 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2689 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2690 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2691 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2692 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2693 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2694 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2698 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2699 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2700 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2705 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2707 if (stop_req > max_stop_req)
2708 stop_req = max_stop_req;
2711 Find the drain rate of the display buffer.
2713 temp_ff.full = rfixed_const((16/pixel_bytes2));
2714 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2716 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2717 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2718 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2719 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2720 if ((rdev->family == CHIP_R350) &&
2721 (stop_req > 0x15)) {
2724 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2725 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2726 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2727 RADEON_GRPH_CRITICAL_AT_SOF |
2728 RADEON_GRPH_STOP_CNTL);
2730 if ((rdev->family == CHIP_RS100) ||
2731 (rdev->family == CHIP_RS200))
2732 critical_point2 = 0;
2734 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2735 temp_ff.full = rfixed_const(temp);
2736 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2737 if (sclk_ff.full < temp_ff.full)
2738 temp_ff.full = sclk_ff.full;
2740 read_return_rate.full = temp_ff.full;
2743 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2744 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2746 time_disp1_drop_priority.full = 0;
2748 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2749 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2750 crit_point_ff.full += rfixed_const_half(0);
2752 critical_point2 = rfixed_trunc(crit_point_ff);
2754 if (rdev->disp_priority == 2) {
2755 critical_point2 = 0;
2758 if (max_stop_req - critical_point2 < 4)
2759 critical_point2 = 0;
2763 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2764 /* some R300 cards have problem with this set to 0 */
2765 critical_point2 = 0x10;
2768 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2769 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2771 if ((rdev->family == CHIP_RS400) ||
2772 (rdev->family == CHIP_RS480)) {
2774 /* attempt to program RS400 disp2 regs correctly ??? */
2775 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2776 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2777 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2778 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2779 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2780 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2781 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2782 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2783 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2784 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2785 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2786 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2788 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2789 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2790 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2791 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2794 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2795 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2799 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2801 DRM_ERROR("pitch %d\n", t->pitch);
2802 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2803 DRM_ERROR("width %d\n", t->width);
2804 DRM_ERROR("width_11 %d\n", t->width_11);
2805 DRM_ERROR("height %d\n", t->height);
2806 DRM_ERROR("height_11 %d\n", t->height_11);
2807 DRM_ERROR("num levels %d\n", t->num_levels);
2808 DRM_ERROR("depth %d\n", t->txdepth);
2809 DRM_ERROR("bpp %d\n", t->cpp);
2810 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2811 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2812 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2813 DRM_ERROR("compress format %d\n", t->compress_format);
2816 static int r100_cs_track_cube(struct radeon_device *rdev,
2817 struct r100_cs_track *track, unsigned idx)
2819 unsigned face, w, h;
2820 struct radeon_bo *cube_robj;
2823 for (face = 0; face < 5; face++) {
2824 cube_robj = track->textures[idx].cube_info[face].robj;
2825 w = track->textures[idx].cube_info[face].width;
2826 h = track->textures[idx].cube_info[face].height;
2829 size *= track->textures[idx].cpp;
2831 size += track->textures[idx].cube_info[face].offset;
2833 if (size > radeon_bo_size(cube_robj)) {
2834 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2835 size, radeon_bo_size(cube_robj));
2836 r100_cs_track_texture_print(&track->textures[idx]);
2843 static int r100_track_compress_size(int compress_format, int w, int h)
2845 int block_width, block_height, block_bytes;
2846 int wblocks, hblocks;
2853 switch (compress_format) {
2854 case R100_TRACK_COMP_DXT1:
2859 case R100_TRACK_COMP_DXT35:
2865 hblocks = (h + block_height - 1) / block_height;
2866 wblocks = (w + block_width - 1) / block_width;
2867 if (wblocks < min_wblocks)
2868 wblocks = min_wblocks;
2869 sz = wblocks * hblocks * block_bytes;
2873 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2874 struct r100_cs_track *track)
2876 struct radeon_bo *robj;
2878 unsigned u, i, w, h;
2881 for (u = 0; u < track->num_texture; u++) {
2882 if (!track->textures[u].enabled)
2884 robj = track->textures[u].robj;
2886 DRM_ERROR("No texture bound to unit %u\n", u);
2890 for (i = 0; i <= track->textures[u].num_levels; i++) {
2891 if (track->textures[u].use_pitch) {
2892 if (rdev->family < CHIP_R300)
2893 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2895 w = track->textures[u].pitch / (1 << i);
2897 w = track->textures[u].width;
2898 if (rdev->family >= CHIP_RV515)
2899 w |= track->textures[u].width_11;
2901 if (track->textures[u].roundup_w)
2902 w = roundup_pow_of_two(w);
2904 h = track->textures[u].height;
2905 if (rdev->family >= CHIP_RV515)
2906 h |= track->textures[u].height_11;
2908 if (track->textures[u].roundup_h)
2909 h = roundup_pow_of_two(h);
2910 if (track->textures[u].compress_format) {
2912 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2913 /* compressed textures are block based */
2917 size *= track->textures[u].cpp;
2919 switch (track->textures[u].tex_coord_type) {
2923 size *= (1 << track->textures[u].txdepth);
2926 if (track->separate_cube) {
2927 ret = r100_cs_track_cube(rdev, track, u);
2934 DRM_ERROR("Invalid texture coordinate type %u for unit "
2935 "%u\n", track->textures[u].tex_coord_type, u);
2938 if (size > radeon_bo_size(robj)) {
2939 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2940 "%lu\n", u, size, radeon_bo_size(robj));
2941 r100_cs_track_texture_print(&track->textures[u]);
2948 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2955 for (i = 0; i < track->num_cb; i++) {
2956 if (track->cb[i].robj == NULL) {
2957 if (!(track->fastfill || track->color_channel_mask ||
2958 track->blend_read_enable)) {
2961 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2964 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2965 size += track->cb[i].offset;
2966 if (size > radeon_bo_size(track->cb[i].robj)) {
2967 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2968 "(need %lu have %lu) !\n", i, size,
2969 radeon_bo_size(track->cb[i].robj));
2970 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2971 i, track->cb[i].pitch, track->cb[i].cpp,
2972 track->cb[i].offset, track->maxy);
2976 if (track->z_enabled) {
2977 if (track->zb.robj == NULL) {
2978 DRM_ERROR("[drm] No buffer for z buffer !\n");
2981 size = track->zb.pitch * track->zb.cpp * track->maxy;
2982 size += track->zb.offset;
2983 if (size > radeon_bo_size(track->zb.robj)) {
2984 DRM_ERROR("[drm] Buffer too small for z buffer "
2985 "(need %lu have %lu) !\n", size,
2986 radeon_bo_size(track->zb.robj));
2987 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2988 track->zb.pitch, track->zb.cpp,
2989 track->zb.offset, track->maxy);
2993 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2994 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2995 switch (prim_walk) {
2997 for (i = 0; i < track->num_arrays; i++) {
2998 size = track->arrays[i].esize * track->max_indx * 4;
2999 if (track->arrays[i].robj == NULL) {
3000 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3001 "bound\n", prim_walk, i);
3004 if (size > radeon_bo_size(track->arrays[i].robj)) {
3005 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3006 "need %lu dwords have %lu dwords\n",
3007 prim_walk, i, size >> 2,
3008 radeon_bo_size(track->arrays[i].robj)
3010 DRM_ERROR("Max indices %u\n", track->max_indx);
3016 for (i = 0; i < track->num_arrays; i++) {
3017 size = track->arrays[i].esize * (nverts - 1) * 4;
3018 if (track->arrays[i].robj == NULL) {
3019 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3020 "bound\n", prim_walk, i);
3023 if (size > radeon_bo_size(track->arrays[i].robj)) {
3024 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3025 "need %lu dwords have %lu dwords\n",
3026 prim_walk, i, size >> 2,
3027 radeon_bo_size(track->arrays[i].robj)
3034 size = track->vtx_size * nverts;
3035 if (size != track->immd_dwords) {
3036 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3037 track->immd_dwords, size);
3038 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3039 nverts, track->vtx_size);
3044 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3048 return r100_cs_track_texture_check(rdev, track);
3051 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3055 if (rdev->family < CHIP_R300) {
3057 if (rdev->family <= CHIP_RS200)
3058 track->num_texture = 3;
3060 track->num_texture = 6;
3062 track->separate_cube = 1;
3065 track->num_texture = 16;
3067 track->separate_cube = 0;
3070 for (i = 0; i < track->num_cb; i++) {
3071 track->cb[i].robj = NULL;
3072 track->cb[i].pitch = 8192;
3073 track->cb[i].cpp = 16;
3074 track->cb[i].offset = 0;
3076 track->z_enabled = true;
3077 track->zb.robj = NULL;
3078 track->zb.pitch = 8192;
3080 track->zb.offset = 0;
3081 track->vtx_size = 0x7F;
3082 track->immd_dwords = 0xFFFFFFFFUL;
3083 track->num_arrays = 11;
3084 track->max_indx = 0x00FFFFFFUL;
3085 for (i = 0; i < track->num_arrays; i++) {
3086 track->arrays[i].robj = NULL;
3087 track->arrays[i].esize = 0x7F;
3089 for (i = 0; i < track->num_texture; i++) {
3090 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3091 track->textures[i].pitch = 16536;
3092 track->textures[i].width = 16536;
3093 track->textures[i].height = 16536;
3094 track->textures[i].width_11 = 1 << 11;
3095 track->textures[i].height_11 = 1 << 11;
3096 track->textures[i].num_levels = 12;
3097 if (rdev->family <= CHIP_RS200) {
3098 track->textures[i].tex_coord_type = 0;
3099 track->textures[i].txdepth = 0;
3101 track->textures[i].txdepth = 16;
3102 track->textures[i].tex_coord_type = 1;
3104 track->textures[i].cpp = 64;
3105 track->textures[i].robj = NULL;
3106 /* CS IB emission code makes sure texture unit are disabled */
3107 track->textures[i].enabled = false;
3108 track->textures[i].roundup_w = true;
3109 track->textures[i].roundup_h = true;
3110 if (track->separate_cube)
3111 for (face = 0; face < 5; face++) {
3112 track->textures[i].cube_info[face].robj = NULL;
3113 track->textures[i].cube_info[face].width = 16536;
3114 track->textures[i].cube_info[face].height = 16536;
3115 track->textures[i].cube_info[face].offset = 0;
3120 int r100_ring_test(struct radeon_device *rdev)
3127 r = radeon_scratch_get(rdev, &scratch);
3129 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3132 WREG32(scratch, 0xCAFEDEAD);
3133 r = radeon_ring_lock(rdev, 2);
3135 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3136 radeon_scratch_free(rdev, scratch);
3139 radeon_ring_write(rdev, PACKET0(scratch, 0));
3140 radeon_ring_write(rdev, 0xDEADBEEF);
3141 radeon_ring_unlock_commit(rdev);
3142 for (i = 0; i < rdev->usec_timeout; i++) {
3143 tmp = RREG32(scratch);
3144 if (tmp == 0xDEADBEEF) {
3149 if (i < rdev->usec_timeout) {
3150 DRM_INFO("ring test succeeded in %d usecs\n", i);
3152 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3156 radeon_scratch_free(rdev, scratch);
3160 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3162 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3163 radeon_ring_write(rdev, ib->gpu_addr);
3164 radeon_ring_write(rdev, ib->length_dw);
3167 int r100_ib_test(struct radeon_device *rdev)
3169 struct radeon_ib *ib;
3175 r = radeon_scratch_get(rdev, &scratch);
3177 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3180 WREG32(scratch, 0xCAFEDEAD);
3181 r = radeon_ib_get(rdev, &ib);
3185 ib->ptr[0] = PACKET0(scratch, 0);
3186 ib->ptr[1] = 0xDEADBEEF;
3187 ib->ptr[2] = PACKET2(0);
3188 ib->ptr[3] = PACKET2(0);
3189 ib->ptr[4] = PACKET2(0);
3190 ib->ptr[5] = PACKET2(0);
3191 ib->ptr[6] = PACKET2(0);
3192 ib->ptr[7] = PACKET2(0);
3194 r = radeon_ib_schedule(rdev, ib);
3196 radeon_scratch_free(rdev, scratch);
3197 radeon_ib_free(rdev, &ib);
3200 r = radeon_fence_wait(ib->fence, false);
3204 for (i = 0; i < rdev->usec_timeout; i++) {
3205 tmp = RREG32(scratch);
3206 if (tmp == 0xDEADBEEF) {
3211 if (i < rdev->usec_timeout) {
3212 DRM_INFO("ib test succeeded in %u usecs\n", i);
3214 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3218 radeon_scratch_free(rdev, scratch);
3219 radeon_ib_free(rdev, &ib);
3223 void r100_ib_fini(struct radeon_device *rdev)
3225 radeon_ib_pool_fini(rdev);
3228 int r100_ib_init(struct radeon_device *rdev)
3232 r = radeon_ib_pool_init(rdev);
3234 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3238 r = r100_ib_test(rdev);
3240 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3247 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3249 /* Shutdown CP we shouldn't need to do that but better be safe than
3252 rdev->cp.ready = false;
3253 WREG32(R_000740_CP_CSQ_CNTL, 0);
3255 /* Save few CRTC registers */
3256 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3257 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3258 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3259 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3260 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3261 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3262 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3265 /* Disable VGA aperture access */
3266 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3267 /* Disable cursor, overlay, crtc */
3268 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3269 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3270 S_000054_CRTC_DISPLAY_DIS(1));
3271 WREG32(R_000050_CRTC_GEN_CNTL,
3272 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3273 S_000050_CRTC_DISP_REQ_EN_B(1));
3274 WREG32(R_000420_OV0_SCALE_CNTL,
3275 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3276 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3277 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3278 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3279 S_000360_CUR2_LOCK(1));
3280 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3281 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3282 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3283 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3284 WREG32(R_000360_CUR2_OFFSET,
3285 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3289 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3291 /* Update base address for crtc */
3292 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3293 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3294 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3296 /* Restore CRTC registers */
3297 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3298 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3299 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3300 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3301 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3305 void r100_vga_render_disable(struct radeon_device *rdev)
3309 tmp = RREG8(R_0003C2_GENMO_WT);
3310 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3313 static void r100_debugfs(struct radeon_device *rdev)
3317 r = r100_debugfs_mc_info_init(rdev);
3319 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3322 static void r100_mc_program(struct radeon_device *rdev)
3324 struct r100_mc_save save;
3326 /* Stops all mc clients */
3327 r100_mc_stop(rdev, &save);
3328 if (rdev->flags & RADEON_IS_AGP) {
3329 WREG32(R_00014C_MC_AGP_LOCATION,
3330 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3331 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3332 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3333 if (rdev->family > CHIP_RV200)
3334 WREG32(R_00015C_AGP_BASE_2,
3335 upper_32_bits(rdev->mc.agp_base) & 0xff);
3337 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3338 WREG32(R_000170_AGP_BASE, 0);
3339 if (rdev->family > CHIP_RV200)
3340 WREG32(R_00015C_AGP_BASE_2, 0);
3342 /* Wait for mc idle */
3343 if (r100_mc_wait_for_idle(rdev))
3344 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3345 /* Program MC, should be a 32bits limited address space */
3346 WREG32(R_000148_MC_FB_LOCATION,
3347 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3348 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3349 r100_mc_resume(rdev, &save);
3352 void r100_clock_startup(struct radeon_device *rdev)
3356 if (radeon_dynclks != -1 && radeon_dynclks)
3357 radeon_legacy_set_clock_gating(rdev, 1);
3358 /* We need to force on some of the block */
3359 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3360 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3361 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3362 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3363 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3366 static int r100_startup(struct radeon_device *rdev)
3370 /* set common regs */
3371 r100_set_common_regs(rdev);
3373 r100_mc_program(rdev);
3375 r100_clock_startup(rdev);
3376 /* Initialize GPU configuration (# pipes, ...) */
3377 r100_gpu_init(rdev);
3378 /* Initialize GART (initialize after TTM so we can allocate
3379 * memory through TTM but finalize after TTM) */
3380 r100_enable_bm(rdev);
3381 if (rdev->flags & RADEON_IS_PCI) {
3382 r = r100_pci_gart_enable(rdev);
3388 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3389 /* 1M ring buffer */
3390 r = r100_cp_init(rdev, 1024 * 1024);
3392 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3395 r = r100_wb_init(rdev);
3397 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3398 r = r100_ib_init(rdev);
3400 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3406 int r100_resume(struct radeon_device *rdev)
3408 /* Make sur GART are not working */
3409 if (rdev->flags & RADEON_IS_PCI)
3410 r100_pci_gart_disable(rdev);
3411 /* Resume clock before doing reset */
3412 r100_clock_startup(rdev);
3413 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3414 if (radeon_gpu_reset(rdev)) {
3415 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3416 RREG32(R_000E40_RBBM_STATUS),
3417 RREG32(R_0007C0_CP_STAT));
3420 radeon_combios_asic_init(rdev->ddev);
3421 /* Resume clock after posting */
3422 r100_clock_startup(rdev);
3423 /* Initialize surface registers */
3424 radeon_surface_init(rdev);
3425 return r100_startup(rdev);
3428 int r100_suspend(struct radeon_device *rdev)
3430 r100_cp_disable(rdev);
3431 r100_wb_disable(rdev);
3432 r100_irq_disable(rdev);
3433 if (rdev->flags & RADEON_IS_PCI)
3434 r100_pci_gart_disable(rdev);
3438 void r100_fini(struct radeon_device *rdev)
3443 radeon_gem_fini(rdev);
3444 if (rdev->flags & RADEON_IS_PCI)
3445 r100_pci_gart_fini(rdev);
3446 radeon_agp_fini(rdev);
3447 radeon_irq_kms_fini(rdev);
3448 radeon_fence_driver_fini(rdev);
3449 radeon_bo_fini(rdev);
3450 radeon_atombios_fini(rdev);
3455 int r100_init(struct radeon_device *rdev)
3459 /* Register debugfs file specific to this group of asics */
3462 r100_vga_render_disable(rdev);
3463 /* Initialize scratch registers */
3464 radeon_scratch_init(rdev);
3465 /* Initialize surface registers */
3466 radeon_surface_init(rdev);
3467 /* TODO: disable VGA need to use VGA request */
3469 if (!radeon_get_bios(rdev)) {
3470 if (ASIC_IS_AVIVO(rdev))
3473 if (rdev->is_atom_bios) {
3474 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3477 r = radeon_combios_init(rdev);
3481 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3482 if (radeon_gpu_reset(rdev)) {
3484 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3485 RREG32(R_000E40_RBBM_STATUS),
3486 RREG32(R_0007C0_CP_STAT));
3488 /* check if cards are posted or not */
3489 if (radeon_boot_test_post_card(rdev) == false)
3491 /* Set asic errata */
3493 /* Initialize clocks */
3494 radeon_get_clock_info(rdev->ddev);
3495 /* Initialize power management */
3496 radeon_pm_init(rdev);
3497 /* initialize AGP */
3498 if (rdev->flags & RADEON_IS_AGP) {
3499 r = radeon_agp_init(rdev);
3501 radeon_agp_disable(rdev);
3504 /* initialize VRAM */
3507 r = radeon_fence_driver_init(rdev);
3510 r = radeon_irq_kms_init(rdev);
3513 /* Memory manager */
3514 r = radeon_bo_init(rdev);
3517 if (rdev->flags & RADEON_IS_PCI) {
3518 r = r100_pci_gart_init(rdev);
3522 r100_set_safe_registers(rdev);
3523 rdev->accel_working = true;
3524 r = r100_startup(rdev);
3526 /* Somethings want wront with the accel init stop accel */
3527 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3531 radeon_irq_kms_fini(rdev);
3532 if (rdev->flags & RADEON_IS_PCI)
3533 r100_pci_gart_fini(rdev);
3534 rdev->accel_working = false;