2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
53 switch (radeon_crtc->rmx_type) {
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
85 static void atombios_scaler_setup(struct drm_crtc *crtc)
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
113 memset(&args, 0, sizeof(args));
115 args.ucScaler = radeon_crtc->crtc_id;
121 args.ucTVStandard = ATOM_TV_NTSC;
124 args.ucTVStandard = ATOM_TV_PAL;
127 args.ucTVStandard = ATOM_TV_PALM;
130 args.ucTVStandard = ATOM_TV_PAL60;
133 args.ucTVStandard = ATOM_TV_NTSCJ;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
139 args.ucTVStandard = ATOM_TV_SECAM;
142 args.ucTVStandard = ATOM_TV_PALCN;
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
150 switch (radeon_crtc->rmx_type) {
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 args.ucEnable = ATOM_SCALER_CENTER;
158 args.ucEnable = ATOM_SCALER_EXPANSION;
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
164 args.ucEnable = ATOM_SCALER_CENTER;
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
184 memset(&args, 0, sizeof(args));
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
200 memset(&args, 0, sizeof(args));
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
216 memset(&args, 0, sizeof(args));
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
247 case DRM_MODE_DPMS_ON:
248 atombios_enable_crtc(crtc, ATOM_ENABLE);
249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
251 atombios_blank_crtc(crtc, ATOM_DISABLE);
252 /* XXX re-enable when interrupt support is added */
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
255 radeon_crtc_load_lut(crtc);
257 case DRM_MODE_DPMS_STANDBY:
258 case DRM_MODE_DPMS_SUSPEND:
259 case DRM_MODE_DPMS_OFF:
260 /* XXX re-enable when interrupt support is added */
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
263 atombios_blank_crtc(crtc, ATOM_ENABLE);
264 if (ASIC_IS_DCE3(rdev))
265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
266 atombios_enable_crtc(crtc, ATOM_DISABLE);
272 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
273 struct drm_display_mode *mode)
275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
276 struct drm_device *dev = crtc->dev;
277 struct radeon_device *rdev = dev->dev_private;
278 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
279 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
282 memset(&args, 0, sizeof(args));
283 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
284 args.usH_Blanking_Time =
285 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
286 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
287 args.usV_Blanking_Time =
288 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
289 args.usH_SyncOffset =
290 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
292 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
293 args.usV_SyncOffset =
294 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
296 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
297 /*args.ucH_Border = mode->hborder;*/
298 /*args.ucV_Border = mode->vborder;*/
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 misc |= ATOM_VSYNC_POLARITY;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 misc |= ATOM_HSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_CSYNC)
305 misc |= ATOM_COMPOSITESYNC;
306 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
307 misc |= ATOM_INTERLACE;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 misc |= ATOM_DOUBLE_CLOCK_MODE;
311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
312 args.ucCRTC = radeon_crtc->crtc_id;
314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
317 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
318 struct drm_display_mode *mode)
320 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
321 struct drm_device *dev = crtc->dev;
322 struct radeon_device *rdev = dev->dev_private;
323 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
324 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
327 memset(&args, 0, sizeof(args));
328 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
329 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
330 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
332 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
333 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
334 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
335 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
337 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
339 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
340 misc |= ATOM_VSYNC_POLARITY;
341 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
342 misc |= ATOM_HSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_CSYNC)
344 misc |= ATOM_COMPOSITESYNC;
345 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
346 misc |= ATOM_INTERLACE;
347 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
348 misc |= ATOM_DOUBLE_CLOCK_MODE;
350 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
351 args.ucCRTC = radeon_crtc->crtc_id;
353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356 union atom_enable_ss {
357 ENABLE_LVDS_SS_PARAMETERS legacy;
358 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
361 static void atombios_set_ss(struct drm_crtc *crtc, int enable)
363 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
364 struct drm_device *dev = crtc->dev;
365 struct radeon_device *rdev = dev->dev_private;
366 struct drm_encoder *encoder = NULL;
367 struct radeon_encoder *radeon_encoder = NULL;
368 struct radeon_encoder_atom_dig *dig = NULL;
369 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
370 union atom_enable_ss args;
371 uint16_t percentage = 0;
372 uint8_t type = 0, step = 0, delay = 0, range = 0;
374 /* XXX add ss support for DCE4 */
375 if (ASIC_IS_DCE4(rdev))
378 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
379 if (encoder->crtc == crtc) {
380 radeon_encoder = to_radeon_encoder(encoder);
381 /* only enable spread spectrum on LVDS */
382 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
383 dig = radeon_encoder->enc_priv;
384 if (dig && dig->ss) {
385 percentage = dig->ss->percentage;
386 type = dig->ss->type;
387 step = dig->ss->step;
388 delay = dig->ss->delay;
389 range = dig->ss->range;
401 memset(&args, 0, sizeof(args));
402 if (ASIC_IS_AVIVO(rdev)) {
403 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
404 args.v1.ucSpreadSpectrumType = type;
405 args.v1.ucSpreadSpectrumStep = step;
406 args.v1.ucSpreadSpectrumDelay = delay;
407 args.v1.ucSpreadSpectrumRange = range;
408 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
409 args.v1.ucEnable = enable;
411 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
412 args.legacy.ucSpreadSpectrumType = type;
413 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
414 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
415 args.legacy.ucEnable = enable;
417 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
420 union adjust_pixel_clock {
421 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
422 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
425 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
426 struct drm_display_mode *mode,
427 struct radeon_pll *pll)
429 struct drm_device *dev = crtc->dev;
430 struct radeon_device *rdev = dev->dev_private;
431 struct drm_encoder *encoder = NULL;
432 struct radeon_encoder *radeon_encoder = NULL;
433 u32 adjusted_clock = mode->clock;
434 int encoder_mode = 0;
436 /* reset the pll flags */
439 /* select the PLL algo */
440 if (ASIC_IS_AVIVO(rdev)) {
442 pll->algo = PLL_ALGO_AVIVO;
444 pll->algo = PLL_ALGO_LEGACY;
446 pll->algo = PLL_ALGO_LEGACY;
448 if (ASIC_IS_AVIVO(rdev)) {
449 if ((rdev->family == CHIP_RS600) ||
450 (rdev->family == CHIP_RS690) ||
451 (rdev->family == CHIP_RS740))
452 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
453 RADEON_PLL_PREFER_CLOSEST_LOWER);
455 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
456 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
458 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
460 pll->flags |= RADEON_PLL_LEGACY;
462 if (mode->clock > 200000) /* range limits??? */
463 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
465 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
469 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
470 if (encoder->crtc == crtc) {
471 radeon_encoder = to_radeon_encoder(encoder);
472 encoder_mode = atombios_get_encoder_mode(encoder);
473 if (ASIC_IS_AVIVO(rdev)) {
474 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
475 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
476 adjusted_clock = mode->clock * 2;
477 /* LVDS PLL quirks */
478 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
479 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
480 pll->algo = dig->pll_algo;
483 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
484 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
485 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
486 pll->flags |= RADEON_PLL_USE_REF_DIV;
492 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
493 * accordingly based on the encoder/transmitter to work around
494 * special hw requirements.
496 if (ASIC_IS_DCE3(rdev)) {
497 union adjust_pixel_clock args;
501 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
502 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
505 memset(&args, 0, sizeof(args));
512 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
513 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
514 args.v1.ucEncodeMode = encoder_mode;
516 atom_execute_table(rdev->mode_info.atom_context,
517 index, (uint32_t *)&args);
518 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
521 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
522 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
523 args.v3.sInput.ucEncodeMode = encoder_mode;
524 args.v3.sInput.ucDispPllConfig = 0;
525 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
528 if (encoder_mode == ATOM_ENCODER_MODE_DP)
529 args.v3.sInput.ucDispPllConfig |=
530 DISPPLL_CONFIG_COHERENT_MODE;
532 if (dig->coherent_mode)
533 args.v3.sInput.ucDispPllConfig |=
534 DISPPLL_CONFIG_COHERENT_MODE;
535 if (mode->clock > 165000)
536 args.v3.sInput.ucDispPllConfig |=
537 DISPPLL_CONFIG_DUAL_LINK;
539 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
540 /* may want to enable SS on DP/eDP eventually */
541 args.v3.sInput.ucDispPllConfig |=
542 DISPPLL_CONFIG_SS_ENABLE;
543 if (mode->clock > 165000)
544 args.v3.sInput.ucDispPllConfig |=
545 DISPPLL_CONFIG_DUAL_LINK;
547 atom_execute_table(rdev->mode_info.atom_context,
548 index, (uint32_t *)&args);
549 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
550 if (args.v3.sOutput.ucRefDiv) {
551 pll->flags |= RADEON_PLL_USE_REF_DIV;
552 pll->reference_div = args.v3.sOutput.ucRefDiv;
554 if (args.v3.sOutput.ucPostDiv) {
555 pll->flags |= RADEON_PLL_USE_POST_DIV;
556 pll->post_div = args.v3.sOutput.ucPostDiv;
560 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
561 return adjusted_clock;
565 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
566 return adjusted_clock;
569 return adjusted_clock;
572 union set_pixel_clock {
573 SET_PIXEL_CLOCK_PS_ALLOCATION base;
574 PIXEL_CLOCK_PARAMETERS v1;
575 PIXEL_CLOCK_PARAMETERS_V2 v2;
576 PIXEL_CLOCK_PARAMETERS_V3 v3;
577 PIXEL_CLOCK_PARAMETERS_V5 v5;
580 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
582 struct drm_device *dev = crtc->dev;
583 struct radeon_device *rdev = dev->dev_private;
586 union set_pixel_clock args;
588 memset(&args, 0, sizeof(args));
590 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
591 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
598 /* if the default dcpll clock is specified,
599 * SetPixelClock provides the dividers
601 args.v5.ucCRTC = ATOM_CRTC_INVALID;
602 args.v5.usPixelClock = rdev->clock.default_dispclk;
603 args.v5.ucPpll = ATOM_DCPLL;
606 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
611 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
614 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
617 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
619 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
620 struct drm_device *dev = crtc->dev;
621 struct radeon_device *rdev = dev->dev_private;
622 struct drm_encoder *encoder = NULL;
623 struct radeon_encoder *radeon_encoder = NULL;
626 union set_pixel_clock args;
627 u32 pll_clock = mode->clock;
628 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
629 struct radeon_pll *pll;
631 int encoder_mode = 0;
633 memset(&args, 0, sizeof(args));
635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
636 if (encoder->crtc == crtc) {
637 radeon_encoder = to_radeon_encoder(encoder);
638 encoder_mode = atombios_get_encoder_mode(encoder);
646 switch (radeon_crtc->pll_id) {
648 pll = &rdev->clock.p1pll;
651 pll = &rdev->clock.p2pll;
654 case ATOM_PPLL_INVALID:
655 pll = &rdev->clock.dcpll;
659 /* adjust pixel clock as needed */
660 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
662 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
663 &ref_div, &post_div);
665 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
666 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
673 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
674 args.v1.usRefDiv = cpu_to_le16(ref_div);
675 args.v1.usFbDiv = cpu_to_le16(fb_div);
676 args.v1.ucFracFbDiv = frac_fb_div;
677 args.v1.ucPostDiv = post_div;
678 args.v1.ucPpll = radeon_crtc->pll_id;
679 args.v1.ucCRTC = radeon_crtc->crtc_id;
680 args.v1.ucRefDivSrc = 1;
683 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
684 args.v2.usRefDiv = cpu_to_le16(ref_div);
685 args.v2.usFbDiv = cpu_to_le16(fb_div);
686 args.v2.ucFracFbDiv = frac_fb_div;
687 args.v2.ucPostDiv = post_div;
688 args.v2.ucPpll = radeon_crtc->pll_id;
689 args.v2.ucCRTC = radeon_crtc->crtc_id;
690 args.v2.ucRefDivSrc = 1;
693 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
694 args.v3.usRefDiv = cpu_to_le16(ref_div);
695 args.v3.usFbDiv = cpu_to_le16(fb_div);
696 args.v3.ucFracFbDiv = frac_fb_div;
697 args.v3.ucPostDiv = post_div;
698 args.v3.ucPpll = radeon_crtc->pll_id;
699 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
700 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
701 args.v3.ucEncoderMode = encoder_mode;
704 args.v5.ucCRTC = radeon_crtc->crtc_id;
705 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
706 args.v5.ucRefDiv = ref_div;
707 args.v5.usFbDiv = cpu_to_le16(fb_div);
708 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
709 args.v5.ucPostDiv = post_div;
710 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
711 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
712 args.v5.ucEncoderMode = encoder_mode;
713 args.v5.ucPpll = radeon_crtc->pll_id;
716 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
721 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
725 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
728 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
729 struct drm_framebuffer *old_fb)
731 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
732 struct drm_device *dev = crtc->dev;
733 struct radeon_device *rdev = dev->dev_private;
734 struct radeon_framebuffer *radeon_fb;
735 struct drm_gem_object *obj;
736 struct radeon_bo *rbo;
737 uint64_t fb_location;
738 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
743 DRM_DEBUG("No FB bound\n");
747 radeon_fb = to_radeon_framebuffer(crtc->fb);
749 /* Pin framebuffer & get tilling informations */
750 obj = radeon_fb->obj;
751 rbo = obj->driver_private;
752 r = radeon_bo_reserve(rbo, false);
753 if (unlikely(r != 0))
755 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
756 if (unlikely(r != 0)) {
757 radeon_bo_unreserve(rbo);
760 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
761 radeon_bo_unreserve(rbo);
763 switch (crtc->fb->bits_per_pixel) {
765 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
766 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
769 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
770 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
773 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
774 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
778 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
779 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
782 DRM_ERROR("Unsupported screen depth %d\n",
783 crtc->fb->bits_per_pixel);
787 switch (radeon_crtc->crtc_id) {
789 WREG32(AVIVO_D1VGA_CONTROL, 0);
792 WREG32(AVIVO_D2VGA_CONTROL, 0);
795 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
798 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
801 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
804 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
810 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
811 upper_32_bits(fb_location));
812 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
813 upper_32_bits(fb_location));
814 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
815 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
816 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
817 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
818 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
820 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
821 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
822 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
823 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
824 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
825 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
827 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
828 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
829 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
831 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
832 crtc->mode.vdisplay);
835 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
837 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
838 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
840 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
841 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
842 EVERGREEN_INTERLEAVE_EN);
844 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
846 if (old_fb && old_fb != crtc->fb) {
847 radeon_fb = to_radeon_framebuffer(old_fb);
848 rbo = radeon_fb->obj->driver_private;
849 r = radeon_bo_reserve(rbo, false);
850 if (unlikely(r != 0))
852 radeon_bo_unpin(rbo);
853 radeon_bo_unreserve(rbo);
856 /* Bytes per pixel may have changed */
857 radeon_bandwidth_update(rdev);
862 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
863 struct drm_framebuffer *old_fb)
865 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
866 struct drm_device *dev = crtc->dev;
867 struct radeon_device *rdev = dev->dev_private;
868 struct radeon_framebuffer *radeon_fb;
869 struct drm_gem_object *obj;
870 struct radeon_bo *rbo;
871 uint64_t fb_location;
872 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
877 DRM_DEBUG("No FB bound\n");
881 radeon_fb = to_radeon_framebuffer(crtc->fb);
883 /* Pin framebuffer & get tilling informations */
884 obj = radeon_fb->obj;
885 rbo = obj->driver_private;
886 r = radeon_bo_reserve(rbo, false);
887 if (unlikely(r != 0))
889 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
890 if (unlikely(r != 0)) {
891 radeon_bo_unreserve(rbo);
894 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
895 radeon_bo_unreserve(rbo);
897 switch (crtc->fb->bits_per_pixel) {
900 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
901 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
905 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
906 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
910 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
911 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
916 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
917 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
920 DRM_ERROR("Unsupported screen depth %d\n",
921 crtc->fb->bits_per_pixel);
925 if (tiling_flags & RADEON_TILING_MACRO)
926 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
928 if (tiling_flags & RADEON_TILING_MICRO)
929 fb_format |= AVIVO_D1GRPH_TILED;
931 if (radeon_crtc->crtc_id == 0)
932 WREG32(AVIVO_D1VGA_CONTROL, 0);
934 WREG32(AVIVO_D2VGA_CONTROL, 0);
936 if (rdev->family >= CHIP_RV770) {
937 if (radeon_crtc->crtc_id) {
938 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
939 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
941 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
942 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
945 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
947 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
948 radeon_crtc->crtc_offset, (u32) fb_location);
949 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
951 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
952 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
953 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
954 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
955 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
956 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
958 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
959 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
960 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
962 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
963 crtc->mode.vdisplay);
966 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
968 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
969 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
971 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
972 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
973 AVIVO_D1MODE_INTERLEAVE_EN);
975 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
977 if (old_fb && old_fb != crtc->fb) {
978 radeon_fb = to_radeon_framebuffer(old_fb);
979 rbo = radeon_fb->obj->driver_private;
980 r = radeon_bo_reserve(rbo, false);
981 if (unlikely(r != 0))
983 radeon_bo_unpin(rbo);
984 radeon_bo_unreserve(rbo);
987 /* Bytes per pixel may have changed */
988 radeon_bandwidth_update(rdev);
993 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
994 struct drm_framebuffer *old_fb)
996 struct drm_device *dev = crtc->dev;
997 struct radeon_device *rdev = dev->dev_private;
999 if (ASIC_IS_DCE4(rdev))
1000 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1001 else if (ASIC_IS_AVIVO(rdev))
1002 return avivo_crtc_set_base(crtc, x, y, old_fb);
1004 return radeon_crtc_set_base(crtc, x, y, old_fb);
1007 /* properly set additional regs when using atombios */
1008 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1010 struct drm_device *dev = crtc->dev;
1011 struct radeon_device *rdev = dev->dev_private;
1012 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1013 u32 disp_merge_cntl;
1015 switch (radeon_crtc->crtc_id) {
1017 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1018 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1019 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1022 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1023 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1024 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1025 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1026 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1031 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1033 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1034 struct drm_device *dev = crtc->dev;
1035 struct radeon_device *rdev = dev->dev_private;
1036 struct drm_encoder *test_encoder;
1037 struct drm_crtc *test_crtc;
1038 uint32_t pll_in_use = 0;
1040 if (ASIC_IS_DCE4(rdev)) {
1041 /* if crtc is driving DP and we have an ext clock, use that */
1042 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1043 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1044 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1045 if (rdev->clock.dp_extclk)
1046 return ATOM_PPLL_INVALID;
1051 /* otherwise, pick one of the plls */
1052 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1053 struct radeon_crtc *radeon_test_crtc;
1055 if (crtc == test_crtc)
1058 radeon_test_crtc = to_radeon_crtc(test_crtc);
1059 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1060 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1061 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1063 if (!(pll_in_use & 1))
1067 return radeon_crtc->crtc_id;
1071 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1072 struct drm_display_mode *mode,
1073 struct drm_display_mode *adjusted_mode,
1074 int x, int y, struct drm_framebuffer *old_fb)
1076 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1077 struct drm_device *dev = crtc->dev;
1078 struct radeon_device *rdev = dev->dev_private;
1080 /* TODO color tiling */
1083 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1085 atombios_set_ss(crtc, 0);
1086 /* always set DCPLL */
1087 if (ASIC_IS_DCE4(rdev))
1088 atombios_crtc_set_dcpll(crtc);
1089 atombios_crtc_set_pll(crtc, adjusted_mode);
1090 atombios_set_ss(crtc, 1);
1092 if (ASIC_IS_DCE4(rdev))
1093 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1094 else if (ASIC_IS_AVIVO(rdev))
1095 atombios_crtc_set_timing(crtc, adjusted_mode);
1097 atombios_crtc_set_timing(crtc, adjusted_mode);
1098 if (radeon_crtc->crtc_id == 0)
1099 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1100 radeon_legacy_atom_fixup(crtc);
1102 atombios_crtc_set_base(crtc, x, y, old_fb);
1103 atombios_overscan_setup(crtc, mode, adjusted_mode);
1104 atombios_scaler_setup(crtc);
1108 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1109 struct drm_display_mode *mode,
1110 struct drm_display_mode *adjusted_mode)
1112 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1117 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1119 atombios_lock_crtc(crtc, ATOM_ENABLE);
1120 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1123 static void atombios_crtc_commit(struct drm_crtc *crtc)
1125 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1126 atombios_lock_crtc(crtc, ATOM_DISABLE);
1129 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1130 .dpms = atombios_crtc_dpms,
1131 .mode_fixup = atombios_crtc_mode_fixup,
1132 .mode_set = atombios_crtc_mode_set,
1133 .mode_set_base = atombios_crtc_set_base,
1134 .prepare = atombios_crtc_prepare,
1135 .commit = atombios_crtc_commit,
1136 .load_lut = radeon_crtc_load_lut,
1139 void radeon_atombios_init_crtc(struct drm_device *dev,
1140 struct radeon_crtc *radeon_crtc)
1142 struct radeon_device *rdev = dev->dev_private;
1144 if (ASIC_IS_DCE4(rdev)) {
1145 switch (radeon_crtc->crtc_id) {
1148 radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET;
1151 radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET;
1154 radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET;
1157 radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET;
1160 radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET;
1163 radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET;
1167 if (radeon_crtc->crtc_id == 1)
1168 radeon_crtc->crtc_offset =
1169 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1171 radeon_crtc->crtc_offset = 0;
1173 radeon_crtc->pll_id = -1;
1174 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);