2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
53 switch (radeon_crtc->rmx_type) {
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
85 static void atombios_scaler_setup(struct drm_crtc *crtc)
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
113 memset(&args, 0, sizeof(args));
115 args.ucScaler = radeon_crtc->crtc_id;
121 args.ucTVStandard = ATOM_TV_NTSC;
124 args.ucTVStandard = ATOM_TV_PAL;
127 args.ucTVStandard = ATOM_TV_PALM;
130 args.ucTVStandard = ATOM_TV_PAL60;
133 args.ucTVStandard = ATOM_TV_NTSCJ;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
139 args.ucTVStandard = ATOM_TV_SECAM;
142 args.ucTVStandard = ATOM_TV_PALCN;
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
150 switch (radeon_crtc->rmx_type) {
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 args.ucEnable = ATOM_SCALER_CENTER;
158 args.ucEnable = ATOM_SCALER_EXPANSION;
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
164 args.ucEnable = ATOM_SCALER_CENTER;
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
184 memset(&args, 0, sizeof(args));
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
200 memset(&args, 0, sizeof(args));
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
216 memset(&args, 0, sizeof(args));
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
247 case DRM_MODE_DPMS_ON:
248 atombios_enable_crtc(crtc, 1);
249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, 1);
251 atombios_blank_crtc(crtc, 0);
252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
253 radeon_crtc_load_lut(crtc);
255 case DRM_MODE_DPMS_STANDBY:
256 case DRM_MODE_DPMS_SUSPEND:
257 case DRM_MODE_DPMS_OFF:
258 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
259 atombios_blank_crtc(crtc, 1);
260 if (ASIC_IS_DCE3(rdev))
261 atombios_enable_crtc_memreq(crtc, 0);
262 atombios_enable_crtc(crtc, 0);
268 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
269 struct drm_display_mode *mode)
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
278 memset(&args, 0, sizeof(args));
279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
280 args.usH_Blanking_Time =
281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
283 args.usV_Blanking_Time =
284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
285 args.usH_SyncOffset =
286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 /*args.ucH_Border = mode->hborder;*/
294 /*args.ucV_Border = mode->vborder;*/
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
313 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352 union atom_enable_ss {
353 ENABLE_LVDS_SS_PARAMETERS legacy;
354 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
357 static void atombios_set_ss(struct drm_crtc *crtc, int enable)
359 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
360 struct drm_device *dev = crtc->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 struct drm_encoder *encoder = NULL;
363 struct radeon_encoder *radeon_encoder = NULL;
364 struct radeon_encoder_atom_dig *dig = NULL;
365 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
366 union atom_enable_ss args;
367 uint16_t percentage = 0;
368 uint8_t type = 0, step = 0, delay = 0, range = 0;
370 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
371 if (encoder->crtc == crtc) {
372 radeon_encoder = to_radeon_encoder(encoder);
373 /* only enable spread spectrum on LVDS */
374 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
375 dig = radeon_encoder->enc_priv;
376 if (dig && dig->ss) {
377 percentage = dig->ss->percentage;
378 type = dig->ss->type;
379 step = dig->ss->step;
380 delay = dig->ss->delay;
381 range = dig->ss->range;
393 memset(&args, 0, sizeof(args));
394 if (ASIC_IS_AVIVO(rdev)) {
395 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
396 args.v1.ucSpreadSpectrumType = type;
397 args.v1.ucSpreadSpectrumStep = step;
398 args.v1.ucSpreadSpectrumDelay = delay;
399 args.v1.ucSpreadSpectrumRange = range;
400 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
401 args.v1.ucEnable = enable;
403 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
404 args.legacy.ucSpreadSpectrumType = type;
405 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
406 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
407 args.legacy.ucEnable = enable;
409 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
412 union adjust_pixel_clock {
413 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
416 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
417 struct drm_display_mode *mode,
418 struct radeon_pll *pll)
420 struct drm_device *dev = crtc->dev;
421 struct radeon_device *rdev = dev->dev_private;
422 struct drm_encoder *encoder = NULL;
423 struct radeon_encoder *radeon_encoder = NULL;
424 u32 adjusted_clock = mode->clock;
426 /* reset the pll flags */
429 /* select the PLL algo */
430 if (ASIC_IS_AVIVO(rdev)) {
432 pll->algo = PLL_ALGO_AVIVO;
434 pll->algo = PLL_ALGO_LEGACY;
436 pll->algo = PLL_ALGO_LEGACY;
438 if (ASIC_IS_AVIVO(rdev)) {
439 if ((rdev->family == CHIP_RS600) ||
440 (rdev->family == CHIP_RS690) ||
441 (rdev->family == CHIP_RS740))
442 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
443 RADEON_PLL_PREFER_CLOSEST_LOWER);
445 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
446 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
448 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
450 pll->flags |= RADEON_PLL_LEGACY;
452 if (mode->clock > 200000) /* range limits??? */
453 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
455 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
459 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
460 if (encoder->crtc == crtc) {
461 radeon_encoder = to_radeon_encoder(encoder);
462 if (ASIC_IS_AVIVO(rdev)) {
463 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
464 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
465 adjusted_clock = mode->clock * 2;
466 /* LVDS PLL quirks */
467 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
468 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
469 pll->algo = dig->pll_algo;
472 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
473 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
474 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
475 pll->flags |= RADEON_PLL_USE_REF_DIV;
481 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
482 * accordingly based on the encoder/transmitter to work around
483 * special hw requirements.
485 if (ASIC_IS_DCE3(rdev)) {
486 union adjust_pixel_clock args;
487 struct radeon_encoder_atom_dig *dig;
491 if (!radeon_encoder->enc_priv)
492 return adjusted_clock;
493 dig = radeon_encoder->enc_priv;
495 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
496 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
499 memset(&args, 0, sizeof(args));
506 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
507 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
508 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
510 atom_execute_table(rdev->mode_info.atom_context,
511 index, (uint32_t *)&args);
512 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
515 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
516 return adjusted_clock;
520 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
521 return adjusted_clock;
524 return adjusted_clock;
527 union set_pixel_clock {
528 SET_PIXEL_CLOCK_PS_ALLOCATION base;
529 PIXEL_CLOCK_PARAMETERS v1;
530 PIXEL_CLOCK_PARAMETERS_V2 v2;
531 PIXEL_CLOCK_PARAMETERS_V3 v3;
534 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
536 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
537 struct drm_device *dev = crtc->dev;
538 struct radeon_device *rdev = dev->dev_private;
539 struct drm_encoder *encoder = NULL;
540 struct radeon_encoder *radeon_encoder = NULL;
543 union set_pixel_clock args;
544 u32 pll_clock = mode->clock;
545 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
546 struct radeon_pll *pll;
549 memset(&args, 0, sizeof(args));
551 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
552 if (encoder->crtc == crtc) {
553 radeon_encoder = to_radeon_encoder(encoder);
561 if (radeon_crtc->crtc_id == 0)
562 pll = &rdev->clock.p1pll;
564 pll = &rdev->clock.p2pll;
566 /* adjust pixel clock as needed */
567 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
569 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
570 &ref_div, &post_div);
572 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
573 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
580 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
581 args.v1.usRefDiv = cpu_to_le16(ref_div);
582 args.v1.usFbDiv = cpu_to_le16(fb_div);
583 args.v1.ucFracFbDiv = frac_fb_div;
584 args.v1.ucPostDiv = post_div;
586 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
587 args.v1.ucCRTC = radeon_crtc->crtc_id;
588 args.v1.ucRefDivSrc = 1;
591 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
592 args.v2.usRefDiv = cpu_to_le16(ref_div);
593 args.v2.usFbDiv = cpu_to_le16(fb_div);
594 args.v2.ucFracFbDiv = frac_fb_div;
595 args.v2.ucPostDiv = post_div;
597 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
598 args.v2.ucCRTC = radeon_crtc->crtc_id;
599 args.v2.ucRefDivSrc = 1;
602 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
603 args.v3.usRefDiv = cpu_to_le16(ref_div);
604 args.v3.usFbDiv = cpu_to_le16(fb_div);
605 args.v3.ucFracFbDiv = frac_fb_div;
606 args.v3.ucPostDiv = post_div;
608 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
609 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
610 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
611 args.v3.ucEncoderMode =
612 atombios_get_encoder_mode(encoder);
615 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
620 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
624 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
627 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
628 struct drm_framebuffer *old_fb)
630 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
631 struct drm_device *dev = crtc->dev;
632 struct radeon_device *rdev = dev->dev_private;
633 struct radeon_framebuffer *radeon_fb;
634 struct drm_gem_object *obj;
635 struct radeon_bo *rbo;
636 uint64_t fb_location;
637 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
642 DRM_DEBUG("No FB bound\n");
646 radeon_fb = to_radeon_framebuffer(crtc->fb);
648 /* Pin framebuffer & get tilling informations */
649 obj = radeon_fb->obj;
650 rbo = obj->driver_private;
651 r = radeon_bo_reserve(rbo, false);
652 if (unlikely(r != 0))
654 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
655 if (unlikely(r != 0)) {
656 radeon_bo_unreserve(rbo);
659 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
660 radeon_bo_unreserve(rbo);
662 switch (crtc->fb->bits_per_pixel) {
665 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
666 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
670 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
671 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
675 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
676 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
681 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
682 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
685 DRM_ERROR("Unsupported screen depth %d\n",
686 crtc->fb->bits_per_pixel);
690 if (tiling_flags & RADEON_TILING_MACRO)
691 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
693 if (tiling_flags & RADEON_TILING_MICRO)
694 fb_format |= AVIVO_D1GRPH_TILED;
696 if (radeon_crtc->crtc_id == 0)
697 WREG32(AVIVO_D1VGA_CONTROL, 0);
699 WREG32(AVIVO_D2VGA_CONTROL, 0);
701 if (rdev->family >= CHIP_RV770) {
702 if (radeon_crtc->crtc_id) {
703 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
704 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
706 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
707 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
710 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
712 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
713 radeon_crtc->crtc_offset, (u32) fb_location);
714 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
716 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
717 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
718 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
719 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
720 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
721 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
723 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
724 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
725 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
727 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
728 crtc->mode.vdisplay);
731 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
733 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
734 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
736 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
737 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
738 AVIVO_D1MODE_INTERLEAVE_EN);
740 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
742 if (old_fb && old_fb != crtc->fb) {
743 radeon_fb = to_radeon_framebuffer(old_fb);
744 rbo = radeon_fb->obj->driver_private;
745 r = radeon_bo_reserve(rbo, false);
746 if (unlikely(r != 0))
748 radeon_bo_unpin(rbo);
749 radeon_bo_unreserve(rbo);
752 /* Bytes per pixel may have changed */
753 radeon_bandwidth_update(rdev);
758 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
759 struct drm_framebuffer *old_fb)
761 struct drm_device *dev = crtc->dev;
762 struct radeon_device *rdev = dev->dev_private;
764 if (ASIC_IS_AVIVO(rdev))
765 return avivo_crtc_set_base(crtc, x, y, old_fb);
767 return radeon_crtc_set_base(crtc, x, y, old_fb);
770 /* properly set additional regs when using atombios */
771 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
773 struct drm_device *dev = crtc->dev;
774 struct radeon_device *rdev = dev->dev_private;
775 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
778 switch (radeon_crtc->crtc_id) {
780 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
781 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
782 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
785 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
786 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
787 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
788 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
789 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
794 int atombios_crtc_mode_set(struct drm_crtc *crtc,
795 struct drm_display_mode *mode,
796 struct drm_display_mode *adjusted_mode,
797 int x, int y, struct drm_framebuffer *old_fb)
799 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
800 struct drm_device *dev = crtc->dev;
801 struct radeon_device *rdev = dev->dev_private;
803 /* TODO color tiling */
805 atombios_set_ss(crtc, 0);
806 atombios_crtc_set_pll(crtc, adjusted_mode);
807 atombios_set_ss(crtc, 1);
808 atombios_crtc_set_timing(crtc, adjusted_mode);
810 if (ASIC_IS_AVIVO(rdev))
811 atombios_crtc_set_base(crtc, x, y, old_fb);
813 if (radeon_crtc->crtc_id == 0)
814 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
815 atombios_crtc_set_base(crtc, x, y, old_fb);
816 radeon_legacy_atom_fixup(crtc);
818 atombios_overscan_setup(crtc, mode, adjusted_mode);
819 atombios_scaler_setup(crtc);
823 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
824 struct drm_display_mode *mode,
825 struct drm_display_mode *adjusted_mode)
827 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
832 static void atombios_crtc_prepare(struct drm_crtc *crtc)
834 atombios_lock_crtc(crtc, 1);
835 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
838 static void atombios_crtc_commit(struct drm_crtc *crtc)
840 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
841 atombios_lock_crtc(crtc, 0);
844 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
845 .dpms = atombios_crtc_dpms,
846 .mode_fixup = atombios_crtc_mode_fixup,
847 .mode_set = atombios_crtc_mode_set,
848 .mode_set_base = atombios_crtc_set_base,
849 .prepare = atombios_crtc_prepare,
850 .commit = atombios_crtc_commit,
851 .load_lut = radeon_crtc_load_lut,
854 void radeon_atombios_init_crtc(struct drm_device *dev,
855 struct radeon_crtc *radeon_crtc)
857 if (radeon_crtc->crtc_id == 1)
858 radeon_crtc->crtc_offset =
859 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
860 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);