2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
31 MODULE_FIRMWARE("nouveau/nv50.ctxprog");
32 MODULE_FIRMWARE("nouveau/nv50.ctxvals");
33 MODULE_FIRMWARE("nouveau/nv84.ctxprog");
34 MODULE_FIRMWARE("nouveau/nv84.ctxvals");
35 MODULE_FIRMWARE("nouveau/nv86.ctxprog");
36 MODULE_FIRMWARE("nouveau/nv86.ctxvals");
37 MODULE_FIRMWARE("nouveau/nv92.ctxprog");
38 MODULE_FIRMWARE("nouveau/nv92.ctxvals");
39 MODULE_FIRMWARE("nouveau/nv94.ctxprog");
40 MODULE_FIRMWARE("nouveau/nv94.ctxvals");
41 MODULE_FIRMWARE("nouveau/nv96.ctxprog");
42 MODULE_FIRMWARE("nouveau/nv96.ctxvals");
43 MODULE_FIRMWARE("nouveau/nv98.ctxprog");
44 MODULE_FIRMWARE("nouveau/nv98.ctxvals");
45 MODULE_FIRMWARE("nouveau/nva0.ctxprog");
46 MODULE_FIRMWARE("nouveau/nva0.ctxvals");
47 MODULE_FIRMWARE("nouveau/nva5.ctxprog");
48 MODULE_FIRMWARE("nouveau/nva5.ctxvals");
49 MODULE_FIRMWARE("nouveau/nva8.ctxprog");
50 MODULE_FIRMWARE("nouveau/nva8.ctxvals");
51 MODULE_FIRMWARE("nouveau/nvaa.ctxprog");
52 MODULE_FIRMWARE("nouveau/nvaa.ctxvals");
53 MODULE_FIRMWARE("nouveau/nvac.ctxprog");
54 MODULE_FIRMWARE("nouveau/nvac.ctxvals");
56 #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
59 nv50_graph_init_reset(struct drm_device *dev)
61 uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
65 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
66 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
70 nv50_graph_init_intr(struct drm_device *dev)
74 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
75 nv_wr32(dev, 0x400138, 0xffffffff);
76 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
80 nv50_graph_init_regs__nv(struct drm_device *dev)
84 nv_wr32(dev, 0x400804, 0xc0000000);
85 nv_wr32(dev, 0x406800, 0xc0000000);
86 nv_wr32(dev, 0x400c04, 0xc0000000);
87 nv_wr32(dev, 0x401800, 0xc0000000);
88 nv_wr32(dev, 0x405018, 0xc0000000);
89 nv_wr32(dev, 0x402000, 0xc0000000);
91 nv_wr32(dev, 0x400108, 0xffffffff);
93 nv_wr32(dev, 0x400824, 0x00004000);
94 nv_wr32(dev, 0x400500, 0x00010001);
98 nv50_graph_init_regs(struct drm_device *dev)
102 nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
103 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
104 nv_wr32(dev, 0x402ca8, 0x800);
108 nv50_graph_init_ctxctl(struct drm_device *dev)
110 struct drm_nouveau_private *dev_priv = dev->dev_private;
114 nouveau_grctx_prog_load(dev);
115 if (!dev_priv->engine.graph.ctxprog)
116 dev_priv->engine.graph.accel_blocked = true;
118 nv_wr32(dev, 0x400320, 4);
119 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
120 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
125 nv50_graph_init(struct drm_device *dev)
131 nv50_graph_init_reset(dev);
132 nv50_graph_init_regs__nv(dev);
133 nv50_graph_init_regs(dev);
134 nv50_graph_init_intr(dev);
136 ret = nv50_graph_init_ctxctl(dev);
144 nv50_graph_takedown(struct drm_device *dev)
147 nouveau_grctx_fini(dev);
151 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
153 const uint32_t mask = 0x00010001;
156 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
158 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
161 struct nouveau_channel *
162 nv50_graph_channel(struct drm_device *dev)
164 struct drm_nouveau_private *dev_priv = dev->dev_private;
168 /* Be sure we're not in the middle of a context switch or bad things
169 * will happen, such as unloading the wrong pgraph context.
171 if (!nv_wait(0x400300, 0x00000001, 0x00000000))
172 NV_ERROR(dev, "Ctxprog is still running\n");
174 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
175 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
177 inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
179 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
180 struct nouveau_channel *chan = dev_priv->fifos[i];
182 if (chan && chan->ramin && chan->ramin->instance == inst)
190 nv50_graph_create_context(struct nouveau_channel *chan)
192 struct drm_device *dev = chan->dev;
193 struct drm_nouveau_private *dev_priv = dev->dev_private;
194 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
195 struct nouveau_gpuobj *ctx;
196 uint32_t grctx_size = 0x70000;
199 NV_DEBUG(dev, "ch%d\n", chan->id);
201 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
202 NVOBJ_FLAG_ZERO_ALLOC |
203 NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
206 ctx = chan->ramin_grctx->gpuobj;
208 hdr = IS_G80 ? 0x200 : 0x20;
209 dev_priv->engine.instmem.prepare_access(dev, true);
210 nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
211 nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
213 nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
214 nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
215 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
216 nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);
217 dev_priv->engine.instmem.finish_access(dev);
219 dev_priv->engine.instmem.prepare_access(dev, true);
220 nouveau_grctx_vals_load(dev, ctx);
221 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
222 if ((dev_priv->chipset & 0xf0) == 0xa0)
223 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
225 nv_wo32(dev, ctx, 0x0011c/4, 0x00000000);
226 dev_priv->engine.instmem.finish_access(dev);
232 nv50_graph_destroy_context(struct nouveau_channel *chan)
234 struct drm_device *dev = chan->dev;
235 struct drm_nouveau_private *dev_priv = dev->dev_private;
236 int i, hdr = IS_G80 ? 0x200 : 0x20;
238 NV_DEBUG(dev, "ch%d\n", chan->id);
240 if (!chan->ramin || !chan->ramin->gpuobj)
243 dev_priv->engine.instmem.prepare_access(dev, true);
244 for (i = hdr; i < hdr + 24; i += 4)
245 nv_wo32(dev, chan->ramin->gpuobj, i/4, 0);
246 dev_priv->engine.instmem.finish_access(dev);
248 nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
252 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
254 uint32_t fifo = nv_rd32(dev, 0x400500);
256 nv_wr32(dev, 0x400500, fifo & ~1);
257 nv_wr32(dev, 0x400784, inst);
258 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
259 nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
260 nv_wr32(dev, 0x400040, 0xffffffff);
261 (void)nv_rd32(dev, 0x400040);
262 nv_wr32(dev, 0x400040, 0x00000000);
263 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
265 if (nouveau_wait_for_idle(dev))
266 nv_wr32(dev, 0x40032c, inst | (1<<31));
267 nv_wr32(dev, 0x400500, fifo);
273 nv50_graph_load_context(struct nouveau_channel *chan)
275 uint32_t inst = chan->ramin->instance >> 12;
277 NV_DEBUG(chan->dev, "ch%d\n", chan->id);
278 return nv50_graph_do_load_context(chan->dev, inst);
282 nv50_graph_unload_context(struct drm_device *dev)
286 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
287 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
289 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
291 nouveau_wait_for_idle(dev);
292 nv_wr32(dev, 0x400784, inst);
293 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
294 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
295 nouveau_wait_for_idle(dev);
297 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
302 nv50_graph_context_switch(struct drm_device *dev)
306 nv50_graph_unload_context(dev);
308 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
309 inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
310 nv50_graph_do_load_context(dev, inst);
312 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
313 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
317 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
318 int mthd, uint32_t data)
320 struct nouveau_gpuobj_ref *ref = NULL;
322 if (nouveau_gpuobj_ref_find(chan, data, &ref))
325 if (nouveau_notifier_offset(ref->gpuobj, NULL))
328 chan->nvsw.vblsem = ref->gpuobj;
329 chan->nvsw.vblsem_offset = ~0;
334 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
335 int mthd, uint32_t data)
337 if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
340 chan->nvsw.vblsem_offset = data >> 2;
345 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
346 int mthd, uint32_t data)
348 chan->nvsw.vblsem_rval = data;
353 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
354 int mthd, uint32_t data)
356 struct drm_device *dev = chan->dev;
357 struct drm_nouveau_private *dev_priv = dev->dev_private;
359 if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
362 if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
363 NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
364 nv_wr32(dev, NV50_PDISPLAY_INTR_1,
365 NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
366 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
367 NV50_PDISPLAY_INTR_EN) |
368 NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
371 list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
375 static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
376 { 0x018c, nv50_graph_nvsw_dma_vblsem },
377 { 0x0400, nv50_graph_nvsw_vblsem_offset },
378 { 0x0404, nv50_graph_nvsw_vblsem_release_val },
379 { 0x0408, nv50_graph_nvsw_vblsem_release },
383 struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
384 { 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
385 { 0x0030, false, NULL }, /* null */
386 { 0x5039, false, NULL }, /* m2mf */
387 { 0x502d, false, NULL }, /* 2d */
388 { 0x50c0, false, NULL }, /* compute */
389 { 0x5097, false, NULL }, /* tesla (nv50) */
390 { 0x8297, false, NULL }, /* tesla (nv80/nv90) */
391 { 0x8397, false, NULL }, /* tesla (nva0) */
392 { 0x8597, false, NULL }, /* tesla (nva8) */