SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "drm_sarea.h"
  30 #include "drm_crtc_helper.h"
  31 #include <linux/vgaarb.h>
  32 #include <linux/vga_switcheroo.h>
  33
  34 #include "nouveau_drv.h"
  35 #include "nouveau_drm.h"
  36 #include "nv50_display.h"
  37
  38 static void nouveau_stub_takedown(struct drm_device *dev) {}
  39
  40 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  41 {
  42         struct drm_nouveau_private *dev_priv = dev->dev_private;
  43         struct nouveau_engine *engine = &dev_priv->engine;
  44
  45         switch (dev_priv->chipset & 0xf0) {
  46         case 0x00:
  47                 engine->instmem.init            = nv04_instmem_init;
  48                 engine->instmem.takedown        = nv04_instmem_takedown;
  49                 engine->instmem.suspend         = nv04_instmem_suspend;
  50                 engine->instmem.resume          = nv04_instmem_resume;
  51                 engine->instmem.populate        = nv04_instmem_populate;
  52                 engine->instmem.clear           = nv04_instmem_clear;
  53                 engine->instmem.bind            = nv04_instmem_bind;
  54                 engine->instmem.unbind          = nv04_instmem_unbind;
  55                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  56                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  57                 engine->mc.init                 = nv04_mc_init;
  58                 engine->mc.takedown             = nv04_mc_takedown;
  59                 engine->timer.init              = nv04_timer_init;
  60                 engine->timer.read              = nv04_timer_read;
  61                 engine->timer.takedown          = nv04_timer_takedown;
  62                 engine->fb.init                 = nv04_fb_init;
  63                 engine->fb.takedown             = nv04_fb_takedown;
  64                 engine->graph.grclass           = nv04_graph_grclass;
  65                 engine->graph.init              = nv04_graph_init;
  66                 engine->graph.takedown          = nv04_graph_takedown;
  67                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  68                 engine->graph.channel           = nv04_graph_channel;
  69                 engine->graph.create_context    = nv04_graph_create_context;
  70                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  71                 engine->graph.load_context      = nv04_graph_load_context;
  72                 engine->graph.unload_context    = nv04_graph_unload_context;
  73                 engine->fifo.channels           = 16;
  74                 engine->fifo.init               = nv04_fifo_init;
  75                 engine->fifo.takedown           = nouveau_stub_takedown;
  76                 engine->fifo.disable            = nv04_fifo_disable;
  77                 engine->fifo.enable             = nv04_fifo_enable;
  78                 engine->fifo.reassign           = nv04_fifo_reassign;
  79                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  80                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  81                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  82                 engine->fifo.create_context     = nv04_fifo_create_context;
  83                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  84                 engine->fifo.load_context       = nv04_fifo_load_context;
  85                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  86                 break;
  87         case 0x10:
  88                 engine->instmem.init            = nv04_instmem_init;
  89                 engine->instmem.takedown        = nv04_instmem_takedown;
  90                 engine->instmem.suspend         = nv04_instmem_suspend;
  91                 engine->instmem.resume          = nv04_instmem_resume;
  92                 engine->instmem.populate        = nv04_instmem_populate;
  93                 engine->instmem.clear           = nv04_instmem_clear;
  94                 engine->instmem.bind            = nv04_instmem_bind;
  95                 engine->instmem.unbind          = nv04_instmem_unbind;
  96                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
  97                 engine->instmem.finish_access   = nv04_instmem_finish_access;
  98                 engine->mc.init                 = nv04_mc_init;
  99                 engine->mc.takedown             = nv04_mc_takedown;
 100                 engine->timer.init              = nv04_timer_init;
 101                 engine->timer.read              = nv04_timer_read;
 102                 engine->timer.takedown          = nv04_timer_takedown;
 103                 engine->fb.init                 = nv10_fb_init;
 104                 engine->fb.takedown             = nv10_fb_takedown;
 105                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 106                 engine->graph.grclass           = nv10_graph_grclass;
 107                 engine->graph.init              = nv10_graph_init;
 108                 engine->graph.takedown          = nv10_graph_takedown;
 109                 engine->graph.channel           = nv10_graph_channel;
 110                 engine->graph.create_context    = nv10_graph_create_context;
 111                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 112                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 113                 engine->graph.load_context      = nv10_graph_load_context;
 114                 engine->graph.unload_context    = nv10_graph_unload_context;
 115                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 116                 engine->fifo.channels           = 32;
 117                 engine->fifo.init               = nv10_fifo_init;
 118                 engine->fifo.takedown           = nouveau_stub_takedown;
 119                 engine->fifo.disable            = nv04_fifo_disable;
 120                 engine->fifo.enable             = nv04_fifo_enable;
 121                 engine->fifo.reassign           = nv04_fifo_reassign;
 122                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 123                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 124                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 125                 engine->fifo.create_context     = nv10_fifo_create_context;
 126                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 127                 engine->fifo.load_context       = nv10_fifo_load_context;
 128                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 129                 break;
 130         case 0x20:
 131                 engine->instmem.init            = nv04_instmem_init;
 132                 engine->instmem.takedown        = nv04_instmem_takedown;
 133                 engine->instmem.suspend         = nv04_instmem_suspend;
 134                 engine->instmem.resume          = nv04_instmem_resume;
 135                 engine->instmem.populate        = nv04_instmem_populate;
 136                 engine->instmem.clear           = nv04_instmem_clear;
 137                 engine->instmem.bind            = nv04_instmem_bind;
 138                 engine->instmem.unbind          = nv04_instmem_unbind;
 139                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 140                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 141                 engine->mc.init                 = nv04_mc_init;
 142                 engine->mc.takedown             = nv04_mc_takedown;
 143                 engine->timer.init              = nv04_timer_init;
 144                 engine->timer.read              = nv04_timer_read;
 145                 engine->timer.takedown          = nv04_timer_takedown;
 146                 engine->fb.init                 = nv10_fb_init;
 147                 engine->fb.takedown             = nv10_fb_takedown;
 148                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 149                 engine->graph.grclass           = nv20_graph_grclass;
 150                 engine->graph.init              = nv20_graph_init;
 151                 engine->graph.takedown          = nv20_graph_takedown;
 152                 engine->graph.channel           = nv10_graph_channel;
 153                 engine->graph.create_context    = nv20_graph_create_context;
 154                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 155                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 156                 engine->graph.load_context      = nv20_graph_load_context;
 157                 engine->graph.unload_context    = nv20_graph_unload_context;
 158                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 159                 engine->fifo.channels           = 32;
 160                 engine->fifo.init               = nv10_fifo_init;
 161                 engine->fifo.takedown           = nouveau_stub_takedown;
 162                 engine->fifo.disable            = nv04_fifo_disable;
 163                 engine->fifo.enable             = nv04_fifo_enable;
 164                 engine->fifo.reassign           = nv04_fifo_reassign;
 165                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 166                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 167                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 168                 engine->fifo.create_context     = nv10_fifo_create_context;
 169                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 170                 engine->fifo.load_context       = nv10_fifo_load_context;
 171                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 172                 break;
 173         case 0x30:
 174                 engine->instmem.init            = nv04_instmem_init;
 175                 engine->instmem.takedown        = nv04_instmem_takedown;
 176                 engine->instmem.suspend         = nv04_instmem_suspend;
 177                 engine->instmem.resume          = nv04_instmem_resume;
 178                 engine->instmem.populate        = nv04_instmem_populate;
 179                 engine->instmem.clear           = nv04_instmem_clear;
 180                 engine->instmem.bind            = nv04_instmem_bind;
 181                 engine->instmem.unbind          = nv04_instmem_unbind;
 182                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 183                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 184                 engine->mc.init                 = nv04_mc_init;
 185                 engine->mc.takedown             = nv04_mc_takedown;
 186                 engine->timer.init              = nv04_timer_init;
 187                 engine->timer.read              = nv04_timer_read;
 188                 engine->timer.takedown          = nv04_timer_takedown;
 189                 engine->fb.init                 = nv10_fb_init;
 190                 engine->fb.takedown             = nv10_fb_takedown;
 191                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 192                 engine->graph.grclass           = nv30_graph_grclass;
 193                 engine->graph.init              = nv30_graph_init;
 194                 engine->graph.takedown          = nv20_graph_takedown;
 195                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 196                 engine->graph.channel           = nv10_graph_channel;
 197                 engine->graph.create_context    = nv20_graph_create_context;
 198                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 199                 engine->graph.load_context      = nv20_graph_load_context;
 200                 engine->graph.unload_context    = nv20_graph_unload_context;
 201                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 202                 engine->fifo.channels           = 32;
 203                 engine->fifo.init               = nv10_fifo_init;
 204                 engine->fifo.takedown           = nouveau_stub_takedown;
 205                 engine->fifo.disable            = nv04_fifo_disable;
 206                 engine->fifo.enable             = nv04_fifo_enable;
 207                 engine->fifo.reassign           = nv04_fifo_reassign;
 208                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 209                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 210                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 211                 engine->fifo.create_context     = nv10_fifo_create_context;
 212                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 213                 engine->fifo.load_context       = nv10_fifo_load_context;
 214                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 215                 break;
 216         case 0x40:
 217         case 0x60:
 218                 engine->instmem.init            = nv04_instmem_init;
 219                 engine->instmem.takedown        = nv04_instmem_takedown;
 220                 engine->instmem.suspend         = nv04_instmem_suspend;
 221                 engine->instmem.resume          = nv04_instmem_resume;
 222                 engine->instmem.populate        = nv04_instmem_populate;
 223                 engine->instmem.clear           = nv04_instmem_clear;
 224                 engine->instmem.bind            = nv04_instmem_bind;
 225                 engine->instmem.unbind          = nv04_instmem_unbind;
 226                 engine->instmem.prepare_access  = nv04_instmem_prepare_access;
 227                 engine->instmem.finish_access   = nv04_instmem_finish_access;
 228                 engine->mc.init                 = nv40_mc_init;
 229                 engine->mc.takedown             = nv40_mc_takedown;
 230                 engine->timer.init              = nv04_timer_init;
 231                 engine->timer.read              = nv04_timer_read;
 232                 engine->timer.takedown          = nv04_timer_takedown;
 233                 engine->fb.init                 = nv40_fb_init;
 234                 engine->fb.takedown             = nv40_fb_takedown;
 235                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 236                 engine->graph.grclass           = nv40_graph_grclass;
 237                 engine->graph.init              = nv40_graph_init;
 238                 engine->graph.takedown          = nv40_graph_takedown;
 239                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 240                 engine->graph.channel           = nv40_graph_channel;
 241                 engine->graph.create_context    = nv40_graph_create_context;
 242                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 243                 engine->graph.load_context      = nv40_graph_load_context;
 244                 engine->graph.unload_context    = nv40_graph_unload_context;
 245                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 246                 engine->fifo.channels           = 32;
 247                 engine->fifo.init               = nv40_fifo_init;
 248                 engine->fifo.takedown           = nouveau_stub_takedown;
 249                 engine->fifo.disable            = nv04_fifo_disable;
 250                 engine->fifo.enable             = nv04_fifo_enable;
 251                 engine->fifo.reassign           = nv04_fifo_reassign;
 252                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 253                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 254                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 255                 engine->fifo.create_context     = nv40_fifo_create_context;
 256                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 257                 engine->fifo.load_context       = nv40_fifo_load_context;
 258                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 259                 break;
 260         case 0x50:
 261         case 0x80: /* gotta love NVIDIA's consistency.. */
 262         case 0x90:
 263         case 0xA0:
 264                 engine->instmem.init            = nv50_instmem_init;
 265                 engine->instmem.takedown        = nv50_instmem_takedown;
 266                 engine->instmem.suspend         = nv50_instmem_suspend;
 267                 engine->instmem.resume          = nv50_instmem_resume;
 268                 engine->instmem.populate        = nv50_instmem_populate;
 269                 engine->instmem.clear           = nv50_instmem_clear;
 270                 engine->instmem.bind            = nv50_instmem_bind;
 271                 engine->instmem.unbind          = nv50_instmem_unbind;
 272                 engine->instmem.prepare_access  = nv50_instmem_prepare_access;
 273                 engine->instmem.finish_access   = nv50_instmem_finish_access;
 274                 engine->mc.init                 = nv50_mc_init;
 275                 engine->mc.takedown             = nv50_mc_takedown;
 276                 engine->timer.init              = nv04_timer_init;
 277                 engine->timer.read              = nv04_timer_read;
 278                 engine->timer.takedown          = nv04_timer_takedown;
 279                 engine->fb.init                 = nv50_fb_init;
 280                 engine->fb.takedown             = nv50_fb_takedown;
 281                 engine->graph.grclass           = nv50_graph_grclass;
 282                 engine->graph.init              = nv50_graph_init;
 283                 engine->graph.takedown          = nv50_graph_takedown;
 284                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 285                 engine->graph.channel           = nv50_graph_channel;
 286                 engine->graph.create_context    = nv50_graph_create_context;
 287                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 288                 engine->graph.load_context      = nv50_graph_load_context;
 289                 engine->graph.unload_context    = nv50_graph_unload_context;
 290                 engine->fifo.channels           = 128;
 291                 engine->fifo.init               = nv50_fifo_init;
 292                 engine->fifo.takedown           = nv50_fifo_takedown;
 293                 engine->fifo.disable            = nv04_fifo_disable;
 294                 engine->fifo.enable             = nv04_fifo_enable;
 295                 engine->fifo.reassign           = nv04_fifo_reassign;
 296                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 297                 engine->fifo.create_context     = nv50_fifo_create_context;
 298                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 299                 engine->fifo.load_context       = nv50_fifo_load_context;
 300                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 301                 break;
 302         default:
 303                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 304                 return 1;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static unsigned int
 311 nouveau_vga_set_decode(void *priv, bool state)
 312 {
 313         struct drm_device *dev = priv;
 314         struct drm_nouveau_private *dev_priv = dev->dev_private;
 315
 316         if (dev_priv->chipset >= 0x40)
 317                 nv_wr32(dev, 0x88054, state);
 318         else
 319                 nv_wr32(dev, 0x1854, state);
 320
 321         if (state)
 322                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 323                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 324         else
 325                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326 }
 327
 328 static int
 329 nouveau_card_init_channel(struct drm_device *dev)
 330 {
 331         struct drm_nouveau_private *dev_priv = dev->dev_private;
 332         struct nouveau_gpuobj *gpuobj;
 333         int ret;
 334
 335         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 336                                     (struct drm_file *)-2,
 337                                     NvDmaFB, NvDmaTT);
 338         if (ret)
 339                 return ret;
 340
 341         gpuobj = NULL;
 342         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 343                                      0, dev_priv->vram_size,
 344                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 345                                      &gpuobj);
 346         if (ret)
 347                 goto out_err;
 348
 349         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
 350                                      gpuobj, NULL);
 351         if (ret)
 352                 goto out_err;
 353
 354         gpuobj = NULL;
 355         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 356                                           dev_priv->gart_info.aper_size,
 357                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 358         if (ret)
 359                 goto out_err;
 360
 361         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
 362                                      gpuobj, NULL);
 363         if (ret)
 364                 goto out_err;
 365
 366         return 0;
 367 out_err:
 368         nouveau_gpuobj_del(dev, &gpuobj);
 369         nouveau_channel_free(dev_priv->channel);
 370         dev_priv->channel = NULL;
 371         return ret;
 372 }
 373
 374 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 375                                          enum vga_switcheroo_state state)
 376 {
 377         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 378         if (state == VGA_SWITCHEROO_ON) {
 379                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 380                 nouveau_pci_resume(pdev);
 381         } else {
 382                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 383                 nouveau_pci_suspend(pdev, pmm);
 384         }
 385 }
 386
 387 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 388 {
 389         struct drm_device *dev = pci_get_drvdata(pdev);
 390         bool can_switch;
 391
 392         spin_lock(&dev->count_lock);
 393         can_switch = (dev->open_count == 0);
 394         spin_unlock(&dev->count_lock);
 395         return can_switch;
 396 }
 397
 398 int
 399 nouveau_card_init(struct drm_device *dev)
 400 {
 401         struct drm_nouveau_private *dev_priv = dev->dev_private;
 402         struct nouveau_engine *engine;
 403         int ret;
 404
 405         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 406
 407         if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
 408                 return 0;
 409
 410         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 411         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 412                                        nouveau_switcheroo_can_switch);
 413
 414         /* Initialise internal driver API hooks */
 415         ret = nouveau_init_engine_ptrs(dev);
 416         if (ret)
 417                 goto out;
 418         engine = &dev_priv->engine;
 419         dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
 420         spin_lock_init(&dev_priv->context_switch_lock);
 421
 422         /* Parse BIOS tables / Run init tables if card not POSTed */
 423         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 424                 ret = nouveau_bios_init(dev);
 425                 if (ret)
 426                         goto out;
 427         }
 428
 429         ret = nouveau_mem_detect(dev);
 430         if (ret)
 431                 goto out_bios;
 432
 433         ret = nouveau_gpuobj_early_init(dev);
 434         if (ret)
 435                 goto out_bios;
 436
 437         /* Initialise instance memory, must happen before mem_init so we
 438          * know exactly how much VRAM we're able to use for "normal"
 439          * purposes.
 440          */
 441         ret = engine->instmem.init(dev);
 442         if (ret)
 443                 goto out_gpuobj_early;
 444
 445         /* Setup the memory manager */
 446         ret = nouveau_mem_init(dev);
 447         if (ret)
 448                 goto out_instmem;
 449
 450         ret = nouveau_gpuobj_init(dev);
 451         if (ret)
 452                 goto out_mem;
 453
 454         /* PMC */
 455         ret = engine->mc.init(dev);
 456         if (ret)
 457                 goto out_gpuobj;
 458
 459         /* PTIMER */
 460         ret = engine->timer.init(dev);
 461         if (ret)
 462                 goto out_mc;
 463
 464         /* PFB */
 465         ret = engine->fb.init(dev);
 466         if (ret)
 467                 goto out_timer;
 468
 469         if (nouveau_noaccel)
 470                 engine->graph.accel_blocked = true;
 471         else {
 472                 /* PGRAPH */
 473                 ret = engine->graph.init(dev);
 474                 if (ret)
 475                         goto out_fb;
 476
 477                 /* PFIFO */
 478                 ret = engine->fifo.init(dev);
 479                 if (ret)
 480                         goto out_graph;
 481         }
 482
 483         /* this call irq_preinstall, register irq handler and
 484          * call irq_postinstall
 485          */
 486         ret = drm_irq_install(dev);
 487         if (ret)
 488                 goto out_fifo;
 489
 490         ret = drm_vblank_init(dev, 0);
 491         if (ret)
 492                 goto out_irq;
 493
 494         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 495
 496         if (!engine->graph.accel_blocked) {
 497                 ret = nouveau_card_init_channel(dev);
 498                 if (ret)
 499                         goto out_irq;
 500         }
 501
 502         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 503                 if (dev_priv->card_type >= NV_50)
 504                         ret = nv50_display_create(dev);
 505                 else
 506                         ret = nv04_display_create(dev);
 507                 if (ret)
 508                         goto out_channel;
 509         }
 510
 511         ret = nouveau_backlight_init(dev);
 512         if (ret)
 513                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 514
 515         dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
 516
 517         if (drm_core_check_feature(dev, DRIVER_MODESET))
 518                 drm_helper_initial_config(dev);
 519
 520         return 0;
 521
 522 out_channel:
 523         if (dev_priv->channel) {
 524                 nouveau_channel_free(dev_priv->channel);
 525                 dev_priv->channel = NULL;
 526         }
 527 out_irq:
 528         drm_irq_uninstall(dev);
 529 out_fifo:
 530         if (!nouveau_noaccel)
 531                 engine->fifo.takedown(dev);
 532 out_graph:
 533         if (!nouveau_noaccel)
 534                 engine->graph.takedown(dev);
 535 out_fb:
 536         engine->fb.takedown(dev);
 537 out_timer:
 538         engine->timer.takedown(dev);
 539 out_mc:
 540         engine->mc.takedown(dev);
 541 out_gpuobj:
 542         nouveau_gpuobj_takedown(dev);
 543 out_mem:
 544         nouveau_sgdma_takedown(dev);
 545         nouveau_mem_close(dev);
 546 out_instmem:
 547         engine->instmem.takedown(dev);
 548 out_gpuobj_early:
 549         nouveau_gpuobj_late_takedown(dev);
 550 out_bios:
 551         nouveau_bios_takedown(dev);
 552 out:
 553         vga_client_register(dev->pdev, NULL, NULL, NULL);
 554         return ret;
 555 }
 556
 557 static void nouveau_card_takedown(struct drm_device *dev)
 558 {
 559         struct drm_nouveau_private *dev_priv = dev->dev_private;
 560         struct nouveau_engine *engine = &dev_priv->engine;
 561
 562         NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
 563
 564         if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
 565                 nouveau_backlight_exit(dev);
 566
 567                 if (dev_priv->channel) {
 568                         nouveau_channel_free(dev_priv->channel);
 569                         dev_priv->channel = NULL;
 570                 }
 571
 572                 if (!nouveau_noaccel) {
 573                         engine->fifo.takedown(dev);
 574                         engine->graph.takedown(dev);
 575                 }
 576                 engine->fb.takedown(dev);
 577                 engine->timer.takedown(dev);
 578                 engine->mc.takedown(dev);
 579
 580                 mutex_lock(&dev->struct_mutex);
 581                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 582                 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 583                 mutex_unlock(&dev->struct_mutex);
 584                 nouveau_sgdma_takedown(dev);
 585
 586                 nouveau_gpuobj_takedown(dev);
 587                 nouveau_mem_close(dev);
 588                 engine->instmem.takedown(dev);
 589
 590                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 591                         drm_irq_uninstall(dev);
 592
 593                 nouveau_gpuobj_late_takedown(dev);
 594                 nouveau_bios_takedown(dev);
 595
 596                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 597
 598                 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 599         }
 600 }
 601
 602 /* here a client dies, release the stuff that was allocated for its
 603  * file_priv */
 604 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 605 {
 606         nouveau_channel_cleanup(dev, file_priv);
 607 }
 608
 609 /* first module load, setup the mmio/fb mapping */
 610 /* KMS: we need mmio at load time, not when the first drm client opens. */
 611 int nouveau_firstopen(struct drm_device *dev)
 612 {
 613         return 0;
 614 }
 615
 616 /* if we have an OF card, copy vbios to RAMIN */
 617 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 618 {
 619 #if defined(__powerpc__)
 620         int size, i;
 621         const uint32_t *bios;
 622         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 623         if (!dn) {
 624                 NV_INFO(dev, "Unable to get the OF node\n");
 625                 return;
 626         }
 627
 628         bios = of_get_property(dn, "NVDA,BMP", &size);
 629         if (bios) {
 630                 for (i = 0; i < size; i += 4)
 631                         nv_wi32(dev, i, bios[i/4]);
 632                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 633         } else {
 634                 NV_INFO(dev, "Unable to get the OF bios\n");
 635         }
 636 #endif
 637 }
 638
 639 int nouveau_load(struct drm_device *dev, unsigned long flags)
 640 {
 641         struct drm_nouveau_private *dev_priv;
 642         uint32_t reg0;
 643         resource_size_t mmio_start_offs;
 644
 645         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 646         if (!dev_priv)
 647                 return -ENOMEM;
 648         dev->dev_private = dev_priv;
 649         dev_priv->dev = dev;
 650
 651         dev_priv->flags = flags & NOUVEAU_FLAGS;
 652         dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
 653
 654         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 655                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 656
 657         dev_priv->wq = create_workqueue("nouveau");
 658         if (!dev_priv->wq)
 659                 return -EINVAL;
 660
 661         /* resource 0 is mmio regs */
 662         /* resource 1 is linear FB */
 663         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 664         /* resource 6 is bios */
 665
 666         /* map the mmio regs */
 667         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 668         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 669         if (!dev_priv->mmio) {
 670                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 671                          "Please report your setup to " DRIVER_EMAIL "\n");
 672                 return -EINVAL;
 673         }
 674         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 675                                         (unsigned long long)mmio_start_offs);
 676
 677 #ifdef __BIG_ENDIAN
 678         /* Put the card in BE mode if it's not */
 679         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 680                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 681
 682         DRM_MEMORYBARRIER();
 683 #endif
 684
 685         /* Time to determine the card architecture */
 686         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 687
 688         /* We're dealing with >=NV10 */
 689         if ((reg0 & 0x0f000000) > 0) {
 690                 /* Bit 27-20 contain the architecture in hex */
 691                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 692         /* NV04 or NV05 */
 693         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 694                 if (reg0 & 0x00f00000)
 695                         dev_priv->chipset = 0x05;
 696                 else
 697                         dev_priv->chipset = 0x04;
 698         } else
 699                 dev_priv->chipset = 0xff;
 700
 701         switch (dev_priv->chipset & 0xf0) {
 702         case 0x00:
 703         case 0x10:
 704         case 0x20:
 705         case 0x30:
 706                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 707                 break;
 708         case 0x40:
 709         case 0x60:
 710                 dev_priv->card_type = NV_40;
 711                 break;
 712         case 0x50:
 713         case 0x80:
 714         case 0x90:
 715         case 0xa0:
 716                 dev_priv->card_type = NV_50;
 717                 break;
 718         default:
 719                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 720                 return -EINVAL;
 721         }
 722
 723         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 724                 dev_priv->card_type, reg0);
 725
 726         /* map larger RAMIN aperture on NV40 cards */
 727         dev_priv->ramin  = NULL;
 728         if (dev_priv->card_type >= NV_40) {
 729                 int ramin_bar = 2;
 730                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 731                         ramin_bar = 3;
 732
 733                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 734                 dev_priv->ramin = ioremap(
 735                                 pci_resource_start(dev->pdev, ramin_bar),
 736                                 dev_priv->ramin_size);
 737                 if (!dev_priv->ramin) {
 738                         NV_ERROR(dev, "Failed to init RAMIN mapping, "
 739                                       "limited instance memory available\n");
 740                 }
 741         }
 742
 743         /* On older cards (or if the above failed), create a map covering
 744          * the BAR0 PRAMIN aperture */
 745         if (!dev_priv->ramin) {
 746                 dev_priv->ramin_size = 1 * 1024 * 1024;
 747                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 748                                                         dev_priv->ramin_size);
 749                 if (!dev_priv->ramin) {
 750                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 751                         return -ENOMEM;
 752                 }
 753         }
 754
 755         nouveau_OF_copy_vbios_to_ramin(dev);
 756
 757         /* Special flags */
 758         if (dev->pci_device == 0x01a0)
 759                 dev_priv->flags |= NV_NFORCE;
 760         else if (dev->pci_device == 0x01f0)
 761                 dev_priv->flags |= NV_NFORCE2;
 762
 763         /* For kernel modesetting, init card now and bring up fbcon */
 764         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 765                 int ret = nouveau_card_init(dev);
 766                 if (ret)
 767                         return ret;
 768         }
 769
 770         return 0;
 771 }
 772
 773 static void nouveau_close(struct drm_device *dev)
 774 {
 775         struct drm_nouveau_private *dev_priv = dev->dev_private;
 776
 777         /* In the case of an error dev_priv may not be allocated yet */
 778         if (dev_priv)
 779                 nouveau_card_takedown(dev);
 780 }
 781
 782 /* KMS: we need mmio at load time, not when the first drm client opens. */
 783 void nouveau_lastclose(struct drm_device *dev)
 784 {
 785         if (drm_core_check_feature(dev, DRIVER_MODESET))
 786                 return;
 787
 788         nouveau_close(dev);
 789 }
 790
 791 int nouveau_unload(struct drm_device *dev)
 792 {
 793         struct drm_nouveau_private *dev_priv = dev->dev_private;
 794
 795         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 796                 if (dev_priv->card_type >= NV_50)
 797                         nv50_display_destroy(dev);
 798                 else
 799                         nv04_display_destroy(dev);
 800                 nouveau_close(dev);
 801         }
 802
 803         iounmap(dev_priv->mmio);
 804         iounmap(dev_priv->ramin);
 805
 806         kfree(dev_priv);
 807         dev->dev_private = NULL;
 808         return 0;
 809 }
 810
 811 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 812                                                 struct drm_file *file_priv)
 813 {
 814         struct drm_nouveau_private *dev_priv = dev->dev_private;
 815         struct drm_nouveau_getparam *getparam = data;
 816
 817         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 818
 819         switch (getparam->param) {
 820         case NOUVEAU_GETPARAM_CHIPSET_ID:
 821                 getparam->value = dev_priv->chipset;
 822                 break;
 823         case NOUVEAU_GETPARAM_PCI_VENDOR:
 824                 getparam->value = dev->pci_vendor;
 825                 break;
 826         case NOUVEAU_GETPARAM_PCI_DEVICE:
 827                 getparam->value = dev->pci_device;
 828                 break;
 829         case NOUVEAU_GETPARAM_BUS_TYPE:
 830                 if (drm_device_is_agp(dev))
 831                         getparam->value = NV_AGP;
 832                 else if (drm_device_is_pcie(dev))
 833                         getparam->value = NV_PCIE;
 834                 else
 835                         getparam->value = NV_PCI;
 836                 break;
 837         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 838                 getparam->value = dev_priv->fb_phys;
 839                 break;
 840         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 841                 getparam->value = dev_priv->gart_info.aper_base;
 842                 break;
 843         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 844                 if (dev->sg) {
 845                         getparam->value = (unsigned long)dev->sg->virtual;
 846                 } else {
 847                         NV_ERROR(dev, "Requested PCIGART address, "
 848                                         "while no PCIGART was created\n");
 849                         return -EINVAL;
 850                 }
 851                 break;
 852         case NOUVEAU_GETPARAM_FB_SIZE:
 853                 getparam->value = dev_priv->fb_available_size;
 854                 break;
 855         case NOUVEAU_GETPARAM_AGP_SIZE:
 856                 getparam->value = dev_priv->gart_info.aper_size;
 857                 break;
 858         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
 859                 getparam->value = dev_priv->vm_vram_base;
 860                 break;
 861         case NOUVEAU_GETPARAM_GRAPH_UNITS:
 862                 /* NV40 and NV50 versions are quite different, but register
 863                  * address is the same. User is supposed to know the card
 864                  * family anyway... */
 865                 if (dev_priv->chipset >= 0x40) {
 866                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
 867                         break;
 868                 }
 869                 /* FALLTHRU */
 870         default:
 871                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
 872                 return -EINVAL;
 873         }
 874
 875         return 0;
 876 }
 877
 878 int
 879 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
 880                        struct drm_file *file_priv)
 881 {
 882         struct drm_nouveau_setparam *setparam = data;
 883
 884         NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
 885
 886         switch (setparam->param) {
 887         default:
 888                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
 889                 return -EINVAL;
 890         }
 891
 892         return 0;
 893 }
 894
 895 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 896 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 897                         uint32_t reg, uint32_t mask, uint32_t val)
 898 {
 899         struct drm_nouveau_private *dev_priv = dev->dev_private;
 900         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 901         uint64_t start = ptimer->read(dev);
 902
 903         do {
 904                 if ((nv_rd32(dev, reg) & mask) == val)
 905                         return true;
 906         } while (ptimer->read(dev) - start < timeout);
 907
 908         return false;
 909 }
 910
 911 /* Waits for PGRAPH to go completely idle */
 912 bool nouveau_wait_for_idle(struct drm_device *dev)
 913 {
 914         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
 915                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
 916                          nv_rd32(dev, NV04_PGRAPH_STATUS));
 917                 return false;
 918         }
 919
 920         return true;
 921 }
 922