2 * Copyright (C) 2006 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Ben Skeggs <darktama@iinet.net.au>
35 #include "nouveau_drm.h"
36 #include "nouveau_drv.h"
37 #include "nouveau_reg.h"
38 #include <linux/ratelimit.h>
40 /* needed for hotplug irq */
41 #include "nouveau_connector.h"
42 #include "nv50_display.h"
45 nouveau_irq_preinstall(struct drm_device *dev)
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
50 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
52 if (dev_priv->card_type == NV_50) {
53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
54 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
59 nouveau_irq_postinstall(struct drm_device *dev)
62 nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
67 nouveau_irq_uninstall(struct drm_device *dev)
70 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
74 nouveau_call_method(struct nouveau_channel *chan, int class, int mthd, int data)
76 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
77 struct nouveau_pgraph_object_method *grm;
78 struct nouveau_pgraph_object_class *grc;
80 grc = dev_priv->engine.graph.grclass;
87 if (grc->id != class || !grc->methods)
93 return grm->exec(chan, class, mthd, data);
101 nouveau_fifo_swmthd(struct nouveau_channel *chan, uint32_t addr, uint32_t data)
103 struct drm_device *dev = chan->dev;
104 const int subc = (addr >> 13) & 0x7;
105 const int mthd = addr & 0x1ffc;
107 if (mthd == 0x0000) {
108 struct nouveau_gpuobj_ref *ref = NULL;
110 if (nouveau_gpuobj_ref_find(chan, data, &ref))
113 if (ref->gpuobj->engine != NVOBJ_ENGINE_SW)
116 chan->sw_subchannel[subc] = ref->gpuobj->class;
117 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_rd32(dev,
118 NV04_PFIFO_CACHE1_ENGINE) & ~(0xf << subc * 4));
123 if (nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE) & (1 << (subc*4)))
126 if (nouveau_call_method(chan, chan->sw_subchannel[subc], mthd, data))
133 nouveau_fifo_irq_handler(struct drm_device *dev)
135 struct drm_nouveau_private *dev_priv = dev->dev_private;
136 struct nouveau_engine *engine = &dev_priv->engine;
137 uint32_t status, reassign;
140 reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
141 while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
142 struct nouveau_channel *chan = NULL;
145 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
147 chid = engine->fifo.channel_id(dev);
148 if (chid >= 0 && chid < engine->fifo.channels)
149 chan = dev_priv->fifos[chid];
150 get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
152 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
156 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
157 * wrapping on my G80 chips, but CACHE1 isn't big
158 * enough for this much data.. Tests show that it
159 * wraps around to the start at GET=0x800.. No clue
162 ptr = (get & 0x7ff) >> 2;
164 if (dev_priv->card_type < NV_40) {
166 NV04_PFIFO_CACHE1_METHOD(ptr));
168 NV04_PFIFO_CACHE1_DATA(ptr));
171 NV40_PFIFO_CACHE1_METHOD(ptr));
173 NV40_PFIFO_CACHE1_DATA(ptr));
176 if (!chan || !nouveau_fifo_swmthd(chan, mthd, data)) {
177 NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
178 "Mthd 0x%04x Data 0x%08x\n",
179 chid, (mthd >> 13) & 7, mthd & 0x1ffc,
183 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
184 nv_wr32(dev, NV03_PFIFO_INTR_0,
185 NV_PFIFO_INTR_CACHE_ERROR);
187 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
188 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
189 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
190 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
191 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
192 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
194 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
195 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
196 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
198 status &= ~NV_PFIFO_INTR_CACHE_ERROR;
201 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
202 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d\n", chid);
204 status &= ~NV_PFIFO_INTR_DMA_PUSHER;
205 nv_wr32(dev, NV03_PFIFO_INTR_0,
206 NV_PFIFO_INTR_DMA_PUSHER);
208 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
209 if (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT) != get)
210 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET,
214 if (status & NV_PFIFO_INTR_SEMAPHORE) {
217 status &= ~NV_PFIFO_INTR_SEMAPHORE;
218 nv_wr32(dev, NV03_PFIFO_INTR_0,
219 NV_PFIFO_INTR_SEMAPHORE);
221 sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
222 nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
224 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
225 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
229 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
231 nv_wr32(dev, NV03_PFIFO_INTR_0, status);
235 nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
239 NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
240 nv_wr32(dev, 0x2140, 0);
241 nv_wr32(dev, 0x140, 0);
244 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
247 struct nouveau_bitfield_names {
252 static struct nouveau_bitfield_names nstatus_names[] =
254 { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
255 { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
256 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
257 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
260 static struct nouveau_bitfield_names nstatus_names_nv10[] =
262 { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
263 { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
264 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
265 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
268 static struct nouveau_bitfield_names nsource_names[] =
270 { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
271 { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
272 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
273 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
274 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
275 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
276 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
277 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
278 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
279 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
280 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
281 { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
282 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
283 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
284 { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
285 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
286 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
287 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
288 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
292 nouveau_print_bitfield_names_(uint32_t value,
293 const struct nouveau_bitfield_names *namelist,
294 const int namelist_len)
297 * Caller must have already printed the KERN_* log level for us.
298 * Also the caller is responsible for adding the newline.
301 for (i = 0; i < namelist_len; ++i) {
302 uint32_t mask = namelist[i].mask;
304 printk(" %s", namelist[i].name);
309 printk(" (unknown bits 0x%08x)", value);
311 #define nouveau_print_bitfield_names(val, namelist) \
312 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
314 struct nouveau_enum_names {
320 nouveau_print_enum_names_(uint32_t value,
321 const struct nouveau_enum_names *namelist,
322 const int namelist_len)
325 * Caller must have already printed the KERN_* log level for us.
326 * Also the caller is responsible for adding the newline.
329 for (i = 0; i < namelist_len; ++i) {
330 if (value == namelist[i].value) {
331 printk("%s", namelist[i].name);
335 printk("unknown value 0x%08x", value);
337 #define nouveau_print_enum_names(val, namelist) \
338 nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
341 nouveau_graph_chid_from_grctx(struct drm_device *dev)
343 struct drm_nouveau_private *dev_priv = dev->dev_private;
347 if (dev_priv->card_type < NV_40)
348 return dev_priv->engine.fifo.channels;
350 if (dev_priv->card_type < NV_50) {
351 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4;
353 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
354 struct nouveau_channel *chan = dev_priv->fifos[i];
356 if (!chan || !chan->ramin_grctx)
359 if (inst == chan->ramin_grctx->instance)
363 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12;
365 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
366 struct nouveau_channel *chan = dev_priv->fifos[i];
368 if (!chan || !chan->ramin)
371 if (inst == chan->ramin->instance)
381 nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
383 struct drm_nouveau_private *dev_priv = dev->dev_private;
384 struct nouveau_engine *engine = &dev_priv->engine;
387 if (dev_priv->card_type < NV_10)
388 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
390 if (dev_priv->card_type < NV_40)
391 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
393 channel = nouveau_graph_chid_from_grctx(dev);
395 if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) {
396 NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel);
400 *channel_ret = channel;
404 struct nouveau_pgraph_trap {
407 int subc, mthd, size;
408 uint32_t data, data2;
409 uint32_t nsource, nstatus;
413 nouveau_graph_trap_info(struct drm_device *dev,
414 struct nouveau_pgraph_trap *trap)
416 struct drm_nouveau_private *dev_priv = dev->dev_private;
419 trap->nsource = trap->nstatus = 0;
420 if (dev_priv->card_type < NV_50) {
421 trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
422 trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
425 if (nouveau_graph_trapped_channel(dev, &trap->channel))
427 address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
429 trap->mthd = address & 0x1FFC;
430 trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
431 if (dev_priv->card_type < NV_10) {
432 trap->subc = (address >> 13) & 0x7;
434 trap->subc = (address >> 16) & 0x7;
435 trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH);
438 if (dev_priv->card_type < NV_10)
439 trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF;
440 else if (dev_priv->card_type < NV_40)
441 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF;
442 else if (dev_priv->card_type < NV_50)
443 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF;
445 trap->class = nv_rd32(dev, 0x400814);
449 nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
450 struct nouveau_pgraph_trap *trap)
452 struct drm_nouveau_private *dev_priv = dev->dev_private;
453 uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
455 if (dev_priv->card_type < NV_50) {
456 NV_INFO(dev, "%s - nSource:", id);
457 nouveau_print_bitfield_names(nsource, nsource_names);
458 printk(", nStatus:");
459 if (dev_priv->card_type < NV_10)
460 nouveau_print_bitfield_names(nstatus, nstatus_names);
462 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
466 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
467 "Data 0x%08x:0x%08x\n",
468 id, trap->channel, trap->subc,
469 trap->class, trap->mthd,
470 trap->data2, trap->data);
474 nouveau_pgraph_intr_swmthd(struct drm_device *dev,
475 struct nouveau_pgraph_trap *trap)
477 struct drm_nouveau_private *dev_priv = dev->dev_private;
479 if (trap->channel < 0 ||
480 trap->channel >= dev_priv->engine.fifo.channels ||
481 !dev_priv->fifos[trap->channel])
484 return nouveau_call_method(dev_priv->fifos[trap->channel],
485 trap->class, trap->mthd, trap->data);
489 nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
491 struct nouveau_pgraph_trap trap;
494 nouveau_graph_trap_info(dev, &trap);
496 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
497 if (nouveau_pgraph_intr_swmthd(dev, &trap))
504 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
507 static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20);
509 static int nouveau_ratelimit(void)
511 return __ratelimit(&nouveau_ratelimit_state);
516 nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
518 struct nouveau_pgraph_trap trap;
521 nouveau_graph_trap_info(dev, &trap);
522 trap.nsource = nsource;
524 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
525 if (nouveau_pgraph_intr_swmthd(dev, &trap))
527 } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
528 uint32_t v = nv_rd32(dev, 0x402000);
529 nv_wr32(dev, 0x402000, v);
531 /* dump the error anyway for now: it's useful for
532 Gallium development */
538 if (unhandled && nouveau_ratelimit())
539 nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
543 nouveau_pgraph_intr_context_switch(struct drm_device *dev)
545 struct drm_nouveau_private *dev_priv = dev->dev_private;
546 struct nouveau_engine *engine = &dev_priv->engine;
549 chid = engine->fifo.channel_id(dev);
550 NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid);
552 switch (dev_priv->card_type) {
554 nv04_graph_context_switch(dev);
557 nv10_graph_context_switch(dev);
560 NV_ERROR(dev, "Context switch not implemented\n");
566 nouveau_pgraph_irq_handler(struct drm_device *dev)
570 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
571 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
573 if (status & NV_PGRAPH_INTR_NOTIFY) {
574 nouveau_pgraph_intr_notify(dev, nsource);
576 status &= ~NV_PGRAPH_INTR_NOTIFY;
577 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
580 if (status & NV_PGRAPH_INTR_ERROR) {
581 nouveau_pgraph_intr_error(dev, nsource);
583 status &= ~NV_PGRAPH_INTR_ERROR;
584 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
587 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
588 nouveau_pgraph_intr_context_switch(dev);
590 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
591 nv_wr32(dev, NV03_PGRAPH_INTR,
592 NV_PGRAPH_INTR_CONTEXT_SWITCH);
596 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
597 nv_wr32(dev, NV03_PGRAPH_INTR, status);
600 if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
601 nv_wr32(dev, NV04_PGRAPH_FIFO, 1);
604 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
608 nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
610 struct drm_nouveau_private *dev_priv = dev->dev_private;
613 uint32_t idx = nv_rd32(dev, 0x100c90);
614 if (idx & 0x80000000) {
617 for (i = 0; i < 6; i++) {
618 nv_wr32(dev, 0x100c90, idx | i << 24);
619 trap[i] = nv_rd32(dev, 0x100c94);
621 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
622 struct nouveau_channel *chan = dev_priv->fifos[ch];
624 if (!chan || !chan->ramin)
627 if (trap[1] == chan->ramin->instance >> 12)
630 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
631 name, (trap[5]&0x100?"read":"write"),
632 trap[5]&0xff, trap[4]&0xffff,
633 trap[3]&0xffff, trap[0], trap[2], ch);
635 nv_wr32(dev, 0x100c90, idx | 0x80000000);
636 } else if (display) {
637 NV_INFO(dev, "%s - no VM fault?\n", name);
641 static struct nouveau_enum_names nv50_mp_exec_error_names[] =
643 { 3, "STACK_UNDERFLOW" },
644 { 4, "QUADON_ACTIVE" },
646 { 0x10, "INVALID_OPCODE" },
647 { 0x40, "BREAKPOINT" },
651 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
653 struct drm_nouveau_private *dev_priv = dev->dev_private;
654 uint32_t units = nv_rd32(dev, 0x1540);
655 uint32_t addr, mp10, status, pc, oplow, ophigh;
658 for (i = 0; i < 4; i++) {
659 if (!(units & 1 << (i+24)))
661 if (dev_priv->chipset < 0xa0)
662 addr = 0x408200 + (tpid << 12) + (i << 7);
664 addr = 0x408100 + (tpid << 11) + (i << 7);
665 mp10 = nv_rd32(dev, addr + 0x10);
666 status = nv_rd32(dev, addr + 0x14);
670 nv_rd32(dev, addr + 0x20);
671 pc = nv_rd32(dev, addr + 0x24);
672 oplow = nv_rd32(dev, addr + 0x70);
673 ophigh= nv_rd32(dev, addr + 0x74);
674 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
675 "TP %d MP %d: ", tpid, i);
676 nouveau_print_enum_names(status,
677 nv50_mp_exec_error_names);
678 printk(" at %06x warp %d, opcode %08x %08x\n",
679 pc&0xffffff, pc >> 24,
682 nv_wr32(dev, addr + 0x10, mp10);
683 nv_wr32(dev, addr + 0x14, 0);
687 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
688 "No MPs claiming errors?\n", tpid);
692 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
693 uint32_t ustatus_new, int display, const char *name)
695 struct drm_nouveau_private *dev_priv = dev->dev_private;
697 uint32_t units = nv_rd32(dev, 0x1540);
699 uint32_t ustatus_addr, ustatus;
700 for (i = 0; i < 16; i++) {
701 if (!(units & (1 << i)))
703 if (dev_priv->chipset < 0xa0)
704 ustatus_addr = ustatus_old + (i << 12);
706 ustatus_addr = ustatus_new + (i << 11);
707 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
712 case 6: /* texture error... unknown for now */
713 nv50_pfb_vm_trap(dev, display, name);
715 NV_ERROR(dev, "magic set %d:\n", i);
716 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
717 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
721 case 7: /* MP error */
722 if (ustatus & 0x00010000) {
723 nv50_pgraph_mp_trap(dev, i, display);
724 ustatus &= ~0x00010000;
727 case 8: /* TPDMA error */
729 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
730 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
731 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
732 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
733 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
734 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
735 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
736 nv50_pfb_vm_trap(dev, display, name);
737 /* 2d engine destination */
738 if (ustatus & 0x00000010) {
740 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
742 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
743 i, e0c, e18, e1c, e20, e24);
745 ustatus &= ~0x00000010;
748 if (ustatus & 0x00000040) {
750 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
752 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
753 i, e0c, e18, e1c, e20, e24);
755 ustatus &= ~0x00000040;
757 /* CUDA memory: l[], g[] or stack. */
758 if (ustatus & 0x00000080) {
760 if (e18 & 0x80000000) {
761 /* g[] read fault? */
762 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
763 i, e14, e10 | ((e18 >> 24) & 0x1f));
765 } else if (e18 & 0xc) {
766 /* g[] write fault? */
767 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
768 i, e14, e10 | ((e18 >> 7) & 0x1f));
771 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
774 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
775 i, e0c, e18, e1c, e20, e24);
777 ustatus &= ~0x00000080;
784 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
786 nv_wr32(dev, ustatus_addr, 0xc0000000);
790 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
794 nv50_pgraph_trap_handler(struct drm_device *dev)
796 struct nouveau_pgraph_trap trap;
797 uint32_t status = nv_rd32(dev, 0x400108);
799 int display = nouveau_ratelimit();
802 if (!status && display) {
803 nouveau_graph_trap_info(dev, &trap);
804 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
805 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
808 /* DISPATCH: Relays commands to other units and handles NOTIFY,
809 * COND, QUERY. If you get a trap from it, the command is still stuck
810 * in DISPATCH and you need to do something about it. */
811 if (status & 0x001) {
812 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
813 if (!ustatus && display) {
814 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
817 /* Known to be triggered by screwed up NOTIFY and COND... */
818 if (ustatus & 0x00000001) {
819 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
820 nv_wr32(dev, 0x400500, 0);
821 if (nv_rd32(dev, 0x400808) & 0x80000000) {
823 if (nouveau_graph_trapped_channel(dev, &trap.channel))
825 trap.class = nv_rd32(dev, 0x400814);
826 trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
827 trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
828 trap.data = nv_rd32(dev, 0x40080c);
829 trap.data2 = nv_rd32(dev, 0x400810);
830 nouveau_graph_dump_trap_info(dev,
831 "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
832 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
833 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
835 nv_wr32(dev, 0x400808, 0);
836 } else if (display) {
837 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
839 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
840 nv_wr32(dev, 0x400848, 0);
841 ustatus &= ~0x00000001;
843 if (ustatus & 0x00000002) {
844 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
845 nv_wr32(dev, 0x400500, 0);
846 if (nv_rd32(dev, 0x40084c) & 0x80000000) {
848 if (nouveau_graph_trapped_channel(dev, &trap.channel))
850 trap.class = nv_rd32(dev, 0x400814);
851 trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
852 trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
853 trap.data = nv_rd32(dev, 0x40085c);
855 nouveau_graph_dump_trap_info(dev,
856 "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
857 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
859 nv_wr32(dev, 0x40084c, 0);
860 } else if (display) {
861 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
863 ustatus &= ~0x00000002;
865 if (ustatus && display)
866 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
867 nv_wr32(dev, 0x400804, 0xc0000000);
868 nv_wr32(dev, 0x400108, 0x001);
872 /* TRAPs other than dispatch use the "normal" trap regs. */
873 if (status && display) {
874 nouveau_graph_trap_info(dev, &trap);
875 nouveau_graph_dump_trap_info(dev,
876 "PGRAPH_TRAP", &trap);
879 /* M2MF: Memory to memory copy engine. */
880 if (status & 0x002) {
881 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
882 if (!ustatus && display) {
883 NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
885 if (ustatus & 0x00000001) {
886 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
887 ustatus &= ~0x00000001;
889 if (ustatus & 0x00000002) {
890 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
891 ustatus &= ~0x00000002;
893 if (ustatus & 0x00000004) {
894 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
895 ustatus &= ~0x00000004;
897 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
898 nv_rd32(dev, 0x406804),
899 nv_rd32(dev, 0x406808),
900 nv_rd32(dev, 0x40680c),
901 nv_rd32(dev, 0x406810));
902 if (ustatus && display)
903 NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
904 /* No sane way found yet -- just reset the bugger. */
905 nv_wr32(dev, 0x400040, 2);
906 nv_wr32(dev, 0x400040, 0);
907 nv_wr32(dev, 0x406800, 0xc0000000);
908 nv_wr32(dev, 0x400108, 0x002);
912 /* VFETCH: Fetches data from vertex buffers. */
913 if (status & 0x004) {
914 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
915 if (!ustatus && display) {
916 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
918 if (ustatus & 0x00000001) {
919 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
920 NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
921 nv_rd32(dev, 0x400c00),
922 nv_rd32(dev, 0x400c08),
923 nv_rd32(dev, 0x400c0c),
924 nv_rd32(dev, 0x400c10));
925 ustatus &= ~0x00000001;
927 if (ustatus && display)
928 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
929 nv_wr32(dev, 0x400c04, 0xc0000000);
930 nv_wr32(dev, 0x400108, 0x004);
934 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
935 if (status & 0x008) {
936 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
937 if (!ustatus && display) {
938 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
940 if (ustatus & 0x00000001) {
941 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
942 NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
943 nv_rd32(dev, 0x401804),
944 nv_rd32(dev, 0x401808),
945 nv_rd32(dev, 0x40180c),
946 nv_rd32(dev, 0x401810));
947 ustatus &= ~0x00000001;
949 if (ustatus && display)
950 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
951 /* No sane way found yet -- just reset the bugger. */
952 nv_wr32(dev, 0x400040, 0x80);
953 nv_wr32(dev, 0x400040, 0);
954 nv_wr32(dev, 0x401800, 0xc0000000);
955 nv_wr32(dev, 0x400108, 0x008);
959 /* CCACHE: Handles code and c[] caches and fills them. */
960 if (status & 0x010) {
961 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
962 if (!ustatus && display) {
963 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
965 if (ustatus & 0x00000001) {
966 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
967 NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
968 nv_rd32(dev, 0x405800),
969 nv_rd32(dev, 0x405804),
970 nv_rd32(dev, 0x405808),
971 nv_rd32(dev, 0x40580c),
972 nv_rd32(dev, 0x405810),
973 nv_rd32(dev, 0x405814),
974 nv_rd32(dev, 0x40581c));
975 ustatus &= ~0x00000001;
977 if (ustatus && display)
978 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
979 nv_wr32(dev, 0x405018, 0xc0000000);
980 nv_wr32(dev, 0x400108, 0x010);
984 /* Unknown, not seen yet... 0x402000 is the only trap status reg
985 * remaining, so try to handle it anyway. Perhaps related to that
986 * unknown DMA slot on tesla? */
988 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
989 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
991 NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
992 nv_wr32(dev, 0x402000, 0xc0000000);
993 /* no status modifiction on purpose */
996 /* TEXTURE: CUDA texturing units */
997 if (status & 0x040) {
998 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
999 "PGRAPH_TRAP_TEXTURE");
1000 nv_wr32(dev, 0x400108, 0x040);
1004 /* MP: CUDA execution engines. */
1005 if (status & 0x080) {
1006 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
1008 nv_wr32(dev, 0x400108, 0x080);
1012 /* TPDMA: Handles TP-initiated uncached memory accesses:
1013 * l[], g[], stack, 2d surfaces, render targets. */
1014 if (status & 0x100) {
1015 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
1016 "PGRAPH_TRAP_TPDMA");
1017 nv_wr32(dev, 0x400108, 0x100);
1023 NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1025 nv_wr32(dev, 0x400108, status);
1029 /* There must be a *lot* of these. Will take some time to gather them up. */
1030 static struct nouveau_enum_names nv50_data_error_names[] =
1032 { 4, "INVALID_VALUE" },
1033 { 5, "INVALID_ENUM" },
1034 { 8, "INVALID_OBJECT" },
1035 { 0xc, "INVALID_BITFIELD" },
1036 { 0x28, "MP_NO_REG_SPACE" },
1037 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1041 nv50_pgraph_irq_handler(struct drm_device *dev)
1043 struct nouveau_pgraph_trap trap;
1047 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1048 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
1049 if (status & 0x00000001) {
1050 nouveau_graph_trap_info(dev, &trap);
1051 if (nouveau_ratelimit())
1052 nouveau_graph_dump_trap_info(dev,
1053 "PGRAPH_NOTIFY", &trap);
1054 status &= ~0x00000001;
1055 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
1058 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
1059 * when you write 0x200 to 0x50c0 method 0x31c. */
1060 if (status & 0x00000002) {
1061 nouveau_graph_trap_info(dev, &trap);
1062 if (nouveau_ratelimit())
1063 nouveau_graph_dump_trap_info(dev,
1064 "PGRAPH_COMPUTE_QUERY", &trap);
1065 status &= ~0x00000002;
1066 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
1069 /* Unknown, never seen: 0x4 */
1071 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1072 if (status & 0x00000010) {
1073 nouveau_graph_trap_info(dev, &trap);
1074 if (nouveau_pgraph_intr_swmthd(dev, &trap))
1076 if (unhandled && nouveau_ratelimit())
1077 nouveau_graph_dump_trap_info(dev,
1078 "PGRAPH_ILLEGAL_MTHD", &trap);
1079 status &= ~0x00000010;
1080 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
1083 /* ILLEGAL_CLASS: You used a wrong class. */
1084 if (status & 0x00000020) {
1085 nouveau_graph_trap_info(dev, &trap);
1086 if (nouveau_ratelimit())
1087 nouveau_graph_dump_trap_info(dev,
1088 "PGRAPH_ILLEGAL_CLASS", &trap);
1089 status &= ~0x00000020;
1090 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
1093 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1094 if (status & 0x00000040) {
1095 nouveau_graph_trap_info(dev, &trap);
1096 if (nouveau_ratelimit())
1097 nouveau_graph_dump_trap_info(dev,
1098 "PGRAPH_DOUBLE_NOTIFY", &trap);
1099 status &= ~0x00000040;
1100 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
1103 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
1104 if (status & 0x00001000) {
1105 nv_wr32(dev, 0x400500, 0x00000000);
1106 nv_wr32(dev, NV03_PGRAPH_INTR,
1107 NV_PGRAPH_INTR_CONTEXT_SWITCH);
1108 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
1109 NV40_PGRAPH_INTR_EN) &
1110 ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
1111 nv_wr32(dev, 0x400500, 0x00010001);
1113 nv50_graph_context_switch(dev);
1115 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1118 /* BUFFER_NOTIFY: Your m2mf transfer finished */
1119 if (status & 0x00010000) {
1120 nouveau_graph_trap_info(dev, &trap);
1121 if (nouveau_ratelimit())
1122 nouveau_graph_dump_trap_info(dev,
1123 "PGRAPH_BUFFER_NOTIFY", &trap);
1124 status &= ~0x00010000;
1125 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
1128 /* DATA_ERROR: Invalid value for this method, or invalid
1129 * state in current PGRAPH context for this operation */
1130 if (status & 0x00100000) {
1131 nouveau_graph_trap_info(dev, &trap);
1132 if (nouveau_ratelimit()) {
1133 nouveau_graph_dump_trap_info(dev,
1134 "PGRAPH_DATA_ERROR", &trap);
1135 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
1136 nouveau_print_enum_names(nv_rd32(dev, 0x400110),
1137 nv50_data_error_names);
1140 status &= ~0x00100000;
1141 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
1144 /* TRAP: Something bad happened in the middle of command
1145 * execution. Has a billion types, subtypes, and even
1147 if (status & 0x00200000) {
1148 nv50_pgraph_trap_handler(dev);
1149 status &= ~0x00200000;
1150 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
1153 /* Unknown, never seen: 0x00400000 */
1155 /* SINGLE_STEP: Happens on every method if you turned on
1156 * single stepping in 40008c */
1157 if (status & 0x01000000) {
1158 nouveau_graph_trap_info(dev, &trap);
1159 if (nouveau_ratelimit())
1160 nouveau_graph_dump_trap_info(dev,
1161 "PGRAPH_SINGLE_STEP", &trap);
1162 status &= ~0x01000000;
1163 nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
1166 /* 0x02000000 happens when you pause a ctxprog...
1167 * but the only way this can happen that I know is by
1168 * poking the relevant MMIO register, and we don't
1172 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
1174 nv_wr32(dev, NV03_PGRAPH_INTR, status);
1178 const int isb = (1 << 16) | (1 << 0);
1180 if ((nv_rd32(dev, 0x400500) & isb) != isb)
1181 nv_wr32(dev, 0x400500,
1182 nv_rd32(dev, 0x400500) | isb);
1186 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
1187 if (nv_rd32(dev, 0x400824) & (1 << 31))
1188 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1192 nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
1195 nv_wr32(dev, NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
1198 nv_wr32(dev, NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
1202 nouveau_irq_handler(DRM_IRQ_ARGS)
1204 struct drm_device *dev = (struct drm_device *)arg;
1205 struct drm_nouveau_private *dev_priv = dev->dev_private;
1207 unsigned long flags;
1209 status = nv_rd32(dev, NV03_PMC_INTR_0);
1213 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
1215 if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
1216 nouveau_fifo_irq_handler(dev);
1217 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
1220 if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
1221 if (dev_priv->card_type >= NV_50)
1222 nv50_pgraph_irq_handler(dev);
1224 nouveau_pgraph_irq_handler(dev);
1226 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
1229 if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
1230 nouveau_crtc_irq_handler(dev, (status>>24)&3);
1231 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
1234 if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1235 NV_PMC_INTR_0_NV50_I2C_PENDING)) {
1236 nv50_display_irq_handler(dev);
1237 status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1238 NV_PMC_INTR_0_NV50_I2C_PENDING);
1242 NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);
1244 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);