SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_sdvo_regs.h"
  37
  38 #undef SDVO_DEBUG
  39
  40 struct intel_sdvo_priv {
  41         struct intel_i2c_chan *i2c_bus;
  42         int slaveaddr;
  43
  44         /* Register for the SDVO device: SDVOB or SDVOC */
  45         int output_device;
  46
  47         /* Active outputs controlled by this SDVO output */
  48         uint16_t controlled_output;
  49
  50         /*
  51          * Capabilities of the SDVO device returned by
  52          * i830_sdvo_get_capabilities()
  53          */
  54         struct intel_sdvo_caps caps;
  55
  56         /* Pixel clock limitations reported by the SDVO device, in kHz */
  57         int pixel_clock_min, pixel_clock_max;
  58
  59         /**
  60          * This is set if we're going to treat the device as TV-out.
  61          *
  62          * While we have these nice friendly flags for output types that ought
  63          * to decide this for us, the S-Video output on our HDMI+S-Video card
  64          * shows up as RGB1 (VGA).
  65          */
  66         bool is_tv;
  67
  68         /**
  69          * This is set if we treat the device as HDMI, instead of DVI.
  70          */
  71         bool is_hdmi;
  72
  73         /**
  74          * Returned SDTV resolutions allowed for the current format, if the
  75          * device reported it.
  76          */
  77         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  78
  79         /**
  80          * Current selected TV format.
  81          *
  82          * This is stored in the same structure that's passed to the device, for
  83          * convenience.
  84          */
  85         struct intel_sdvo_tv_format tv_format;
  86
  87         /*
  88          * supported encoding mode, used to determine whether HDMI is
  89          * supported
  90          */
  91         struct intel_sdvo_encode encode;
  92
  93         /* DDC bus used by this SDVO output */
  94         uint8_t ddc_bus;
  95
  96         int save_sdvo_mult;
  97         u16 save_active_outputs;
  98         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
  99         struct intel_sdvo_dtd save_output_dtd[16];
 100         u32 save_SDVOX;
 101 };
 102
 103 /**
 104  * Writes the SDVOB or SDVOC with the given value, but always writes both
 105  * SDVOB and SDVOC to work around apparent hardware issues (according to
 106  * comments in the BIOS).
 107  */
 108 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
 109 {
 110         struct drm_device *dev = intel_output->base.dev;
 111         struct drm_i915_private *dev_priv = dev->dev_private;
 112         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
 113         u32 bval = val, cval = val;
 114         int i;
 115
 116         if (sdvo_priv->output_device == SDVOB) {
 117                 cval = I915_READ(SDVOC);
 118         } else {
 119                 bval = I915_READ(SDVOB);
 120         }
 121         /*
 122          * Write the registers twice for luck. Sometimes,
 123          * writing them only once doesn't appear to 'stick'.
 124          * The BIOS does this too. Yay, magic
 125          */
 126         for (i = 0; i < 2; i++)
 127         {
 128                 I915_WRITE(SDVOB, bval);
 129                 I915_READ(SDVOB);
 130                 I915_WRITE(SDVOC, cval);
 131                 I915_READ(SDVOC);
 132         }
 133 }
 134
 135 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 136                                  u8 *ch)
 137 {
 138         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 139         u8 out_buf[2];
 140         u8 buf[2];
 141         int ret;
 142
 143         struct i2c_msg msgs[] = {
 144                 {
 145                         .addr = sdvo_priv->i2c_bus->slave_addr,
 146                         .flags = 0,
 147                         .len = 1,
 148                         .buf = out_buf,
 149                 },
 150                 {
 151                         .addr = sdvo_priv->i2c_bus->slave_addr,
 152                         .flags = I2C_M_RD,
 153                         .len = 1,
 154                         .buf = buf,
 155                 }
 156         };
 157
 158         out_buf[0] = addr;
 159         out_buf[1] = 0;
 160
 161         if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
 162         {
 163                 *ch = buf[0];
 164                 return true;
 165         }
 166
 167         DRM_DEBUG("i2c transfer returned %d\n", ret);
 168         return false;
 169 }
 170
 171 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
 172                                   u8 ch)
 173 {
 174         u8 out_buf[2];
 175         struct i2c_msg msgs[] = {
 176                 {
 177                         .addr = intel_output->i2c_bus->slave_addr,
 178                         .flags = 0,
 179                         .len = 2,
 180                         .buf = out_buf,
 181                 }
 182         };
 183
 184         out_buf[0] = addr;
 185         out_buf[1] = ch;
 186
 187         if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
 188         {
 189                 return true;
 190         }
 191         return false;
 192 }
 193
 194 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 195 /** Mapping of command numbers to names, for debug output */
 196 static const struct _sdvo_cmd_name {
 197         u8 cmd;
 198         char *name;
 199 } sdvo_cmd_names[] = {
 200     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 201     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 202     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 203     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 204     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 205     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 206     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 207     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 208     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 209     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 210     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 211     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 212     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 213     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 214     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 215     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 216     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 217     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 218     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 219     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 220     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 221     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 222     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 223     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 224     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 243     /* HDMI op code */
 244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 247     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 257     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 264 };
 265
 266 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
 267 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
 268
 269 #ifdef SDVO_DEBUG
 270 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 271                                    void *args, int args_len)
 272 {
 273         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 274         int i;
 275
 276         printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
 277         for (i = 0; i < args_len; i++)
 278                 printk(KERN_DEBUG "%02X ", ((u8 *)args)[i]);
 279         for (; i < 8; i++)
 280                 printk(KERN_DEBUG "   ");
 281         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 282                 if (cmd == sdvo_cmd_names[i].cmd) {
 283                         printk(KERN_DEBUG "(%s)", sdvo_cmd_names[i].name);
 284                         break;
 285                 }
 286         }
 287         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 288                 printk(KERN_DEBUG "(%02X)", cmd);
 289         printk(KERN_DEBUG "\n");
 290 }
 291 #else
 292 #define intel_sdvo_debug_write(o, c, a, l)
 293 #endif
 294
 295 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
 296                                  void *args, int args_len)
 297 {
 298         int i;
 299
 300         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
 301
 302         for (i = 0; i < args_len; i++) {
 303                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
 304                                       ((u8*)args)[i]);
 305         }
 306
 307         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
 308 }
 309
 310 #ifdef SDVO_DEBUG
 311 static const char *cmd_status_names[] = {
 312         "Power on",
 313         "Success",
 314         "Not supported",
 315         "Invalid arg",
 316         "Pending",
 317         "Target not specified",
 318         "Scaling not supported"
 319 };
 320
 321 static void intel_sdvo_debug_response(struct intel_output *intel_output,
 322                                       void *response, int response_len,
 323                                       u8 status)
 324 {
 325         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 326         int i;
 327
 328         printk(KERN_DEBUG "%s: R: ", SDVO_NAME(sdvo_priv));
 329         for (i = 0; i < response_len; i++)
 330                 printk(KERN_DEBUG "%02X ", ((u8 *)response)[i]);
 331         for (; i < 8; i++)
 332                 printk(KERN_DEBUG "   ");
 333         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 334                 printk(KERN_DEBUG "(%s)", cmd_status_names[status]);
 335         else
 336                 printk(KERN_DEBUG "(??? %d)", status);
 337         printk(KERN_DEBUG "\n");
 338 }
 339 #else
 340 #define intel_sdvo_debug_response(o, r, l, s)
 341 #endif
 342
 343 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
 344                                    void *response, int response_len)
 345 {
 346         int i;
 347         u8 status;
 348         u8 retry = 50;
 349
 350         while (retry--) {
 351                 /* Read the command response */
 352                 for (i = 0; i < response_len; i++) {
 353                         intel_sdvo_read_byte(intel_output,
 354                                              SDVO_I2C_RETURN_0 + i,
 355                                              &((u8 *)response)[i]);
 356                 }
 357
 358                 /* read the return status */
 359                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
 360                                      &status);
 361
 362                 intel_sdvo_debug_response(intel_output, response, response_len,
 363                                           status);
 364                 if (status != SDVO_CMD_STATUS_PENDING)
 365                         return status;
 366
 367                 mdelay(50);
 368         }
 369
 370         return status;
 371 }
 372
 373 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 374 {
 375         if (mode->clock >= 100000)
 376                 return 1;
 377         else if (mode->clock >= 50000)
 378                 return 2;
 379         else
 380                 return 4;
 381 }
 382
 383 /**
 384  * Don't check status code from this as it switches the bus back to the
 385  * SDVO chips which defeats the purpose of doing a bus switch in the first
 386  * place.
 387  */
 388 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
 389                                               u8 target)
 390 {
 391         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
 392 }
 393
 394 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
 395 {
 396         struct intel_sdvo_set_target_input_args targets = {0};
 397         u8 status;
 398
 399         if (target_0 && target_1)
 400                 return SDVO_CMD_STATUS_NOTSUPP;
 401
 402         if (target_1)
 403                 targets.target_1 = 1;
 404
 405         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
 406                              sizeof(targets));
 407
 408         status = intel_sdvo_read_response(intel_output, NULL, 0);
 409
 410         return (status == SDVO_CMD_STATUS_SUCCESS);
 411 }
 412
 413 /**
 414  * Return whether each input is trained.
 415  *
 416  * This function is making an assumption about the layout of the response,
 417  * which should be checked against the docs.
 418  */
 419 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
 420 {
 421         struct intel_sdvo_get_trained_inputs_response response;
 422         u8 status;
 423
 424         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 425         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
 426         if (status != SDVO_CMD_STATUS_SUCCESS)
 427                 return false;
 428
 429         *input_1 = response.input0_trained;
 430         *input_2 = response.input1_trained;
 431         return true;
 432 }
 433
 434 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
 435                                           u16 *outputs)
 436 {
 437         u8 status;
 438
 439         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 440         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
 441
 442         return (status == SDVO_CMD_STATUS_SUCCESS);
 443 }
 444
 445 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
 446                                           u16 outputs)
 447 {
 448         u8 status;
 449
 450         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 451                              sizeof(outputs));
 452         status = intel_sdvo_read_response(intel_output, NULL, 0);
 453         return (status == SDVO_CMD_STATUS_SUCCESS);
 454 }
 455
 456 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
 457                                                int mode)
 458 {
 459         u8 status, state = SDVO_ENCODER_STATE_ON;
 460
 461         switch (mode) {
 462         case DRM_MODE_DPMS_ON:
 463                 state = SDVO_ENCODER_STATE_ON;
 464                 break;
 465         case DRM_MODE_DPMS_STANDBY:
 466                 state = SDVO_ENCODER_STATE_STANDBY;
 467                 break;
 468         case DRM_MODE_DPMS_SUSPEND:
 469                 state = SDVO_ENCODER_STATE_SUSPEND;
 470                 break;
 471         case DRM_MODE_DPMS_OFF:
 472                 state = SDVO_ENCODER_STATE_OFF;
 473                 break;
 474         }
 475
 476         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 477                              sizeof(state));
 478         status = intel_sdvo_read_response(intel_output, NULL, 0);
 479
 480         return (status == SDVO_CMD_STATUS_SUCCESS);
 481 }
 482
 483 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
 484                                                    int *clock_min,
 485                                                    int *clock_max)
 486 {
 487         struct intel_sdvo_pixel_clock_range clocks;
 488         u8 status;
 489
 490         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 491                              NULL, 0);
 492
 493         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
 494
 495         if (status != SDVO_CMD_STATUS_SUCCESS)
 496                 return false;
 497
 498         /* Convert the values from units of 10 kHz to kHz. */
 499         *clock_min = clocks.min * 10;
 500         *clock_max = clocks.max * 10;
 501
 502         return true;
 503 }
 504
 505 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
 506                                          u16 outputs)
 507 {
 508         u8 status;
 509
 510         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 511                              sizeof(outputs));
 512
 513         status = intel_sdvo_read_response(intel_output, NULL, 0);
 514         return (status == SDVO_CMD_STATUS_SUCCESS);
 515 }
 516
 517 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
 518                                   struct intel_sdvo_dtd *dtd)
 519 {
 520         u8 status;
 521
 522         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
 523         status = intel_sdvo_read_response(intel_output, &dtd->part1,
 524                                           sizeof(dtd->part1));
 525         if (status != SDVO_CMD_STATUS_SUCCESS)
 526                 return false;
 527
 528         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
 529         status = intel_sdvo_read_response(intel_output, &dtd->part2,
 530                                           sizeof(dtd->part2));
 531         if (status != SDVO_CMD_STATUS_SUCCESS)
 532                 return false;
 533
 534         return true;
 535 }
 536
 537 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
 538                                          struct intel_sdvo_dtd *dtd)
 539 {
 540         return intel_sdvo_get_timing(intel_output,
 541                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 542 }
 543
 544 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
 545                                          struct intel_sdvo_dtd *dtd)
 546 {
 547         return intel_sdvo_get_timing(intel_output,
 548                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 549 }
 550
 551 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
 552                                   struct intel_sdvo_dtd *dtd)
 553 {
 554         u8 status;
 555
 556         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
 557         status = intel_sdvo_read_response(intel_output, NULL, 0);
 558         if (status != SDVO_CMD_STATUS_SUCCESS)
 559                 return false;
 560
 561         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 562         status = intel_sdvo_read_response(intel_output, NULL, 0);
 563         if (status != SDVO_CMD_STATUS_SUCCESS)
 564                 return false;
 565
 566         return true;
 567 }
 568
 569 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
 570                                          struct intel_sdvo_dtd *dtd)
 571 {
 572         return intel_sdvo_set_timing(intel_output,
 573                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 574 }
 575
 576 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
 577                                          struct intel_sdvo_dtd *dtd)
 578 {
 579         return intel_sdvo_set_timing(intel_output,
 580                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 581 }
 582
 583 static bool
 584 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
 585                                          uint16_t clock,
 586                                          uint16_t width,
 587                                          uint16_t height)
 588 {
 589         struct intel_sdvo_preferred_input_timing_args args;
 590         uint8_t status;
 591
 592         args.clock = clock;
 593         args.width = width;
 594         args.height = height;
 595         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 596                              &args, sizeof(args));
 597         status = intel_sdvo_read_response(output, NULL, 0);
 598         if (status != SDVO_CMD_STATUS_SUCCESS)
 599                 return false;
 600
 601         return true;
 602 }
 603
 604 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
 605                                                   struct intel_sdvo_dtd *dtd)
 606 {
 607         bool status;
 608
 609         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 610                              NULL, 0);
 611
 612         status = intel_sdvo_read_response(output, &dtd->part1,
 613                                           sizeof(dtd->part1));
 614         if (status != SDVO_CMD_STATUS_SUCCESS)
 615                 return false;
 616
 617         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 618                              NULL, 0);
 619
 620         status = intel_sdvo_read_response(output, &dtd->part2,
 621                                           sizeof(dtd->part2));
 622         if (status != SDVO_CMD_STATUS_SUCCESS)
 623                 return false;
 624
 625         return false;
 626 }
 627
 628 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 629 {
 630         u8 response, status;
 631
 632         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 633         status = intel_sdvo_read_response(intel_output, &response, 1);
 634
 635         if (status != SDVO_CMD_STATUS_SUCCESS) {
 636                 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
 637                 return SDVO_CLOCK_RATE_MULT_1X;
 638         } else {
 639                 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
 640         }
 641
 642         return response;
 643 }
 644
 645 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
 646 {
 647         u8 status;
 648
 649         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 650         status = intel_sdvo_read_response(intel_output, NULL, 0);
 651         if (status != SDVO_CMD_STATUS_SUCCESS)
 652                 return false;
 653
 654         return true;
 655 }
 656
 657 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 658                                          struct drm_display_mode *mode)
 659 {
 660         uint16_t width, height;
 661         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 662         uint16_t h_sync_offset, v_sync_offset;
 663
 664         width = mode->crtc_hdisplay;
 665         height = mode->crtc_vdisplay;
 666
 667         /* do some mode translations */
 668         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 669         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 670
 671         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 672         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 673
 674         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 675         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 676
 677         dtd->part1.clock = mode->clock / 10;
 678         dtd->part1.h_active = width & 0xff;
 679         dtd->part1.h_blank = h_blank_len & 0xff;
 680         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 681                 ((h_blank_len >> 8) & 0xf);
 682         dtd->part1.v_active = height & 0xff;
 683         dtd->part1.v_blank = v_blank_len & 0xff;
 684         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 685                 ((v_blank_len >> 8) & 0xf);
 686
 687         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 688         dtd->part2.h_sync_width = h_sync_len & 0xff;
 689         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 690                 (v_sync_len & 0xf);
 691         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 692                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 693                 ((v_sync_len & 0x30) >> 4);
 694
 695         dtd->part2.dtd_flags = 0x18;
 696         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 697                 dtd->part2.dtd_flags |= 0x2;
 698         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 699                 dtd->part2.dtd_flags |= 0x4;
 700
 701         dtd->part2.sdvo_flags = 0;
 702         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 703         dtd->part2.reserved = 0;
 704 }
 705
 706 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 707                                          struct intel_sdvo_dtd *dtd)
 708 {
 709         mode->hdisplay = dtd->part1.h_active;
 710         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 711         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 712         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 713         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 714         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 715         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 716         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 717
 718         mode->vdisplay = dtd->part1.v_active;
 719         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 720         mode->vsync_start = mode->vdisplay;
 721         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 722         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 723         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 724         mode->vsync_end = mode->vsync_start +
 725                 (dtd->part2.v_sync_off_width & 0xf);
 726         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 727         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 728         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 729
 730         mode->clock = dtd->part1.clock * 10;
 731
 732         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 733         if (dtd->part2.dtd_flags & 0x2)
 734                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 735         if (dtd->part2.dtd_flags & 0x4)
 736                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 737 }
 738
 739 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
 740                                        struct intel_sdvo_encode *encode)
 741 {
 742         uint8_t status;
 743
 744         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 745         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
 746         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 747                 memset(encode, 0, sizeof(*encode));
 748                 return false;
 749         }
 750
 751         return true;
 752 }
 753
 754 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
 755 {
 756         uint8_t status;
 757
 758         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
 759         status = intel_sdvo_read_response(output, NULL, 0);
 760
 761         return (status == SDVO_CMD_STATUS_SUCCESS);
 762 }
 763
 764 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
 765                                        uint8_t mode)
 766 {
 767         uint8_t status;
 768
 769         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 770         status = intel_sdvo_read_response(output, NULL, 0);
 771
 772         return (status == SDVO_CMD_STATUS_SUCCESS);
 773 }
 774
 775 #if 0
 776 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
 777 {
 778         int i, j;
 779         uint8_t set_buf_index[2];
 780         uint8_t av_split;
 781         uint8_t buf_size;
 782         uint8_t buf[48];
 783         uint8_t *pos;
 784
 785         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 786         intel_sdvo_read_response(output, &av_split, 1);
 787
 788         for (i = 0; i <= av_split; i++) {
 789                 set_buf_index[0] = i; set_buf_index[1] = 0;
 790                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
 791                                      set_buf_index, 2);
 792                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 793                 intel_sdvo_read_response(output, &buf_size, 1);
 794
 795                 pos = buf;
 796                 for (j = 0; j <= buf_size; j += 8) {
 797                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
 798                                              NULL, 0);
 799                         intel_sdvo_read_response(output, pos, 8);
 800                         pos += 8;
 801                 }
 802         }
 803 }
 804 #endif
 805
 806 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
 807                                 uint8_t *data, int8_t size, uint8_t tx_rate)
 808 {
 809     uint8_t set_buf_index[2];
 810
 811     set_buf_index[0] = index;
 812     set_buf_index[1] = 0;
 813
 814     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
 815
 816     for (; size > 0; size -= 8) {
 817         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
 818         data += 8;
 819     }
 820
 821     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 822 }
 823
 824 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 825 {
 826         uint8_t csum = 0;
 827         int i;
 828
 829         for (i = 0; i < size; i++)
 830                 csum += data[i];
 831
 832         return 0x100 - csum;
 833 }
 834
 835 #define DIP_TYPE_AVI    0x82
 836 #define DIP_VERSION_AVI 0x2
 837 #define DIP_LEN_AVI     13
 838
 839 struct dip_infoframe {
 840         uint8_t type;
 841         uint8_t version;
 842         uint8_t len;
 843         uint8_t checksum;
 844         union {
 845                 struct {
 846                         /* Packet Byte #1 */
 847                         uint8_t S:2;
 848                         uint8_t B:2;
 849                         uint8_t A:1;
 850                         uint8_t Y:2;
 851                         uint8_t rsvd1:1;
 852                         /* Packet Byte #2 */
 853                         uint8_t R:4;
 854                         uint8_t M:2;
 855                         uint8_t C:2;
 856                         /* Packet Byte #3 */
 857                         uint8_t SC:2;
 858                         uint8_t Q:2;
 859                         uint8_t EC:3;
 860                         uint8_t ITC:1;
 861                         /* Packet Byte #4 */
 862                         uint8_t VIC:7;
 863                         uint8_t rsvd2:1;
 864                         /* Packet Byte #5 */
 865                         uint8_t PR:4;
 866                         uint8_t rsvd3:4;
 867                         /* Packet Byte #6~13 */
 868                         uint16_t top_bar_end;
 869                         uint16_t bottom_bar_start;
 870                         uint16_t left_bar_end;
 871                         uint16_t right_bar_start;
 872                 } avi;
 873                 struct {
 874                         /* Packet Byte #1 */
 875                         uint8_t channel_count:3;
 876                         uint8_t rsvd1:1;
 877                         uint8_t coding_type:4;
 878                         /* Packet Byte #2 */
 879                         uint8_t sample_size:2; /* SS0, SS1 */
 880                         uint8_t sample_frequency:3;
 881                         uint8_t rsvd2:3;
 882                         /* Packet Byte #3 */
 883                         uint8_t coding_type_private:5;
 884                         uint8_t rsvd3:3;
 885                         /* Packet Byte #4 */
 886                         uint8_t channel_allocation;
 887                         /* Packet Byte #5 */
 888                         uint8_t rsvd4:3;
 889                         uint8_t level_shift:4;
 890                         uint8_t downmix_inhibit:1;
 891                 } audio;
 892                 uint8_t payload[28];
 893         } __attribute__ ((packed)) u;
 894 } __attribute__((packed));
 895
 896 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 897                                          struct drm_display_mode * mode)
 898 {
 899         struct dip_infoframe avi_if = {
 900                 .type = DIP_TYPE_AVI,
 901                 .version = DIP_VERSION_AVI,
 902                 .len = DIP_LEN_AVI,
 903         };
 904
 905         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
 906                                                     4 + avi_if.len);
 907         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
 908                                 SDVO_HBUF_TX_VSYNC);
 909 }
 910
 911 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
 912                                   struct drm_display_mode *mode,
 913                                   struct drm_display_mode *adjusted_mode)
 914 {
 915         struct intel_output *output = enc_to_intel_output(encoder);
 916         struct intel_sdvo_priv *dev_priv = output->dev_priv;
 917
 918         if (!dev_priv->is_tv) {
 919                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
 920                  * SDVO device will be told of the multiplier during mode_set.
 921                  */
 922                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
 923         } else {
 924                 struct intel_sdvo_dtd output_dtd;
 925                 bool success;
 926
 927                 /* We need to construct preferred input timings based on our
 928                  * output timings.  To do that, we have to set the output
 929                  * timings, even though this isn't really the right place in
 930                  * the sequence to do it. Oh well.
 931                  */
 932
 933
 934                 /* Set output timings */
 935                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 936                 intel_sdvo_set_target_output(output,
 937                                              dev_priv->controlled_output);
 938                 intel_sdvo_set_output_timing(output, &output_dtd);
 939
 940                 /* Set the input timing to the screen. Assume always input 0. */
 941                 intel_sdvo_set_target_input(output, true, false);
 942
 943
 944                 success = intel_sdvo_create_preferred_input_timing(output,
 945                                                                    mode->clock / 10,
 946                                                                    mode->hdisplay,
 947                                                                    mode->vdisplay);
 948                 if (success) {
 949                         struct intel_sdvo_dtd input_dtd;
 950
 951                         intel_sdvo_get_preferred_input_timing(output,
 952                                                              &input_dtd);
 953                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
 954
 955                 } else {
 956                         return false;
 957                 }
 958         }
 959         return true;
 960 }
 961
 962 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 963                                 struct drm_display_mode *mode,
 964                                 struct drm_display_mode *adjusted_mode)
 965 {
 966         struct drm_device *dev = encoder->dev;
 967         struct drm_i915_private *dev_priv = dev->dev_private;
 968         struct drm_crtc *crtc = encoder->crtc;
 969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 970         struct intel_output *output = enc_to_intel_output(encoder);
 971         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 972         u32 sdvox = 0;
 973         int sdvo_pixel_multiply;
 974         struct intel_sdvo_in_out_map in_out;
 975         struct intel_sdvo_dtd input_dtd;
 976         u8 status;
 977
 978         if (!mode)
 979                 return;
 980
 981         /* First, set the input mapping for the first input to our controlled
 982          * output. This is only correct if we're a single-input device, in
 983          * which case the first input is the output from the appropriate SDVO
 984          * channel on the motherboard.  In a two-input device, the first input
 985          * will be SDVOB and the second SDVOC.
 986          */
 987         in_out.in0 = sdvo_priv->controlled_output;
 988         in_out.in1 = 0;
 989
 990         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
 991                              &in_out, sizeof(in_out));
 992         status = intel_sdvo_read_response(output, NULL, 0);
 993
 994         if (sdvo_priv->is_hdmi) {
 995                 intel_sdvo_set_avi_infoframe(output, mode);
 996                 sdvox |= SDVO_AUDIO_ENABLE;
 997         }
 998
 999         intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1000
1001         /* If it's a TV, we already set the output timing in mode_fixup.
1002          * Otherwise, the output timing is equal to the input timing.
1003          */
1004         if (!sdvo_priv->is_tv) {
1005                 /* Set the output timing to the screen */
1006                 intel_sdvo_set_target_output(output,
1007                                              sdvo_priv->controlled_output);
1008                 intel_sdvo_set_output_timing(output, &input_dtd);
1009         }
1010
1011         /* Set the input timing to the screen. Assume always input 0. */
1012         intel_sdvo_set_target_input(output, true, false);
1013
1014         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1015          * provide the device with a timing it can support, if it supports that
1016          * feature.  However, presumably we would need to adjust the CRTC to
1017          * output the preferred timing, and we don't support that currently.
1018          */
1019 #if 0
1020         success = intel_sdvo_create_preferred_input_timing(output, clock,
1021                                                            width, height);
1022         if (success) {
1023                 struct intel_sdvo_dtd *input_dtd;
1024
1025                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1026                 intel_sdvo_set_input_timing(output, &input_dtd);
1027         }
1028 #else
1029         intel_sdvo_set_input_timing(output, &input_dtd);
1030 #endif
1031
1032         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1033         case 1:
1034                 intel_sdvo_set_clock_rate_mult(output,
1035                                                SDVO_CLOCK_RATE_MULT_1X);
1036                 break;
1037         case 2:
1038                 intel_sdvo_set_clock_rate_mult(output,
1039                                                SDVO_CLOCK_RATE_MULT_2X);
1040                 break;
1041         case 4:
1042                 intel_sdvo_set_clock_rate_mult(output,
1043                                                SDVO_CLOCK_RATE_MULT_4X);
1044                 break;
1045         }
1046
1047         /* Set the SDVO control regs. */
1048         if (IS_I965G(dev)) {
1049                 sdvox |= SDVO_BORDER_ENABLE |
1050                         SDVO_VSYNC_ACTIVE_HIGH |
1051                         SDVO_HSYNC_ACTIVE_HIGH;
1052         } else {
1053                 sdvox |= I915_READ(sdvo_priv->output_device);
1054                 switch (sdvo_priv->output_device) {
1055                 case SDVOB:
1056                         sdvox &= SDVOB_PRESERVE_MASK;
1057                         break;
1058                 case SDVOC:
1059                         sdvox &= SDVOC_PRESERVE_MASK;
1060                         break;
1061                 }
1062                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1063         }
1064         if (intel_crtc->pipe == 1)
1065                 sdvox |= SDVO_PIPE_B_SELECT;
1066
1067         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1068         if (IS_I965G(dev)) {
1069                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1070         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1071                 /* done in crtc_mode_set as it lives inside the dpll register */
1072         } else {
1073                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1074         }
1075
1076         intel_sdvo_write_sdvox(output, sdvox);
1077 }
1078
1079 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1080 {
1081         struct drm_device *dev = encoder->dev;
1082         struct drm_i915_private *dev_priv = dev->dev_private;
1083         struct intel_output *intel_output = enc_to_intel_output(encoder);
1084         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1085         u32 temp;
1086
1087         if (mode != DRM_MODE_DPMS_ON) {
1088                 intel_sdvo_set_active_outputs(intel_output, 0);
1089                 if (0)
1090                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1091
1092                 if (mode == DRM_MODE_DPMS_OFF) {
1093                         temp = I915_READ(sdvo_priv->output_device);
1094                         if ((temp & SDVO_ENABLE) != 0) {
1095                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1096                         }
1097                 }
1098         } else {
1099                 bool input1, input2;
1100                 int i;
1101                 u8 status;
1102
1103                 temp = I915_READ(sdvo_priv->output_device);
1104                 if ((temp & SDVO_ENABLE) == 0)
1105                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1106                 for (i = 0; i < 2; i++)
1107                   intel_wait_for_vblank(dev);
1108
1109                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1110                                                        &input2);
1111
1112
1113                 /* Warn if the device reported failure to sync.
1114                  * A lot of SDVO devices fail to notify of sync, but it's
1115                  * a given it the status is a success, we succeeded.
1116                  */
1117                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1118                         DRM_DEBUG("First %s output reported failure to sync\n",
1119                                    SDVO_NAME(sdvo_priv));
1120                 }
1121
1122                 if (0)
1123                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1124                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1125         }
1126         return;
1127 }
1128
1129 static void intel_sdvo_save(struct drm_connector *connector)
1130 {
1131         struct drm_device *dev = connector->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         struct intel_output *intel_output = to_intel_output(connector);
1134         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1135         int o;
1136
1137         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1138         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1139
1140         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1141                 intel_sdvo_set_target_input(intel_output, true, false);
1142                 intel_sdvo_get_input_timing(intel_output,
1143                                             &sdvo_priv->save_input_dtd_1);
1144         }
1145
1146         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1147                 intel_sdvo_set_target_input(intel_output, false, true);
1148                 intel_sdvo_get_input_timing(intel_output,
1149                                             &sdvo_priv->save_input_dtd_2);
1150         }
1151
1152         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1153         {
1154                 u16  this_output = (1 << o);
1155                 if (sdvo_priv->caps.output_flags & this_output)
1156                 {
1157                         intel_sdvo_set_target_output(intel_output, this_output);
1158                         intel_sdvo_get_output_timing(intel_output,
1159                                                      &sdvo_priv->save_output_dtd[o]);
1160                 }
1161         }
1162         if (sdvo_priv->is_tv) {
1163                 /* XXX: Save TV format/enhancements. */
1164         }
1165
1166         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1167 }
1168
1169 static void intel_sdvo_restore(struct drm_connector *connector)
1170 {
1171         struct drm_device *dev = connector->dev;
1172         struct intel_output *intel_output = to_intel_output(connector);
1173         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1174         int o;
1175         int i;
1176         bool input1, input2;
1177         u8 status;
1178
1179         intel_sdvo_set_active_outputs(intel_output, 0);
1180
1181         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1182         {
1183                 u16  this_output = (1 << o);
1184                 if (sdvo_priv->caps.output_flags & this_output) {
1185                         intel_sdvo_set_target_output(intel_output, this_output);
1186                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1187                 }
1188         }
1189
1190         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1191                 intel_sdvo_set_target_input(intel_output, true, false);
1192                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1193         }
1194
1195         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1196                 intel_sdvo_set_target_input(intel_output, false, true);
1197                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1198         }
1199
1200         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1201
1202         if (sdvo_priv->is_tv) {
1203                 /* XXX: Restore TV format/enhancements. */
1204         }
1205
1206         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1207
1208         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1209         {
1210                 for (i = 0; i < 2; i++)
1211                         intel_wait_for_vblank(dev);
1212                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1213                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1214                         DRM_DEBUG("First %s output reported failure to sync\n",
1215                                    SDVO_NAME(sdvo_priv));
1216         }
1217
1218         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1219 }
1220
1221 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1222                                  struct drm_display_mode *mode)
1223 {
1224         struct intel_output *intel_output = to_intel_output(connector);
1225         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1226
1227         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1228                 return MODE_NO_DBLESCAN;
1229
1230         if (sdvo_priv->pixel_clock_min > mode->clock)
1231                 return MODE_CLOCK_LOW;
1232
1233         if (sdvo_priv->pixel_clock_max < mode->clock)
1234                 return MODE_CLOCK_HIGH;
1235
1236         return MODE_OK;
1237 }
1238
1239 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1240 {
1241         u8 status;
1242
1243         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1244         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1245         if (status != SDVO_CMD_STATUS_SUCCESS)
1246                 return false;
1247
1248         return true;
1249 }
1250
1251 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1252 {
1253         struct drm_connector *connector = NULL;
1254         struct intel_output *iout = NULL;
1255         struct intel_sdvo_priv *sdvo;
1256
1257         /* find the sdvo connector */
1258         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1259                 iout = to_intel_output(connector);
1260
1261                 if (iout->type != INTEL_OUTPUT_SDVO)
1262                         continue;
1263
1264                 sdvo = iout->dev_priv;
1265
1266                 if (sdvo->output_device == SDVOB && sdvoB)
1267                         return connector;
1268
1269                 if (sdvo->output_device == SDVOC && !sdvoB)
1270                         return connector;
1271
1272         }
1273
1274         return NULL;
1275 }
1276
1277 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1278 {
1279         u8 response[2];
1280         u8 status;
1281         struct intel_output *intel_output;
1282         DRM_DEBUG("\n");
1283
1284         if (!connector)
1285                 return 0;
1286
1287         intel_output = to_intel_output(connector);
1288
1289         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1290         status = intel_sdvo_read_response(intel_output, &response, 2);
1291
1292         if (response[0] !=0)
1293                 return 1;
1294
1295         return 0;
1296 }
1297
1298 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1299 {
1300         u8 response[2];
1301         u8 status;
1302         struct intel_output *intel_output = to_intel_output(connector);
1303
1304         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1305         intel_sdvo_read_response(intel_output, &response, 2);
1306
1307         if (on) {
1308                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1309                 status = intel_sdvo_read_response(intel_output, &response, 2);
1310
1311                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1312         } else {
1313                 response[0] = 0;
1314                 response[1] = 0;
1315                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1316         }
1317
1318         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1319         intel_sdvo_read_response(intel_output, &response, 2);
1320 }
1321
1322 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1323 {
1324         u8 response[2];
1325         u8 status;
1326         struct intel_output *intel_output = to_intel_output(connector);
1327
1328         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1329         status = intel_sdvo_read_response(intel_output, &response, 2);
1330
1331         DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
1332
1333         if (status != SDVO_CMD_STATUS_SUCCESS)
1334                 return connector_status_unknown;
1335
1336         if ((response[0] != 0) || (response[1] != 0))
1337                 return connector_status_connected;
1338         else
1339                 return connector_status_disconnected;
1340 }
1341
1342 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1343 {
1344         struct intel_output *intel_output = to_intel_output(connector);
1345         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1346
1347         /* set the bus switch and get the modes */
1348         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1349         intel_ddc_get_modes(intel_output);
1350
1351 #if 0
1352         struct drm_device *dev = encoder->dev;
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         /* Mac mini hack.  On this device, I get DDC through the analog, which
1355          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1356          * but it does load-detect as connected.  So, just steal the DDC bits
1357          * from analog when we fail at finding it the right way.
1358          */
1359         crt = xf86_config->output[0];
1360         intel_output = crt->driver_private;
1361         if (intel_output->type == I830_OUTPUT_ANALOG &&
1362             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1363                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1364                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1365                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1366         }
1367         if (edid_mon) {
1368                 xf86OutputSetEDID(output, edid_mon);
1369                 modes = xf86OutputGetEDIDModes(output);
1370         }
1371 #endif
1372 }
1373
1374 /**
1375  * This function checks the current TV format, and chooses a default if
1376  * it hasn't been set.
1377  */
1378 static void
1379 intel_sdvo_check_tv_format(struct intel_output *output)
1380 {
1381         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1382         struct intel_sdvo_tv_format format, unset;
1383         uint8_t status;
1384
1385         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1386         status = intel_sdvo_read_response(output, &format, sizeof(format));
1387         if (status != SDVO_CMD_STATUS_SUCCESS)
1388                 return;
1389
1390         memset(&unset, 0, sizeof(unset));
1391         if (memcmp(&format, &unset, sizeof(format))) {
1392                 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
1393                           SDVO_NAME(dev_priv));
1394
1395                 format.ntsc_m = true;
1396                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, NULL, 0);
1397                 status = intel_sdvo_read_response(output, NULL, 0);
1398         }
1399 }
1400
1401 /*
1402  * Set of SDVO TV modes.
1403  * Note!  This is in reply order (see loop in get_tv_modes).
1404  * XXX: all 60Hz refresh?
1405  */
1406 struct drm_display_mode sdvo_tv_modes[] = {
1407         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815680, 321, 384, 416,
1408                    200, 0, 232, 201, 233, 4196112, 0,
1409                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1410         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814080, 321, 384, 416,
1411                    240, 0, 272, 241, 273, 4196112, 0,
1412                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1413         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910080, 401, 464, 496,
1414                    300, 0, 332, 301, 333, 4196112, 0,
1415                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1416         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913280, 641, 704, 736,
1417                    350, 0, 382, 351, 383, 4196112, 0,
1418                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1419         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1420                    400, 0, 432, 401, 433, 4196112, 0,
1421                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1422         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1423                    400, 0, 432, 401, 433, 4196112, 0,
1424                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1425         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624000, 705, 768, 800,
1426                    480, 0, 512, 481, 513, 4196112, 0,
1427                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1428         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232000, 705, 768, 800,
1429                    576, 0, 608, 577, 609, 4196112, 0,
1430                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1431         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751680, 721, 784, 816,
1432                    350, 0, 382, 351, 383, 4196112, 0,
1433                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1434         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199680, 721, 784, 816,
1435                    400, 0, 432, 401, 433, 4196112, 0,
1436                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1437         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116480, 721, 784, 816,
1438                    480, 0, 512, 481, 513, 4196112, 0,
1439                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1440         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054080, 721, 784, 816,
1441                    540, 0, 572, 541, 573, 4196112, 0,
1442                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1443         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816640, 721, 784, 816,
1444                    576, 0, 608, 577, 609, 4196112, 0,
1445                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1446         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570560, 769, 832, 864,
1447                    576, 0, 608, 577, 609, 4196112, 0,
1448                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1449         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030080, 801, 864, 896,
1450                    600, 0, 632, 601, 633, 4196112, 0,
1451                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1452         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581760, 833, 896, 928,
1453                    624, 0, 656, 625, 657, 4196112, 0,
1454                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1455         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707040, 921, 984, 1016,
1456                    766, 0, 798, 767, 799, 4196112, 0,
1457                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1458         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827200, 1025, 1088, 1120,
1459                    768, 0, 800, 769, 801, 4196112, 0,
1460                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1461         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265920, 1281, 1344, 1376,
1462                    1024, 0, 1056, 1025, 1057, 4196112, 0,
1463                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1464 };
1465
1466 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1467 {
1468         struct intel_output *output = to_intel_output(connector);
1469         uint32_t reply = 0;
1470         uint8_t status;
1471         int i = 0;
1472
1473         intel_sdvo_check_tv_format(output);
1474
1475         /* Read the list of supported input resolutions for the selected TV
1476          * format.
1477          */
1478         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1479                              NULL, 0);
1480         status = intel_sdvo_read_response(output, &reply, 3);
1481         if (status != SDVO_CMD_STATUS_SUCCESS)
1482                 return;
1483
1484         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1485                 if (reply & (1 << i))
1486                         drm_mode_probed_add(connector, &sdvo_tv_modes[i]);
1487 }
1488
1489 static int intel_sdvo_get_modes(struct drm_connector *connector)
1490 {
1491         struct intel_output *output = to_intel_output(connector);
1492         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1493
1494         if (sdvo_priv->is_tv)
1495                 intel_sdvo_get_tv_modes(connector);
1496         else
1497                 intel_sdvo_get_ddc_modes(connector);
1498
1499         if (list_empty(&connector->probed_modes))
1500                 return 0;
1501         return 1;
1502 }
1503
1504 static void intel_sdvo_destroy(struct drm_connector *connector)
1505 {
1506         struct intel_output *intel_output = to_intel_output(connector);
1507
1508         if (intel_output->i2c_bus)
1509                 intel_i2c_destroy(intel_output->i2c_bus);
1510         drm_sysfs_connector_remove(connector);
1511         drm_connector_cleanup(connector);
1512         kfree(intel_output);
1513 }
1514
1515 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1516         .dpms = intel_sdvo_dpms,
1517         .mode_fixup = intel_sdvo_mode_fixup,
1518         .prepare = intel_encoder_prepare,
1519         .mode_set = intel_sdvo_mode_set,
1520         .commit = intel_encoder_commit,
1521 };
1522
1523 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1524         .save = intel_sdvo_save,
1525         .restore = intel_sdvo_restore,
1526         .detect = intel_sdvo_detect,
1527         .fill_modes = drm_helper_probe_single_connector_modes,
1528         .destroy = intel_sdvo_destroy,
1529 };
1530
1531 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1532         .get_modes = intel_sdvo_get_modes,
1533         .mode_valid = intel_sdvo_mode_valid,
1534         .best_encoder = intel_best_encoder,
1535 };
1536
1537 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1538 {
1539         drm_encoder_cleanup(encoder);
1540 }
1541
1542 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1543         .destroy = intel_sdvo_enc_destroy,
1544 };
1545
1546
1547 /**
1548  * Choose the appropriate DDC bus for control bus switch command for this
1549  * SDVO output based on the controlled output.
1550  *
1551  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1552  * outputs, then LVDS outputs.
1553  */
1554 static void
1555 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1556 {
1557         uint16_t mask = 0;
1558         unsigned int num_bits;
1559
1560         /* Make a mask of outputs less than or equal to our own priority in the
1561          * list.
1562          */
1563         switch (dev_priv->controlled_output) {
1564         case SDVO_OUTPUT_LVDS1:
1565                 mask |= SDVO_OUTPUT_LVDS1;
1566         case SDVO_OUTPUT_LVDS0:
1567                 mask |= SDVO_OUTPUT_LVDS0;
1568         case SDVO_OUTPUT_TMDS1:
1569                 mask |= SDVO_OUTPUT_TMDS1;
1570         case SDVO_OUTPUT_TMDS0:
1571                 mask |= SDVO_OUTPUT_TMDS0;
1572         case SDVO_OUTPUT_RGB1:
1573                 mask |= SDVO_OUTPUT_RGB1;
1574         case SDVO_OUTPUT_RGB0:
1575                 mask |= SDVO_OUTPUT_RGB0;
1576                 break;
1577         }
1578
1579         /* Count bits to find what number we are in the priority list. */
1580         mask &= dev_priv->caps.output_flags;
1581         num_bits = hweight16(mask);
1582         if (num_bits > 3) {
1583                 /* if more than 3 outputs, default to DDC bus 3 for now */
1584                 num_bits = 3;
1585         }
1586
1587         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1588         dev_priv->ddc_bus = 1 << num_bits;
1589 }
1590
1591 static bool
1592 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1593 {
1594         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1595         uint8_t status;
1596
1597         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1598
1599         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1600         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1601         if (status != SDVO_CMD_STATUS_SUCCESS)
1602                 return false;
1603         return true;
1604 }
1605
1606 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1607 {
1608         struct drm_connector *connector;
1609         struct intel_output *intel_output;
1610         struct intel_sdvo_priv *sdvo_priv;
1611         struct intel_i2c_chan *i2cbus = NULL;
1612         int connector_type;
1613         u8 ch[0x40];
1614         int i;
1615         int encoder_type, output_id;
1616
1617         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1618         if (!intel_output) {
1619                 return false;
1620         }
1621
1622         connector = &intel_output->base;
1623
1624         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1625                            DRM_MODE_CONNECTOR_Unknown);
1626         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1627         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1628         intel_output->type = INTEL_OUTPUT_SDVO;
1629
1630         connector->interlace_allowed = 0;
1631         connector->doublescan_allowed = 0;
1632
1633         /* setup the DDC bus. */
1634         if (output_device == SDVOB)
1635                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1636         else
1637                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1638
1639         if (!i2cbus)
1640                 goto err_connector;
1641
1642         sdvo_priv->i2c_bus = i2cbus;
1643
1644         if (output_device == SDVOB) {
1645                 output_id = 1;
1646                 sdvo_priv->i2c_bus->slave_addr = 0x38;
1647         } else {
1648                 output_id = 2;
1649                 sdvo_priv->i2c_bus->slave_addr = 0x39;
1650         }
1651
1652         sdvo_priv->output_device = output_device;
1653         intel_output->i2c_bus = i2cbus;
1654         intel_output->dev_priv = sdvo_priv;
1655
1656
1657         /* Read the regs to test if we can talk to the device */
1658         for (i = 0; i < 0x40; i++) {
1659                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1660                         DRM_DEBUG("No SDVO device found on SDVO%c\n",
1661                                   output_device == SDVOB ? 'B' : 'C');
1662                         goto err_i2c;
1663                 }
1664         }
1665
1666         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1667
1668         if (sdvo_priv->caps.output_flags &
1669             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1670                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1671                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1672                 else
1673                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1674
1675                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1676                 encoder_type = DRM_MODE_ENCODER_TMDS;
1677                 connector_type = DRM_MODE_CONNECTOR_DVID;
1678
1679                 if (intel_sdvo_get_supp_encode(intel_output,
1680                                                &sdvo_priv->encode) &&
1681                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1682                     sdvo_priv->is_hdmi) {
1683                         /* enable hdmi encoding mode if supported */
1684                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1685                         intel_sdvo_set_colorimetry(intel_output,
1686                                                    SDVO_COLORIMETRY_RGB256);
1687                         connector_type = DRM_MODE_CONNECTOR_HDMIA;
1688                 }
1689         }
1690         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1691         {
1692                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1693                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1694                 encoder_type = DRM_MODE_ENCODER_TVDAC;
1695                 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1696                 sdvo_priv->is_tv = true;
1697                 intel_output->needs_tv_clock = true;
1698         }
1699         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1700         {
1701                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1702                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1703                 encoder_type = DRM_MODE_ENCODER_DAC;
1704                 connector_type = DRM_MODE_CONNECTOR_VGA;
1705         }
1706         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1707         {
1708                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1709                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1710                 encoder_type = DRM_MODE_ENCODER_DAC;
1711                 connector_type = DRM_MODE_CONNECTOR_VGA;
1712         }
1713         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1714         {
1715                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1716                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1717                 encoder_type = DRM_MODE_ENCODER_LVDS;
1718                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1719         }
1720         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1721         {
1722                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1723                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1724                 encoder_type = DRM_MODE_ENCODER_LVDS;
1725                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1726         }
1727         else
1728         {
1729                 unsigned char bytes[2];
1730
1731                 sdvo_priv->controlled_output = 0;
1732                 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1733                 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
1734                           SDVO_NAME(sdvo_priv),
1735                           bytes[0], bytes[1]);
1736                 encoder_type = DRM_MODE_ENCODER_NONE;
1737                 connector_type = DRM_MODE_CONNECTOR_Unknown;
1738                 goto err_i2c;
1739         }
1740
1741         drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1742         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1743         connector->connector_type = connector_type;
1744
1745         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1746         drm_sysfs_connector_add(connector);
1747
1748         intel_sdvo_select_ddc_bus(sdvo_priv);
1749
1750         /* Set the input timing to the screen. Assume always input 0. */
1751         intel_sdvo_set_target_input(intel_output, true, false);
1752
1753         intel_sdvo_get_input_pixel_clock_range(intel_output,
1754                                                &sdvo_priv->pixel_clock_min,
1755                                                &sdvo_priv->pixel_clock_max);
1756
1757
1758         DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1759                   "clock range %dMHz - %dMHz, "
1760                   "input 1: %c, input 2: %c, "
1761                   "output 1: %c, output 2: %c\n",
1762                   SDVO_NAME(sdvo_priv),
1763                   sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1764                   sdvo_priv->caps.device_rev_id,
1765                   sdvo_priv->pixel_clock_min / 1000,
1766                   sdvo_priv->pixel_clock_max / 1000,
1767                   (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1768                   (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1769                   /* check currently supported outputs */
1770                   sdvo_priv->caps.output_flags &
1771                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1772                   sdvo_priv->caps.output_flags &
1773                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1774
1775         intel_output->ddc_bus = i2cbus;
1776
1777         return true;
1778
1779 err_i2c:
1780         intel_i2c_destroy(intel_output->i2c_bus);
1781 err_connector:
1782         drm_connector_cleanup(connector);
1783         kfree(intel_output);
1784
1785         return false;
1786 }